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freedreno/a4xx: add debug callback to emit
[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_gmem.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_draw.h"
36 #include "freedreno_state.h"
37 #include "freedreno_resource.h"
38
39 #include "fd4_gmem.h"
40 #include "fd4_context.h"
41 #include "fd4_draw.h"
42 #include "fd4_emit.h"
43 #include "fd4_program.h"
44 #include "fd4_format.h"
45 #include "fd4_zsa.h"
46
47 static void
48 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
49 struct pipe_surface **bufs, uint32_t *bases,
50 uint32_t bin_w, bool decode_srgb)
51 {
52 enum a4xx_tile_mode tile_mode;
53 unsigned i;
54
55 if (bin_w) {
56 tile_mode = 2;
57 } else {
58 tile_mode = TILE4_LINEAR;
59 }
60
61 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
62 enum a4xx_color_fmt format = 0;
63 enum a3xx_color_swap swap = WZYX;
64 bool srgb = false;
65 struct fd_resource *rsc = NULL;
66 struct fd_resource_slice *slice = NULL;
67 uint32_t stride = 0;
68 uint32_t base = 0;
69 uint32_t offset = 0;
70
71 if ((i < nr_bufs) && bufs[i]) {
72 struct pipe_surface *psurf = bufs[i];
73 enum pipe_format pformat = psurf->format;
74
75 rsc = fd_resource(psurf->texture);
76
77 /* In case we're drawing to Z32F_S8, the "color" actually goes to
78 * the stencil
79 */
80 if (rsc->stencil) {
81 rsc = rsc->stencil;
82 pformat = rsc->base.b.format;
83 bases++;
84 }
85
86 slice = fd_resource_slice(rsc, psurf->u.tex.level);
87 format = fd4_pipe2color(pformat);
88 swap = fd4_pipe2swap(pformat);
89
90 if (decode_srgb)
91 srgb = util_format_is_srgb(pformat);
92 else
93 pformat = util_format_linear(pformat);
94
95 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
96
97 offset = fd_resource_offset(rsc, psurf->u.tex.level,
98 psurf->u.tex.first_layer);
99
100 if (bin_w) {
101 stride = bin_w * rsc->cpp;
102
103 if (bases) {
104 base = bases[i];
105 }
106 } else {
107 stride = slice->pitch * rsc->cpp;
108 }
109 } else if ((i < nr_bufs) && bases) {
110 base = bases[i];
111 }
112
113 OUT_PKT0(ring, REG_A4XX_RB_MRT_BUF_INFO(i), 3);
114 OUT_RING(ring, A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
115 A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
116 A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
117 A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
118 COND(srgb, A4XX_RB_MRT_BUF_INFO_COLOR_SRGB));
119 if (bin_w || (i >= nr_bufs) || !bufs[i]) {
120 OUT_RING(ring, base);
121 OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(stride));
122 } else {
123 OUT_RELOCW(ring, rsc->bo, offset, 0, 0);
124 /* RB_MRT[i].CONTROL3.STRIDE not emitted by c2d..
125 * not sure if we need to skip it for bypass or
126 * not.
127 */
128 OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(0));
129 }
130 }
131 }
132
133 static bool
134 use_hw_binning(struct fd_context *ctx)
135 {
136 struct fd_gmem_stateobj *gmem = &ctx->gmem;
137 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
138
139 /* this seems to be a hw bug.. but this hack fixes piglit fbo-maxsize: */
140 if ((pfb->width > 4096) && (pfb->height > 4096))
141 return false;
142
143 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
144 }
145
146 /* transfer from gmem to system memory (ie. normal RAM) */
147
148 static void
149 emit_gmem2mem_surf(struct fd_context *ctx, bool stencil,
150 uint32_t base, struct pipe_surface *psurf)
151 {
152 struct fd_ringbuffer *ring = ctx->ring;
153 struct fd_resource *rsc = fd_resource(psurf->texture);
154 enum pipe_format pformat = psurf->format;
155 struct fd_resource_slice *slice;
156 uint32_t offset;
157
158 if (stencil) {
159 debug_assert(rsc->stencil);
160 rsc = rsc->stencil;
161 pformat = rsc->base.b.format;
162 }
163
164 slice = &rsc->slices[psurf->u.tex.level];
165 offset = fd_resource_offset(rsc, psurf->u.tex.level,
166 psurf->u.tex.first_layer);
167
168 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
169
170 OUT_PKT0(ring, REG_A4XX_RB_COPY_CONTROL, 4);
171 OUT_RING(ring, A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
172 A4XX_RB_COPY_CONTROL_MODE(RB_COPY_RESOLVE) |
173 A4XX_RB_COPY_CONTROL_GMEM_BASE(base));
174 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* RB_COPY_DEST_BASE */
175 OUT_RING(ring, A4XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->cpp));
176 OUT_RING(ring, A4XX_RB_COPY_DEST_INFO_TILE(TILE4_LINEAR) |
177 A4XX_RB_COPY_DEST_INFO_FORMAT(fd4_pipe2color(pformat)) |
178 A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
179 A4XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
180 A4XX_RB_COPY_DEST_INFO_SWAP(fd4_pipe2swap(pformat)));
181
182 fd4_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
183 DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
184 }
185
186 static void
187 fd4_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
188 {
189 struct fd4_context *fd4_ctx = fd4_context(ctx);
190 struct fd_gmem_stateobj *gmem = &ctx->gmem;
191 struct fd_ringbuffer *ring = ctx->ring;
192 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
193 struct fd4_emit emit = {
194 .debug = &ctx->debug,
195 .vtx = &fd4_ctx->solid_vbuf_state,
196 .prog = &ctx->solid_prog,
197 .key = {
198 .half_precision = true,
199 },
200 };
201
202 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
203 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
204
205 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
206 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
207 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
208 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
209 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
210 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
211 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
212 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
213 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
214 OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
215
216 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
217 OUT_RING(ring, 0xff000000 |
218 A4XX_RB_STENCILREFMASK_STENCILREF(0) |
219 A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
220 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
221 OUT_RING(ring, 0xff000000 |
222 A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
223 A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
224 A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0xff));
225
226 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
227 OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
228
229 fd_wfi(ctx, ring);
230
231 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
232 OUT_RING(ring, 0x80000); /* GRAS_CL_CLIP_CNTL */
233
234 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
235 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)pfb->width/2.0));
236 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)pfb->width/2.0));
237 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)pfb->height/2.0));
238 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)pfb->height/2.0));
239 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
240 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
241
242 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
243 OUT_RING(ring, A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
244 0xa); /* XXX */
245
246 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
247 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
248 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
249 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
250 A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
251
252 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
253 OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
254
255 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
256 OUT_RING(ring, 0x00000002);
257
258 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
259 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
260 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
261 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
262 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
263
264 OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
265 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
266 OUT_RING(ring, 0); /* ??? UNKNOWN_2209 */
267
268 fd4_program_emit(ring, &emit, 0, NULL);
269 fd4_emit_vertex_bufs(ring, &emit);
270
271 if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
272 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
273 if (!rsc->stencil || (ctx->resolve & FD_BUFFER_DEPTH))
274 emit_gmem2mem_surf(ctx, false, ctx->gmem.zsbuf_base[0], pfb->zsbuf);
275 if (rsc->stencil && (ctx->resolve & FD_BUFFER_STENCIL))
276 emit_gmem2mem_surf(ctx, true, ctx->gmem.zsbuf_base[1], pfb->zsbuf);
277 }
278
279 if (ctx->resolve & FD_BUFFER_COLOR) {
280 unsigned i;
281 for (i = 0; i < pfb->nr_cbufs; i++) {
282 if (!pfb->cbufs[i])
283 continue;
284 if (!(ctx->resolve & (PIPE_CLEAR_COLOR0 << i)))
285 continue;
286 emit_gmem2mem_surf(ctx, false, gmem->cbuf_base[i], pfb->cbufs[i]);
287 }
288 }
289
290 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
291 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
292 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
293 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
294 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
295 }
296
297 /* transfer from system memory to gmem */
298
299 static void
300 emit_mem2gmem_surf(struct fd_context *ctx, uint32_t *bases,
301 struct pipe_surface **bufs, uint32_t nr_bufs, uint32_t bin_w)
302 {
303 struct fd_ringbuffer *ring = ctx->ring;
304 struct pipe_surface *zsbufs[2];
305
306 emit_mrt(ring, nr_bufs, bufs, bases, bin_w, false);
307
308 if (bufs[0] && (bufs[0]->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)) {
309 /* The gmem_restore_tex logic will put the first buffer's stencil
310 * as color. Supply it with the proper information to make that
311 * happen.
312 */
313 zsbufs[0] = zsbufs[1] = bufs[0];
314 bufs = zsbufs;
315 nr_bufs = 2;
316 }
317
318 fd4_emit_gmem_restore_tex(ring, nr_bufs, bufs);
319
320 fd4_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
321 DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
322 }
323
324 static void
325 fd4_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
326 {
327 struct fd4_context *fd4_ctx = fd4_context(ctx);
328 struct fd_gmem_stateobj *gmem = &ctx->gmem;
329 struct fd_ringbuffer *ring = ctx->ring;
330 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
331 struct fd4_emit emit = {
332 .debug = &ctx->debug,
333 .vtx = &fd4_ctx->blit_vbuf_state,
334 .sprite_coord_enable = 1,
335 /* NOTE: They all use the same VP, this is for vtx bufs. */
336 .prog = &ctx->blit_prog[0],
337 .key = {
338 .half_precision = fd_half_precision(pfb),
339 },
340 .no_decode_srgb = true,
341 };
342 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
343 float x0, y0, x1, y1;
344 unsigned bin_w = tile->bin_w;
345 unsigned bin_h = tile->bin_h;
346 unsigned i;
347
348 /* write texture coordinates to vertexbuf: */
349 x0 = ((float)tile->xoff) / ((float)pfb->width);
350 x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
351 y0 = ((float)tile->yoff) / ((float)pfb->height);
352 y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
353
354 OUT_PKT3(ring, CP_MEM_WRITE, 5);
355 OUT_RELOCW(ring, fd_resource(fd4_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
356 OUT_RING(ring, fui(x0));
357 OUT_RING(ring, fui(y0));
358 OUT_RING(ring, fui(x1));
359 OUT_RING(ring, fui(y1));
360
361 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
362 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
363
364 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
365 OUT_RING(ring, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
366 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
367
368 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
369 OUT_RING(ring, A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
370 A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
371 A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
372 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
373 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
374 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
375 }
376
377 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
378 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
379 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
380 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
381 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
382 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
383 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
384 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
385 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
386
387 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
388 OUT_RING(ring, 0x8); /* XXX RB_RENDER_CONTROL */
389
390 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
391 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
392
393 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
394 OUT_RING(ring, 0x280000); /* XXX GRAS_CL_CLIP_CNTL */
395
396 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
397 OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0) |
398 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
399
400 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
401 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)bin_w/2.0));
402 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)bin_w/2.0));
403 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)bin_h/2.0));
404 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)bin_h/2.0));
405 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
406 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
407
408 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
409 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
410 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
411 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
412 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
413
414 OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
415 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
416 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
417 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
418 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
419
420 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
421 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
422 A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h));
423
424 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
425 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
426 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
427 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
428 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
429 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
430 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
431 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
432 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
433 OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
434
435 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
436 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
437 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
438 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
439 A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
440
441 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
442 OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST |
443 A4XX_PC_PRIM_VTX_CNTL_VAROUT(1));
444
445 OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
446 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
447 OUT_RING(ring, 0); /* ??? UNKNOWN_2209 */
448
449 fd4_emit_vertex_bufs(ring, &emit);
450
451 /* for gmem pitch/base calculations, we need to use the non-
452 * truncated tile sizes:
453 */
454 bin_w = gmem->bin_w;
455 bin_h = gmem->bin_h;
456
457 if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_COLOR)) {
458 emit.prog = &ctx->blit_prog[pfb->nr_cbufs - 1];
459 emit.fp = NULL; /* frag shader changed so clear cache */
460 fd4_program_emit(ring, &emit, pfb->nr_cbufs, pfb->cbufs);
461 emit_mem2gmem_surf(ctx, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs, bin_w);
462 }
463
464 if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
465 switch (pfb->zsbuf->format) {
466 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
467 case PIPE_FORMAT_Z32_FLOAT:
468 emit.prog = (pfb->zsbuf->format == PIPE_FORMAT_Z32_FLOAT) ?
469 &ctx->blit_z : &ctx->blit_zs;
470 emit.key.half_precision = false;
471
472 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
473 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_Z_ENABLE |
474 A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
475 A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS) |
476 A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE);
477
478 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
479 OUT_RING(ring, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE);
480
481 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
482 OUT_RING(ring, 0x80000); /* GRAS_CL_CLIP_CNTL */
483
484 break;
485 default:
486 /* Non-float can use a regular color write. It's split over 8-bit
487 * components, so half precision is always sufficient.
488 */
489 emit.prog = &ctx->blit_prog[0];
490 emit.key.half_precision = true;
491 break;
492 }
493 emit.fp = NULL; /* frag shader changed so clear cache */
494 fd4_program_emit(ring, &emit, 1, &pfb->zsbuf);
495 emit_mem2gmem_surf(ctx, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
496 }
497
498 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
499 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
500 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
501 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
502
503 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
504 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
505 A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h) |
506 0x00010000); /* XXX */
507 }
508
509 static void
510 patch_draws(struct fd_context *ctx, enum pc_di_vis_cull_mode vismode)
511 {
512 unsigned i;
513 for (i = 0; i < fd_patch_num_elements(&ctx->draw_patches); i++) {
514 struct fd_cs_patch *patch = fd_patch_element(&ctx->draw_patches, i);
515 *patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
516 }
517 util_dynarray_resize(&ctx->draw_patches, 0);
518 }
519
520 /* for rendering directly to system memory: */
521 static void
522 fd4_emit_sysmem_prep(struct fd_context *ctx)
523 {
524 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
525 struct fd_ringbuffer *ring = ctx->ring;
526
527 fd4_emit_restore(ctx);
528
529 OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
530 OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
531 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
532
533 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0, true);
534
535 /* setup scissor/offset for current tile: */
536 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
537 OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(0) |
538 A4XX_RB_BIN_OFFSET_Y(0));
539
540 OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
541 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
542 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
543 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
544 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
545
546 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
547 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(0) |
548 A4XX_RB_MODE_CONTROL_HEIGHT(0) |
549 0x00c00000); /* XXX */
550
551 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
552 OUT_RING(ring, 0x8);
553
554 patch_draws(ctx, IGNORE_VISIBILITY);
555 }
556
557 static void
558 update_vsc_pipe(struct fd_context *ctx)
559 {
560 struct fd4_context *fd4_ctx = fd4_context(ctx);
561 struct fd_ringbuffer *ring = ctx->ring;
562 int i;
563
564 OUT_PKT0(ring, REG_A4XX_VSC_SIZE_ADDRESS, 1);
565 OUT_RELOCW(ring, fd4_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
566
567 OUT_PKT0(ring, REG_A4XX_VSC_PIPE_CONFIG_REG(0), 8);
568 for (i = 0; i < 8; i++) {
569 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
570 OUT_RING(ring, A4XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
571 A4XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
572 A4XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
573 A4XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
574 }
575
576 OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(0), 8);
577 for (i = 0; i < 8; i++) {
578 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
579 if (!pipe->bo) {
580 pipe->bo = fd_bo_new(ctx->dev, 0x40000,
581 DRM_FREEDRENO_GEM_TYPE_KMEM);
582 }
583 OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE_DATA_ADDRESS[i] */
584 }
585
586 OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(0), 8);
587 for (i = 0; i < 8; i++) {
588 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
589 OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
590 }
591 }
592
593 static void
594 emit_binning_pass(struct fd_context *ctx)
595 {
596 struct fd_gmem_stateobj *gmem = &ctx->gmem;
597 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
598 struct fd_ringbuffer *ring = ctx->ring;
599 int i;
600
601 uint32_t x1 = gmem->minx;
602 uint32_t y1 = gmem->miny;
603 uint32_t x2 = gmem->minx + gmem->width - 1;
604 uint32_t y2 = gmem->miny + gmem->height - 1;
605
606 OUT_PKT0(ring, REG_A4XX_PC_BINNING_COMMAND, 1);
607 OUT_RING(ring, A4XX_PC_BINNING_COMMAND_BINNING_ENABLE);
608
609 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
610 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS) |
611 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
612 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
613 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
614
615 OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
616 OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
617 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
618
619 /* setup scissor/offset for whole screen: */
620 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
621 OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(x1) |
622 A4XX_RB_BIN_OFFSET_Y(y1));
623
624 OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
625 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
626 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
627 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
628 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
629
630 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
631 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
632 OUT_RING(ring, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR) |
633 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
634 }
635
636 /* emit IB to binning drawcmds: */
637 ctx->emit_ib(ring, ctx->binning_start, ctx->binning_end);
638
639 fd_reset_wfi(ctx);
640 fd_wfi(ctx, ring);
641
642 /* and then put stuff back the way it was: */
643
644 OUT_PKT0(ring, REG_A4XX_PC_BINNING_COMMAND, 1);
645 OUT_RING(ring, 0x00000000);
646
647 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
648 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
649 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
650 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
651 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
652
653 fd_event_write(ctx, ring, CACHE_FLUSH);
654 fd_wfi(ctx, ring);
655 }
656
657 /* before first tile */
658 static void
659 fd4_emit_tile_init(struct fd_context *ctx)
660 {
661 struct fd_ringbuffer *ring = ctx->ring;
662 struct fd_gmem_stateobj *gmem = &ctx->gmem;
663
664 fd4_emit_restore(ctx);
665
666 OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1);
667 OUT_RING(ring, A4XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
668 A4XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
669
670 update_vsc_pipe(ctx);
671
672 if (use_hw_binning(ctx)) {
673 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
674 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
675 A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h));
676
677 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
678 OUT_RING(ring, A4XX_RB_RENDER_CONTROL_BINNING_PASS |
679 A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
680 0x8);
681
682 /* emit hw binning pass: */
683 emit_binning_pass(ctx);
684
685 patch_draws(ctx, USE_VISIBILITY);
686 } else {
687 patch_draws(ctx, IGNORE_VISIBILITY);
688 }
689
690 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
691 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
692 A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h) |
693 A4XX_RB_MODE_CONTROL_ENABLE_GMEM);
694 }
695
696 /* before mem2gmem */
697 static void
698 fd4_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
699 {
700 struct fd_ringbuffer *ring = ctx->ring;
701 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
702 struct fd_gmem_stateobj *gmem = &ctx->gmem;
703
704 if (pfb->zsbuf) {
705 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
706 uint32_t cpp = rsc->cpp;
707
708 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_INFO, 3);
709 OUT_RING(ring, A4XX_RB_DEPTH_INFO_DEPTH_BASE(gmem->zsbuf_base[0]) |
710 A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd4_pipe2depth(pfb->zsbuf->format)));
711 OUT_RING(ring, A4XX_RB_DEPTH_PITCH(cpp * gmem->bin_w));
712 OUT_RING(ring, A4XX_RB_DEPTH_PITCH2(cpp * gmem->bin_w));
713
714 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_INFO, 2);
715 if (rsc->stencil) {
716 OUT_RING(ring, A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL |
717 A4XX_RB_STENCIL_INFO_STENCIL_BASE(gmem->zsbuf_base[1]));
718 OUT_RING(ring, A4XX_RB_STENCIL_PITCH(rsc->stencil->cpp * gmem->bin_w));
719 } else {
720 OUT_RING(ring, 0x00000000);
721 OUT_RING(ring, 0x00000000);
722 }
723 } else {
724 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_INFO, 3);
725 OUT_RING(ring, 0x00000000);
726 OUT_RING(ring, 0x00000000);
727 OUT_RING(ring, 0x00000000);
728
729 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_INFO, 2);
730 OUT_RING(ring, 0); /* RB_STENCIL_INFO */
731 OUT_RING(ring, 0); /* RB_STENCIL_PITCH */
732 }
733
734 OUT_PKT0(ring, REG_A4XX_GRAS_DEPTH_CONTROL, 1);
735 if (pfb->zsbuf) {
736 OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(
737 fd4_pipe2depth(pfb->zsbuf->format)));
738 } else {
739 OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(DEPTH4_NONE));
740 }
741
742 if (ctx->needs_rb_fbd) {
743 fd_wfi(ctx, ring);
744 OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
745 OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
746 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
747 ctx->needs_rb_fbd = false;
748 }
749 }
750
751 /* before IB to rendering cmds: */
752 static void
753 fd4_emit_tile_renderprep(struct fd_context *ctx, struct fd_tile *tile)
754 {
755 struct fd4_context *fd4_ctx = fd4_context(ctx);
756 struct fd_ringbuffer *ring = ctx->ring;
757 struct fd_gmem_stateobj *gmem = &ctx->gmem;
758 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
759
760 uint32_t x1 = tile->xoff;
761 uint32_t y1 = tile->yoff;
762 uint32_t x2 = tile->xoff + tile->bin_w - 1;
763 uint32_t y2 = tile->yoff + tile->bin_h - 1;
764
765 if (use_hw_binning(ctx)) {
766 struct fd_vsc_pipe *pipe = &ctx->pipe[tile->p];
767
768 assert(pipe->w * pipe->h);
769
770 fd_event_write(ctx, ring, HLSQ_FLUSH);
771 fd_wfi(ctx, ring);
772
773 OUT_PKT0(ring, REG_A4XX_PC_VSTREAM_CONTROL, 1);
774 OUT_RING(ring, A4XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
775 A4XX_PC_VSTREAM_CONTROL_N(tile->n));
776
777 OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
778 OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
779 OUT_RELOCW(ring, fd4_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
780 (tile->p * 4), 0, 0);
781 } else {
782 OUT_PKT0(ring, REG_A4XX_PC_VSTREAM_CONTROL, 1);
783 OUT_RING(ring, 0x00000000);
784 }
785
786 OUT_PKT3(ring, CP_SET_BIN, 3);
787 OUT_RING(ring, 0x00000000);
788 OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
789 OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
790
791 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem->cbuf_base, gmem->bin_w, true);
792
793 /* setup scissor/offset for current tile: */
794 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
795 OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(tile->xoff) |
796 A4XX_RB_BIN_OFFSET_Y(tile->yoff));
797
798 OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
799 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
800 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
801 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
802 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
803
804 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
805 OUT_RING(ring, 0x8);
806 }
807
808 void
809 fd4_gmem_init(struct pipe_context *pctx)
810 {
811 struct fd_context *ctx = fd_context(pctx);
812
813 ctx->emit_sysmem_prep = fd4_emit_sysmem_prep;
814 ctx->emit_tile_init = fd4_emit_tile_init;
815 ctx->emit_tile_prep = fd4_emit_tile_prep;
816 ctx->emit_tile_mem2gmem = fd4_emit_tile_mem2gmem;
817 ctx->emit_tile_renderprep = fd4_emit_tile_renderprep;
818 ctx->emit_tile_gmem2mem = fd4_emit_tile_gmem2mem;
819 }