src/gallium/drivers/freedreno/a4xx/fd4_gmem.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_inlines.h"
  33 #include "util/u_format.h"
  34
  35 #include "freedreno_draw.h"
  36 #include "freedreno_state.h"
  37 #include "freedreno_resource.h"
  38
  39 #include "fd4_gmem.h"
  40 #include "fd4_context.h"
  41 #include "fd4_draw.h"
  42 #include "fd4_emit.h"
  43 #include "fd4_program.h"
  44 #include "fd4_util.h"
  45 #include "fd4_zsa.h"
  46
  47 static const struct ir3_shader_key key = {
  48                 // XXX should set this based on render target format!  We don't
  49                 // want half_precision if float32 render target!!!
  50                 .half_precision = true,
  51 };
  52
  53 static void
  54 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
  55                 struct pipe_surface **bufs, uint32_t *bases, uint32_t bin_w)
  56 {
  57         unsigned i;
  58
  59         for (i = 0; i < 8; i++) {
  60                 enum a4xx_color_fmt format = 0;
  61                 enum a3xx_color_swap swap = WZYX;
  62                 struct fd_resource *rsc = NULL;
  63                 struct fd_resource_slice *slice = NULL;
  64                 uint32_t stride = 0;
  65                 uint32_t base = 0;
  66                 uint32_t layer_offset = 0;
  67
  68                 if ((i < nr_bufs) && bufs[i]) {
  69                         struct pipe_surface *psurf = bufs[i];
  70
  71                         rsc = fd_resource(psurf->texture);
  72                         slice = &rsc->slices[psurf->u.tex.level];
  73                         format = fd4_pipe2color(psurf->format);
  74                         swap = fd4_pipe2swap(psurf->format);
  75
  76                         debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
  77
  78                         layer_offset = slice->size0 * psurf->u.tex.first_layer;
  79
  80                         if (bin_w) {
  81                                 stride = bin_w * rsc->cpp;
  82
  83                                 if (bases) {
  84                                         base = bases[i];
  85                                 }
  86                         } else {
  87                                 stride = slice->pitch * rsc->cpp;
  88                         }
  89                 }
  90
  91                 OUT_PKT0(ring, REG_A4XX_RB_MRT_BUF_INFO(i), 3);
  92                 OUT_RING(ring, A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
  93                                 0x80 | /* XXX not on gmem2mem?? tile-mode? */
  94                                 A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
  95                                 A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap));
  96                 if (bin_w || (i >= nr_bufs)) {
  97                         OUT_RING(ring, base);
  98                 } else {
  99                         OUT_RELOCW(ring, rsc->bo,
 100                                         slice->offset + layer_offset, 0, -1);
 101                 }
 102                 OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(stride));
 103         }
 104 }
 105
 106 static uint32_t
 107 depth_base(struct fd_context *ctx)
 108 {
 109         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 110         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 111         uint32_t cpp = 4;
 112         if (pfb->cbufs[0]) {
 113                 struct fd_resource *rsc =
 114                                 fd_resource(pfb->cbufs[0]->texture);
 115                 cpp = rsc->cpp;
 116         }
 117         return align(gmem->bin_w * gmem->bin_h * cpp, 0x4000);
 118 }
 119
 120 /* transfer from gmem to system memory (ie. normal RAM) */
 121
 122 static void
 123 emit_gmem2mem_surf(struct fd_context *ctx,
 124                 uint32_t base, struct pipe_surface *psurf)
 125 {
 126         struct fd_ringbuffer *ring = ctx->ring;
 127         struct fd_resource *rsc = fd_resource(psurf->texture);
 128         struct fd_resource_slice *slice = &rsc->slices[psurf->u.tex.level];
 129
 130         OUT_PKT0(ring, REG_A4XX_RB_COPY_CONTROL, 4);
 131         OUT_RING(ring, A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
 132                         A4XX_RB_COPY_CONTROL_MODE(RB_COPY_RESOLVE) |
 133                         A4XX_RB_COPY_CONTROL_GMEM_BASE(base));
 134         OUT_RELOCW(ring, rsc->bo, slice->offset, 0, 0);   /* RB_COPY_DEST_BASE */
 135         OUT_RING(ring, A4XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->cpp));
 136         OUT_RING(ring, A4XX_RB_COPY_DEST_INFO_TILE(TILE4_LINEAR) |
 137                         A4XX_RB_COPY_DEST_INFO_FORMAT(fd4_pipe2color(psurf->format)) |
 138                         A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
 139                         A4XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
 140                         A4XX_RB_COPY_DEST_INFO_SWAP(fd4_pipe2swap(psurf->format)));
 141
 142         fd4_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 143                         DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
 144 }
 145
 146 static void
 147 fd4_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
 148 {
 149         struct fd4_context *fd4_ctx = fd4_context(ctx);
 150         struct fd_ringbuffer *ring = ctx->ring;
 151         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 152         struct fd4_emit emit = {
 153                         .vtx = &fd4_ctx->solid_vbuf_state,
 154                         .prog = &ctx->solid_prog,
 155                         .key = key,
 156                         .format = fd4_emit_format(pfb->cbufs[0]),
 157         };
 158
 159         OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 160         OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 161
 162         OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 1);
 163         OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 164                         A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 165                         A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 166                         A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 167                         A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 168                         A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 169                         A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 170                         A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 171
 172         OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
 173         OUT_RING(ring, 0xff000000 |
 174                         A4XX_RB_STENCILREFMASK_STENCILREF(0) |
 175                         A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
 176                         A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 177         OUT_RING(ring, 0xff000000 |
 178                         A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
 179                         A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
 180                         A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0xff));
 181
 182         OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
 183         OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
 184
 185         fd_wfi(ctx, ring);
 186
 187         OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
 188         OUT_RING(ring, 0x80000);      /* GRAS_CL_CLIP_CNTL */
 189
 190         OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
 191         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)pfb->width/2.0));
 192         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)pfb->width/2.0));
 193         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)pfb->height/2.0));
 194         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)pfb->height/2.0));
 195         OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
 196         OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
 197
 198         OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
 199         OUT_RING(ring, A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
 200                         0xa);       /* XXX */
 201
 202         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 203         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
 204                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 205                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 206                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
 207
 208         OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
 209         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 210
 211         OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
 212         OUT_RING(ring, 0x00000002);
 213
 214         OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
 215         OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
 216                         A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
 217         OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
 218                         A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
 219
 220         OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
 221         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 222         OUT_RING(ring, 0);            /* ??? UNKNOWN_2209 */
 223
 224         fd4_program_emit(ring, &emit);
 225         fd4_emit_vertex_bufs(ring, &emit);
 226
 227         if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
 228                 uint32_t base = depth_base(ctx);
 229                 emit_gmem2mem_surf(ctx, base, pfb->zsbuf);
 230         }
 231
 232         if (ctx->resolve & FD_BUFFER_COLOR) {
 233                 emit_gmem2mem_surf(ctx, 0, pfb->cbufs[0]);
 234         }
 235
 236         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 237         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 238                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 239                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 240                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 241 }
 242
 243 /* transfer from system memory to gmem */
 244
 245 static void
 246 emit_mem2gmem_surf(struct fd_context *ctx, uint32_t base,
 247                 struct pipe_surface *psurf, uint32_t bin_w)
 248 {
 249         struct fd_ringbuffer *ring = ctx->ring;
 250
 251         emit_mrt(ring, 1, &psurf, &base, bin_w);
 252
 253         fd4_emit_gmem_restore_tex(ring, psurf);
 254
 255         fd4_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 256                         DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
 257 }
 258
 259 static void
 260 fd4_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
 261 {
 262         struct fd4_context *fd4_ctx = fd4_context(ctx);
 263         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 264         struct fd_ringbuffer *ring = ctx->ring;
 265         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 266         struct fd4_emit emit = {
 267                         .vtx = &fd4_ctx->blit_vbuf_state,
 268                         .prog = &ctx->blit_prog,
 269                         .key = key,
 270                         .format = fd4_emit_format(pfb->cbufs[0]),
 271         };
 272         float x0, y0, x1, y1;
 273         unsigned bin_w = tile->bin_w;
 274         unsigned bin_h = tile->bin_h;
 275         unsigned i;
 276
 277         /* write texture coordinates to vertexbuf: */
 278         x0 = ((float)tile->xoff) / ((float)pfb->width);
 279         x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
 280         y0 = ((float)tile->yoff) / ((float)pfb->height);
 281         y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
 282
 283         OUT_PKT3(ring, CP_MEM_WRITE, 5);
 284         OUT_RELOCW(ring, fd_resource(fd4_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
 285         OUT_RING(ring, fui(x0));
 286         OUT_RING(ring, fui(y0));
 287         OUT_RING(ring, fui(x1));
 288         OUT_RING(ring, fui(y1));
 289
 290         for (i = 0; i < 8; i++) {
 291                 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
 292                 OUT_RING(ring, A4XX_RB_MRT_CONTROL_FASTCLEAR |
 293                                 A4XX_RB_MRT_CONTROL_B11 |
 294                                 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
 295
 296                 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
 297                 OUT_RING(ring, A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
 298                                 A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 299                                 A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
 300                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
 301                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 302                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
 303         }
 304
 305         OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
 306         OUT_RING(ring, 0x8);          /* XXX RB_RENDER_CONTROL */
 307
 308         OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 309         OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
 310
 311         OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
 312         OUT_RING(ring, 0x280000);     /* XXX GRAS_CL_CLIP_CNTL */
 313
 314         OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
 315         OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0) |
 316                         A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
 317
 318         OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
 319         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)bin_w/2.0));
 320         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)bin_w/2.0));
 321         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)bin_h/2.0));
 322         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)bin_h/2.0));
 323         OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
 324         OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
 325
 326         OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
 327         OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
 328                         A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
 329         OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
 330                         A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
 331
 332         OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 333         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
 334                         A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
 335         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
 336                         A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
 337
 338         OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
 339         OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
 340                         A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h));
 341
 342         OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 1);
 343         OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
 344                         A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 345                         A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 346                         A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 347                         A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
 348                         A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 349                         A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 350                         A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 351
 352         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 353         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 354                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 355                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 356                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
 357
 358         OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
 359         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST |
 360                         A4XX_PC_PRIM_VTX_CNTL_VAROUT);
 361
 362         OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
 363         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 364         OUT_RING(ring, 0);            /* ??? UNKNOWN_2209 */
 365
 366         fd4_program_emit(ring, &emit);
 367         fd4_emit_vertex_bufs(ring, &emit);
 368
 369         /* for gmem pitch/base calculations, we need to use the non-
 370          * truncated tile sizes:
 371          */
 372         bin_w = gmem->bin_w;
 373         bin_h = gmem->bin_h;
 374
 375         if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
 376                 emit_mem2gmem_surf(ctx, depth_base(ctx), pfb->zsbuf, bin_w);
 377
 378         if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_COLOR))
 379                 emit_mem2gmem_surf(ctx, 0, pfb->cbufs[0], bin_w);
 380
 381         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 382         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 383                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 384                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 385
 386         OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
 387         OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
 388                         A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h) |
 389                         0x00010000);  /* XXX */
 390 }
 391
 392 static void
 393 patch_draws(struct fd_context *ctx, enum pc_di_vis_cull_mode vismode)
 394 {
 395         unsigned i;
 396         for (i = 0; i < fd_patch_num_elements(&ctx->draw_patches); i++) {
 397                 struct fd_cs_patch *patch = fd_patch_element(&ctx->draw_patches, i);
 398                 *patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
 399         }
 400         util_dynarray_resize(&ctx->draw_patches, 0);
 401 }
 402
 403 static void
 404 patch_rbrc(struct fd_context *ctx, uint32_t val)
 405 {
 406         struct fd4_context *fd4_ctx = fd4_context(ctx);
 407         unsigned i;
 408         for (i = 0; i < fd_patch_num_elements(&fd4_ctx->rbrc_patches); i++) {
 409                 struct fd_cs_patch *patch = fd_patch_element(&fd4_ctx->rbrc_patches, i);
 410                 *patch->cs = patch->val | val;
 411         }
 412         util_dynarray_resize(&fd4_ctx->rbrc_patches, 0);
 413 }
 414
 415 static void
 416 update_vsc_pipe(struct fd_context *ctx)
 417 {
 418         struct fd4_context *fd4_ctx = fd4_context(ctx);
 419         struct fd_ringbuffer *ring = ctx->ring;
 420         int i;
 421
 422         OUT_PKT0(ring, REG_A4XX_VSC_SIZE_ADDRESS, 1);
 423         OUT_RELOCW(ring, fd4_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
 424
 425         OUT_PKT0(ring, REG_A4XX_VSC_PIPE_CONFIG_REG(0), 8);
 426         for (i = 0; i < 8; i++) {
 427                 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
 428                 OUT_RING(ring, A4XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
 429                                 A4XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
 430                                 A4XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
 431                                 A4XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
 432         }
 433
 434         OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(0), 8);
 435         for (i = 0; i < 8; i++) {
 436                 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
 437                 if (!pipe->bo) {
 438                         pipe->bo = fd_bo_new(ctx->dev, 0x40000,
 439                                         DRM_FREEDRENO_GEM_TYPE_KMEM);
 440                 }
 441                 OUT_RELOCW(ring, pipe->bo, 0, 0, 0);       /* VSC_PIPE_DATA_ADDRESS[i] */
 442         }
 443
 444         OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(0), 8);
 445         for (i = 0; i < 8; i++) {
 446                 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
 447                 OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
 448         }
 449 }
 450
 451 /* before first tile */
 452 static void
 453 fd4_emit_tile_init(struct fd_context *ctx)
 454 {
 455         struct fd_ringbuffer *ring = ctx->ring;
 456         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 457         uint32_t rb_render_control;
 458
 459         fd4_emit_restore(ctx);
 460
 461         OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1);
 462         OUT_RING(ring, A4XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
 463                         A4XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
 464
 465         OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
 466         OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
 467                         A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h) |
 468                         0x00010000);  /* XXX */
 469
 470         update_vsc_pipe(ctx);
 471         patch_draws(ctx, IGNORE_VISIBILITY);
 472
 473         rb_render_control = 0; // XXX or BINNING_PASS.. but maybe we can emit only from gmem
 474         patch_rbrc(ctx, rb_render_control);
 475 }
 476
 477 /* before mem2gmem */
 478 static void
 479 fd4_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
 480 {
 481         struct fd_ringbuffer *ring = ctx->ring;
 482         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 483         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 484         uint32_t reg;
 485
 486         OUT_PKT0(ring, REG_A4XX_RB_DEPTH_INFO, 3);
 487         reg = A4XX_RB_DEPTH_INFO_DEPTH_BASE(depth_base(ctx));
 488         if (pfb->zsbuf) {
 489                 reg |= A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
 490         }
 491         OUT_RING(ring, reg);
 492         if (pfb->zsbuf) {
 493                 OUT_RING(ring, A4XX_RB_DEPTH_PITCH(gmem->bin_w));
 494                 OUT_RING(ring, A4XX_RB_DEPTH_PITCH2(gmem->bin_w));
 495         } else {
 496                 OUT_RING(ring, 0x00000000);
 497                 OUT_RING(ring, 0x00000000);
 498         }
 499
 500         if (pfb->zsbuf) {
 501                 OUT_PKT0(ring, REG_A4XX_GRAS_DEPTH_CONTROL, 1);
 502                 OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(
 503                                 fd_pipe2depth(pfb->zsbuf->format)));
 504         }
 505
 506         if (ctx->needs_rb_fbd) {
 507                 fd_wfi(ctx, ring);
 508                 OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
 509                 OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
 510                                 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
 511                 ctx->needs_rb_fbd = false;
 512         }
 513 }
 514
 515 /* before IB to rendering cmds: */
 516 static void
 517 fd4_emit_tile_renderprep(struct fd_context *ctx, struct fd_tile *tile)
 518 {
 519         struct fd_ringbuffer *ring = ctx->ring;
 520         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 521         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 522
 523         uint32_t x1 = tile->xoff;
 524         uint32_t y1 = tile->yoff;
 525         uint32_t x2 = tile->xoff + tile->bin_w - 1;
 526         uint32_t y2 = tile->yoff + tile->bin_h - 1;
 527
 528         OUT_PKT3(ring, CP_SET_BIN, 3);
 529         OUT_RING(ring, 0x00000000);
 530         OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
 531         OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
 532
 533         emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, gmem->bin_w);
 534
 535         /* setup scissor/offset for current tile: */
 536         OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
 537         OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(tile->xoff) |
 538                         A4XX_RB_BIN_OFFSET_Y(tile->yoff));
 539
 540         OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 541         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
 542                         A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
 543         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
 544                         A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
 545 }
 546
 547 void
 548 fd4_gmem_init(struct pipe_context *pctx)
 549 {
 550         struct fd_context *ctx = fd_context(pctx);
 551
 552         ctx->emit_tile_init = fd4_emit_tile_init;
 553         ctx->emit_tile_prep = fd4_emit_tile_prep;
 554         ctx->emit_tile_mem2gmem = fd4_emit_tile_mem2gmem;
 555         ctx->emit_tile_renderprep = fd4_emit_tile_renderprep;
 556         ctx->emit_tile_gmem2mem = fd4_emit_tile_gmem2mem;
 557 }