src/gallium/drivers/freedreno/a4xx/fd4_gmem.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_inlines.h"
  33 #include "util/u_format.h"
  34
  35 #include "freedreno_draw.h"
  36 #include "freedreno_state.h"
  37 #include "freedreno_resource.h"
  38
  39 #include "fd4_gmem.h"
  40 #include "fd4_context.h"
  41 #include "fd4_draw.h"
  42 #include "fd4_emit.h"
  43 #include "fd4_program.h"
  44 #include "fd4_format.h"
  45 #include "fd4_zsa.h"
  46
  47 static const struct ir3_shader_key key = {
  48                 // XXX should set this based on render target format!  We don't
  49                 // want half_precision if float32 render target!!!
  50                 .half_precision = true,
  51 };
  52
  53 static void
  54 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
  55                 struct pipe_surface **bufs, uint32_t *bases, uint32_t bin_w)
  56 {
  57         unsigned i;
  58
  59         for (i = 0; i < 8; i++) {
  60                 enum a4xx_color_fmt format = 0;
  61                 enum a3xx_color_swap swap = WZYX;
  62                 struct fd_resource *rsc = NULL;
  63                 struct fd_resource_slice *slice = NULL;
  64                 uint32_t stride = 0;
  65                 uint32_t base = 0;
  66                 uint32_t layer_offset = 0;
  67
  68                 if ((i < nr_bufs) && bufs[i]) {
  69                         struct pipe_surface *psurf = bufs[i];
  70
  71                         rsc = fd_resource(psurf->texture);
  72                         slice = &rsc->slices[psurf->u.tex.level];
  73                         format = fd4_pipe2color(psurf->format);
  74                         swap = fd4_pipe2swap(psurf->format);
  75
  76                         debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
  77
  78                         layer_offset = slice->size0 * psurf->u.tex.first_layer;
  79
  80                         if (bin_w) {
  81                                 stride = bin_w * rsc->cpp;
  82
  83                                 if (bases) {
  84                                         base = bases[i];
  85                                 }
  86                         } else {
  87                                 stride = slice->pitch * rsc->cpp;
  88                         }
  89                 }
  90
  91                 OUT_PKT0(ring, REG_A4XX_RB_MRT_BUF_INFO(i), 3);
  92                 OUT_RING(ring, A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
  93                                 0x80 | /* XXX not on gmem2mem?? tile-mode? */
  94                                 A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
  95                                 A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap));
  96                 if (bin_w || (i >= nr_bufs)) {
  97                         OUT_RING(ring, base);
  98                 } else {
  99                         OUT_RELOCW(ring, rsc->bo,
 100                                         slice->offset + layer_offset, 0, -1);
 101                 }
 102                 OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(stride));
 103         }
 104 }
 105
 106 static uint32_t
 107 depth_base(struct fd_context *ctx)
 108 {
 109         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 110         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 111         uint32_t cpp = 4;
 112         if (pfb->cbufs[0]) {
 113                 struct fd_resource *rsc =
 114                                 fd_resource(pfb->cbufs[0]->texture);
 115                 cpp = rsc->cpp;
 116         }
 117         return align(gmem->bin_w * gmem->bin_h * cpp, 0x4000);
 118 }
 119
 120 /* transfer from gmem to system memory (ie. normal RAM) */
 121
 122 static void
 123 emit_gmem2mem_surf(struct fd_context *ctx,
 124                 uint32_t base, struct pipe_surface *psurf)
 125 {
 126         struct fd_ringbuffer *ring = ctx->ring;
 127         struct fd_resource *rsc = fd_resource(psurf->texture);
 128         struct fd_resource_slice *slice = &rsc->slices[psurf->u.tex.level];
 129
 130         OUT_PKT0(ring, REG_A4XX_RB_COPY_CONTROL, 4);
 131         OUT_RING(ring, A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
 132                         A4XX_RB_COPY_CONTROL_MODE(RB_COPY_RESOLVE) |
 133                         A4XX_RB_COPY_CONTROL_GMEM_BASE(base));
 134         OUT_RELOCW(ring, rsc->bo, slice->offset, 0, 0);   /* RB_COPY_DEST_BASE */
 135         OUT_RING(ring, A4XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->cpp));
 136         OUT_RING(ring, A4XX_RB_COPY_DEST_INFO_TILE(TILE4_LINEAR) |
 137                         A4XX_RB_COPY_DEST_INFO_FORMAT(fd4_pipe2color(psurf->format)) |
 138                         A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
 139                         A4XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
 140                         A4XX_RB_COPY_DEST_INFO_SWAP(fd4_pipe2swap(psurf->format)));
 141
 142         fd4_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 143                         DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
 144 }
 145
 146 static void
 147 fd4_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
 148 {
 149         struct fd4_context *fd4_ctx = fd4_context(ctx);
 150         struct fd_ringbuffer *ring = ctx->ring;
 151         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 152         struct fd4_emit emit = {
 153                         .vtx = &fd4_ctx->solid_vbuf_state,
 154                         .prog = &ctx->solid_prog,
 155                         .key = key,
 156                         .format = fd4_emit_format(pfb->cbufs[0]),
 157         };
 158
 159         OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 160         OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 161
 162         OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
 163         OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 164                         A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 165                         A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 166                         A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 167                         A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 168                         A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 169                         A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 170                         A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 171         OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
 172
 173         OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
 174         OUT_RING(ring, 0xff000000 |
 175                         A4XX_RB_STENCILREFMASK_STENCILREF(0) |
 176                         A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
 177                         A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 178         OUT_RING(ring, 0xff000000 |
 179                         A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
 180                         A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
 181                         A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0xff));
 182
 183         OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
 184         OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
 185
 186         fd_wfi(ctx, ring);
 187
 188         OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
 189         OUT_RING(ring, 0x80000);      /* GRAS_CL_CLIP_CNTL */
 190
 191         OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
 192         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)pfb->width/2.0));
 193         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)pfb->width/2.0));
 194         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)pfb->height/2.0));
 195         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)pfb->height/2.0));
 196         OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
 197         OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
 198
 199         OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
 200         OUT_RING(ring, A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
 201                         0xa);       /* XXX */
 202
 203         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 204         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
 205                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 206                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 207                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
 208
 209         OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
 210         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 211
 212         OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
 213         OUT_RING(ring, 0x00000002);
 214
 215         OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
 216         OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
 217                         A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
 218         OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
 219                         A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
 220
 221         OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
 222         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 223         OUT_RING(ring, 0);            /* ??? UNKNOWN_2209 */
 224
 225         fd4_program_emit(ring, &emit);
 226         fd4_emit_vertex_bufs(ring, &emit);
 227
 228         if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
 229                 uint32_t base = depth_base(ctx);
 230                 emit_gmem2mem_surf(ctx, base, pfb->zsbuf);
 231         }
 232
 233         if (ctx->resolve & FD_BUFFER_COLOR) {
 234                 emit_gmem2mem_surf(ctx, 0, pfb->cbufs[0]);
 235         }
 236
 237         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 238         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 239                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 240                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 241                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 242 }
 243
 244 /* transfer from system memory to gmem */
 245
 246 static void
 247 emit_mem2gmem_surf(struct fd_context *ctx, uint32_t base,
 248                 struct pipe_surface *psurf, uint32_t bin_w)
 249 {
 250         struct fd_ringbuffer *ring = ctx->ring;
 251
 252         emit_mrt(ring, 1, &psurf, &base, bin_w);
 253
 254         fd4_emit_gmem_restore_tex(ring, psurf);
 255
 256         fd4_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 257                         DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
 258 }
 259
 260 static void
 261 fd4_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
 262 {
 263         struct fd4_context *fd4_ctx = fd4_context(ctx);
 264         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 265         struct fd_ringbuffer *ring = ctx->ring;
 266         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 267         struct fd4_emit emit = {
 268                         .vtx = &fd4_ctx->blit_vbuf_state,
 269                         .prog = &ctx->blit_prog,
 270                         .key = key,
 271                         .format = fd4_emit_format(pfb->cbufs[0]),
 272         };
 273         float x0, y0, x1, y1;
 274         unsigned bin_w = tile->bin_w;
 275         unsigned bin_h = tile->bin_h;
 276         unsigned i;
 277
 278         /* write texture coordinates to vertexbuf: */
 279         x0 = ((float)tile->xoff) / ((float)pfb->width);
 280         x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
 281         y0 = ((float)tile->yoff) / ((float)pfb->height);
 282         y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
 283
 284         OUT_PKT3(ring, CP_MEM_WRITE, 5);
 285         OUT_RELOCW(ring, fd_resource(fd4_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
 286         OUT_RING(ring, fui(x0));
 287         OUT_RING(ring, fui(y0));
 288         OUT_RING(ring, fui(x1));
 289         OUT_RING(ring, fui(y1));
 290
 291         for (i = 0; i < 8; i++) {
 292                 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
 293                 OUT_RING(ring, A4XX_RB_MRT_CONTROL_FASTCLEAR |
 294                                 A4XX_RB_MRT_CONTROL_B11 |
 295                                 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
 296
 297                 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
 298                 OUT_RING(ring, A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
 299                                 A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 300                                 A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
 301                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
 302                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 303                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
 304         }
 305
 306         OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
 307         OUT_RING(ring, 0x8);          /* XXX RB_RENDER_CONTROL */
 308
 309         OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 310         OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
 311
 312         OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
 313         OUT_RING(ring, 0x280000);     /* XXX GRAS_CL_CLIP_CNTL */
 314
 315         OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
 316         OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0) |
 317                         A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
 318
 319         OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
 320         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)bin_w/2.0));
 321         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)bin_w/2.0));
 322         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)bin_h/2.0));
 323         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)bin_h/2.0));
 324         OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
 325         OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
 326
 327         OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
 328         OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
 329                         A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
 330         OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
 331                         A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
 332
 333         OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 334         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
 335                         A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
 336         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
 337                         A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
 338
 339         OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
 340         OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
 341                         A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h));
 342
 343         OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
 344         OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
 345                         A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 346                         A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 347                         A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 348                         A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
 349                         A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 350                         A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 351                         A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 352         OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
 353
 354         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 355         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 356                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 357                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 358                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
 359
 360         OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
 361         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST |
 362                         A4XX_PC_PRIM_VTX_CNTL_VAROUT);
 363
 364         OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
 365         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 366         OUT_RING(ring, 0);            /* ??? UNKNOWN_2209 */
 367
 368         fd4_program_emit(ring, &emit);
 369         fd4_emit_vertex_bufs(ring, &emit);
 370
 371         /* for gmem pitch/base calculations, we need to use the non-
 372          * truncated tile sizes:
 373          */
 374         bin_w = gmem->bin_w;
 375         bin_h = gmem->bin_h;
 376
 377         if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
 378                 emit_mem2gmem_surf(ctx, depth_base(ctx), pfb->zsbuf, bin_w);
 379
 380         if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_COLOR))
 381                 emit_mem2gmem_surf(ctx, 0, pfb->cbufs[0], bin_w);
 382
 383         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 384         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 385                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 386                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 387
 388         OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
 389         OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
 390                         A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h) |
 391                         0x00010000);  /* XXX */
 392 }
 393
 394 static void
 395 patch_draws(struct fd_context *ctx, enum pc_di_vis_cull_mode vismode)
 396 {
 397         unsigned i;
 398         for (i = 0; i < fd_patch_num_elements(&ctx->draw_patches); i++) {
 399                 struct fd_cs_patch *patch = fd_patch_element(&ctx->draw_patches, i);
 400                 *patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
 401         }
 402         util_dynarray_resize(&ctx->draw_patches, 0);
 403 }
 404
 405 static void
 406 patch_rbrc(struct fd_context *ctx, uint32_t val)
 407 {
 408         struct fd4_context *fd4_ctx = fd4_context(ctx);
 409         unsigned i;
 410         for (i = 0; i < fd_patch_num_elements(&fd4_ctx->rbrc_patches); i++) {
 411                 struct fd_cs_patch *patch = fd_patch_element(&fd4_ctx->rbrc_patches, i);
 412                 *patch->cs = patch->val | val;
 413         }
 414         util_dynarray_resize(&fd4_ctx->rbrc_patches, 0);
 415 }
 416
 417 static void
 418 update_vsc_pipe(struct fd_context *ctx)
 419 {
 420         struct fd4_context *fd4_ctx = fd4_context(ctx);
 421         struct fd_ringbuffer *ring = ctx->ring;
 422         int i;
 423
 424         OUT_PKT0(ring, REG_A4XX_VSC_SIZE_ADDRESS, 1);
 425         OUT_RELOCW(ring, fd4_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
 426
 427         OUT_PKT0(ring, REG_A4XX_VSC_PIPE_CONFIG_REG(0), 8);
 428         for (i = 0; i < 8; i++) {
 429                 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
 430                 OUT_RING(ring, A4XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
 431                                 A4XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
 432                                 A4XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
 433                                 A4XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
 434         }
 435
 436         OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(0), 8);
 437         for (i = 0; i < 8; i++) {
 438                 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
 439                 if (!pipe->bo) {
 440                         pipe->bo = fd_bo_new(ctx->dev, 0x40000,
 441                                         DRM_FREEDRENO_GEM_TYPE_KMEM);
 442                 }
 443                 OUT_RELOCW(ring, pipe->bo, 0, 0, 0);       /* VSC_PIPE_DATA_ADDRESS[i] */
 444         }
 445
 446         OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(0), 8);
 447         for (i = 0; i < 8; i++) {
 448                 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
 449                 OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
 450         }
 451 }
 452
 453 /* before first tile */
 454 static void
 455 fd4_emit_tile_init(struct fd_context *ctx)
 456 {
 457         struct fd_ringbuffer *ring = ctx->ring;
 458         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 459         uint32_t rb_render_control;
 460
 461         fd4_emit_restore(ctx);
 462
 463         OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1);
 464         OUT_RING(ring, A4XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
 465                         A4XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
 466
 467         OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
 468         OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
 469                         A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h) |
 470                         0x00010000);  /* XXX */
 471
 472         update_vsc_pipe(ctx);
 473         patch_draws(ctx, IGNORE_VISIBILITY);
 474
 475         rb_render_control = 0; // XXX or BINNING_PASS.. but maybe we can emit only from gmem
 476         patch_rbrc(ctx, rb_render_control);
 477 }
 478
 479 /* before mem2gmem */
 480 static void
 481 fd4_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
 482 {
 483         struct fd_ringbuffer *ring = ctx->ring;
 484         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 485         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 486         uint32_t reg;
 487
 488         OUT_PKT0(ring, REG_A4XX_RB_DEPTH_INFO, 3);
 489         reg = A4XX_RB_DEPTH_INFO_DEPTH_BASE(depth_base(ctx));
 490         if (pfb->zsbuf) {
 491                 reg |= A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd4_pipe2depth(pfb->zsbuf->format));
 492         }
 493         OUT_RING(ring, reg);
 494         if (pfb->zsbuf) {
 495                 uint32_t cpp = util_format_get_blocksize(pfb->zsbuf->format);
 496                 OUT_RING(ring, A4XX_RB_DEPTH_PITCH(cpp * gmem->bin_w));
 497                 OUT_RING(ring, A4XX_RB_DEPTH_PITCH2(cpp * gmem->bin_w));
 498         } else {
 499                 OUT_RING(ring, 0x00000000);
 500                 OUT_RING(ring, 0x00000000);
 501         }
 502
 503         OUT_PKT0(ring, REG_A4XX_GRAS_DEPTH_CONTROL, 1);
 504         if (pfb->zsbuf) {
 505                 OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(
 506                                 fd4_pipe2depth(pfb->zsbuf->format)));
 507         } else {
 508                 OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(DEPTH4_NONE));
 509         }
 510
 511         if (ctx->needs_rb_fbd) {
 512                 fd_wfi(ctx, ring);
 513                 OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
 514                 OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
 515                                 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
 516                 ctx->needs_rb_fbd = false;
 517         }
 518 }
 519
 520 /* before IB to rendering cmds: */
 521 static void
 522 fd4_emit_tile_renderprep(struct fd_context *ctx, struct fd_tile *tile)
 523 {
 524         struct fd_ringbuffer *ring = ctx->ring;
 525         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 526         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 527
 528         uint32_t x1 = tile->xoff;
 529         uint32_t y1 = tile->yoff;
 530         uint32_t x2 = tile->xoff + tile->bin_w - 1;
 531         uint32_t y2 = tile->yoff + tile->bin_h - 1;
 532
 533         OUT_PKT3(ring, CP_SET_BIN, 3);
 534         OUT_RING(ring, 0x00000000);
 535         OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
 536         OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
 537
 538         emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, gmem->bin_w);
 539
 540         /* setup scissor/offset for current tile: */
 541         OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
 542         OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(tile->xoff) |
 543                         A4XX_RB_BIN_OFFSET_Y(tile->yoff));
 544
 545         OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 546         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
 547                         A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
 548         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
 549                         A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
 550 }
 551
 552 void
 553 fd4_gmem_init(struct pipe_context *pctx)
 554 {
 555         struct fd_context *ctx = fd_context(pctx);
 556
 557         ctx->emit_tile_init = fd4_emit_tile_init;
 558         ctx->emit_tile_prep = fd4_emit_tile_prep;
 559         ctx->emit_tile_mem2gmem = fd4_emit_tile_mem2gmem;
 560         ctx->emit_tile_renderprep = fd4_emit_tile_renderprep;
 561         ctx->emit_tile_gmem2mem = fd4_emit_tile_gmem2mem;
 562 }