src/gallium/drivers/freedreno/a4xx/fd4_gmem.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_inlines.h"
  33 #include "util/u_format.h"
  34
  35 #include "freedreno_draw.h"
  36 #include "freedreno_state.h"
  37 #include "freedreno_resource.h"
  38
  39 #include "fd4_gmem.h"
  40 #include "fd4_context.h"
  41 #include "fd4_draw.h"
  42 #include "fd4_emit.h"
  43 #include "fd4_program.h"
  44 #include "fd4_util.h"
  45 #include "fd4_zsa.h"
  46
  47 static const struct ir3_shader_key key = {
  48                 // XXX should set this based on render target format!  We don't
  49                 // want half_precision if float32 render target!!!
  50                 .half_precision = true,
  51 };
  52
  53 static void
  54 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
  55                 struct pipe_surface **bufs, uint32_t *bases, uint32_t bin_w)
  56 {
  57         unsigned i;
  58
  59         for (i = 0; i < 8; i++) {
  60                 enum a4xx_color_fmt format = 0;
  61                 enum a3xx_color_swap swap = WZYX;
  62                 struct fd_resource *rsc = NULL;
  63                 struct fd_resource_slice *slice = NULL;
  64                 uint32_t stride = 0;
  65                 uint32_t base = 0;
  66                 uint32_t layer_offset = 0;
  67
  68                 if ((i < nr_bufs) && bufs[i]) {
  69                         struct pipe_surface *psurf = bufs[i];
  70
  71                         rsc = fd_resource(psurf->texture);
  72                         slice = &rsc->slices[psurf->u.tex.level];
  73                         format = fd4_pipe2color(psurf->format);
  74                         swap = fd4_pipe2swap(psurf->format);
  75
  76                         debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
  77
  78                         layer_offset = slice->size0 * psurf->u.tex.first_layer;
  79
  80                         if (bin_w) {
  81                                 stride = bin_w * rsc->cpp;
  82
  83                                 if (bases) {
  84                                         base = bases[i];
  85                                 }
  86                         } else {
  87                                 stride = slice->pitch * rsc->cpp;
  88                         }
  89                 }
  90
  91                 OUT_PKT0(ring, REG_A4XX_RB_MRT_BUF_INFO(i), 3);
  92                 OUT_RING(ring, A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
  93                                 0x80 | /* XXX not on gmem2mem?? tile-mode? */
  94                                 A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
  95                                 A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap));
  96                 if (bin_w || (i >= nr_bufs)) {
  97                         OUT_RING(ring, base);
  98                 } else {
  99                         OUT_RELOCW(ring, rsc->bo,
 100                                         slice->offset + layer_offset, 0, -1);
 101                 }
 102                 OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(stride));
 103         }
 104 }
 105
 106 static uint32_t
 107 depth_base(struct fd_context *ctx)
 108 {
 109         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 110         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 111         uint32_t cpp = 4;
 112         if (pfb->cbufs[0]) {
 113                 struct fd_resource *rsc =
 114                                 fd_resource(pfb->cbufs[0]->texture);
 115                 cpp = rsc->cpp;
 116         }
 117         return align(gmem->bin_w * gmem->bin_h * cpp, 0x4000);
 118 }
 119
 120 /* transfer from gmem to system memory (ie. normal RAM) */
 121
 122 static void
 123 emit_gmem2mem_surf(struct fd_context *ctx,
 124                 uint32_t base, struct pipe_surface *psurf)
 125 {
 126         struct fd_ringbuffer *ring = ctx->ring;
 127         struct fd_resource *rsc = fd_resource(psurf->texture);
 128         struct fd_resource_slice *slice = &rsc->slices[psurf->u.tex.level];
 129
 130         OUT_PKT0(ring, REG_A4XX_RB_COPY_CONTROL, 4);
 131         OUT_RING(ring, A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
 132                         A4XX_RB_COPY_CONTROL_MODE(RB_COPY_RESOLVE) |
 133                         A4XX_RB_COPY_CONTROL_GMEM_BASE(base));
 134         OUT_RELOCW(ring, rsc->bo, slice->offset, 0, 0);   /* RB_COPY_DEST_BASE */
 135         OUT_RING(ring, A4XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->cpp));
 136         OUT_RING(ring, A4XX_RB_COPY_DEST_INFO_TILE(TILE4_LINEAR) |
 137                         A4XX_RB_COPY_DEST_INFO_FORMAT(fd4_pipe2color(psurf->format)) |
 138                         A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
 139                         A4XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
 140                         A4XX_RB_COPY_DEST_INFO_SWAP(fd4_pipe2swap(psurf->format)));
 141
 142         fd4_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 143                         DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
 144 }
 145
 146 static void
 147 fd4_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
 148 {
 149         struct fd4_context *fd4_ctx = fd4_context(ctx);
 150         struct fd_ringbuffer *ring = ctx->ring;
 151         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 152         struct fd4_emit emit = {
 153                         .vtx = &fd4_ctx->solid_vbuf_state,
 154                         .prog = &ctx->solid_prog,
 155                         .key = key,
 156         };
 157
 158         OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 159         OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 160
 161         OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 1);
 162         OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 163                         A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 164                         A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 165                         A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 166                         A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 167                         A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 168                         A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 169                         A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 170
 171         OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
 172         OUT_RING(ring, 0xff000000 |
 173                         A4XX_RB_STENCILREFMASK_STENCILREF(0) |
 174                         A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
 175                         A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 176         OUT_RING(ring, 0xff000000 |
 177                         A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
 178                         A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
 179                         A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0xff));
 180
 181         OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
 182         OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
 183
 184         fd_wfi(ctx, ring);
 185
 186         OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
 187         OUT_RING(ring, 0x80000);      /* GRAS_CL_CLIP_CNTL */
 188
 189         OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
 190         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)pfb->width/2.0));
 191         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)pfb->width/2.0));
 192         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)pfb->height/2.0));
 193         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)pfb->height/2.0));
 194         OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
 195         OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
 196
 197         OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
 198         OUT_RING(ring, A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
 199                         0xa);       /* XXX */
 200
 201         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 202         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
 203                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 204                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 205                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
 206
 207         OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
 208         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 209
 210         OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
 211         OUT_RING(ring, 0x00000002);
 212
 213         OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
 214         OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
 215                         A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
 216         OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
 217                         A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
 218
 219         OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
 220         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 221         OUT_RING(ring, 0);            /* ??? UNKNOWN_2209 */
 222
 223         fd4_program_emit(ring, &emit);
 224         fd4_emit_vertex_bufs(ring, &emit);
 225
 226         if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
 227                 uint32_t base = depth_base(ctx);
 228                 emit_gmem2mem_surf(ctx, base, pfb->zsbuf);
 229         }
 230
 231         if (ctx->resolve & FD_BUFFER_COLOR) {
 232                 emit_gmem2mem_surf(ctx, 0, pfb->cbufs[0]);
 233         }
 234
 235         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 236         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 237                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 238                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 239                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 240 }
 241
 242 /* transfer from system memory to gmem */
 243
 244 static void
 245 emit_mem2gmem_surf(struct fd_context *ctx, struct fd4_emit *emit,
 246                 uint32_t base, struct pipe_surface *psurf, uint32_t bin_w)
 247 {
 248         struct ir3_shader_variant *fp = fd4_emit_get_fp(emit);
 249         struct fd_ringbuffer *ring = ctx->ring;
 250         uint32_t color_regid = ir3_find_output_regid(fp,
 251                         ir3_semantic_name(TGSI_SEMANTIC_COLOR, 0));
 252
 253         OUT_PKT0(ring, REG_A4XX_SP_FS_MRT_REG(0), 8);
 254         OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(color_regid) |
 255                         A4XX_SP_FS_MRT_REG_MRTFORMAT(fd4_pipe2color(psurf->format)) |
 256                         COND(fp->key.half_precision, A4XX_SP_FS_MRT_REG_HALF_PRECISION));
 257         OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
 258         OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
 259         OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
 260         OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
 261         OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
 262         OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
 263         OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
 264
 265         emit_mrt(ring, 1, &psurf, &base, bin_w);
 266
 267         fd4_emit_gmem_restore_tex(ring, psurf);
 268
 269         fd4_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 270                         DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
 271 }
 272
 273 static void
 274 fd4_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
 275 {
 276         struct fd4_context *fd4_ctx = fd4_context(ctx);
 277         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 278         struct fd_ringbuffer *ring = ctx->ring;
 279         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 280         struct fd4_emit emit = {
 281                         .vtx = &fd4_ctx->blit_vbuf_state,
 282                         .prog = &ctx->blit_prog,
 283                         .key = key,
 284         };
 285         float x0, y0, x1, y1;
 286         unsigned bin_w = tile->bin_w;
 287         unsigned bin_h = tile->bin_h;
 288         unsigned i;
 289
 290         /* write texture coordinates to vertexbuf: */
 291         x0 = ((float)tile->xoff) / ((float)pfb->width);
 292         x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
 293         y0 = ((float)tile->yoff) / ((float)pfb->height);
 294         y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
 295
 296         OUT_PKT3(ring, CP_MEM_WRITE, 5);
 297         OUT_RELOCW(ring, fd_resource(fd4_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
 298         OUT_RING(ring, fui(x0));
 299         OUT_RING(ring, fui(y0));
 300         OUT_RING(ring, fui(x1));
 301         OUT_RING(ring, fui(y1));
 302
 303         for (i = 0; i < 8; i++) {
 304                 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
 305                 OUT_RING(ring, A4XX_RB_MRT_CONTROL_FASTCLEAR |
 306                                 A4XX_RB_MRT_CONTROL_B11 |
 307                                 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
 308
 309                 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
 310                 OUT_RING(ring, A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
 311                                 A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 312                                 A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
 313                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
 314                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 315                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
 316         }
 317
 318         OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
 319         OUT_RING(ring, 0x8);          /* XXX RB_RENDER_CONTROL */
 320
 321         OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 322         OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
 323
 324         OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
 325         OUT_RING(ring, 0x280000);     /* XXX GRAS_CL_CLIP_CNTL */
 326
 327         OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
 328         OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0) |
 329                         A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
 330
 331         OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
 332         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)bin_w/2.0));
 333         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)bin_w/2.0));
 334         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)bin_h/2.0));
 335         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)bin_h/2.0));
 336         OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
 337         OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
 338
 339         OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
 340         OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
 341                         A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
 342         OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
 343                         A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
 344
 345         OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 346         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
 347                         A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
 348         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
 349                         A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
 350
 351         OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
 352         OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
 353                         A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h));
 354
 355         OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 1);
 356         OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
 357                         A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 358                         A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 359                         A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 360                         A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
 361                         A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 362                         A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 363                         A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 364
 365         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 366         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 367                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 368                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 369                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
 370
 371         OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
 372         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST |
 373                         A4XX_PC_PRIM_VTX_CNTL_VAROUT);
 374
 375         OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
 376         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 377         OUT_RING(ring, 0);            /* ??? UNKNOWN_2209 */
 378
 379         fd4_program_emit(ring, &emit);
 380         fd4_emit_vertex_bufs(ring, &emit);
 381
 382         /* for gmem pitch/base calculations, we need to use the non-
 383          * truncated tile sizes:
 384          */
 385         bin_w = gmem->bin_w;
 386         bin_h = gmem->bin_h;
 387
 388         if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
 389                 emit_mem2gmem_surf(ctx, &emit, depth_base(ctx), pfb->zsbuf, bin_w);
 390
 391         if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_COLOR))
 392                 emit_mem2gmem_surf(ctx, &emit, 0, pfb->cbufs[0], bin_w);
 393
 394         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 395         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 396                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 397                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 398
 399         OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
 400         OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
 401                         A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h) |
 402                         0x00010000);  /* XXX */
 403 }
 404
 405 static void
 406 patch_draws(struct fd_context *ctx, enum pc_di_vis_cull_mode vismode)
 407 {
 408         unsigned i;
 409         for (i = 0; i < fd_patch_num_elements(&ctx->draw_patches); i++) {
 410                 struct fd_cs_patch *patch = fd_patch_element(&ctx->draw_patches, i);
 411                 *patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
 412         }
 413         util_dynarray_resize(&ctx->draw_patches, 0);
 414 }
 415
 416 static void
 417 patch_rbrc(struct fd_context *ctx, uint32_t val)
 418 {
 419         struct fd4_context *fd4_ctx = fd4_context(ctx);
 420         unsigned i;
 421         for (i = 0; i < fd_patch_num_elements(&fd4_ctx->rbrc_patches); i++) {
 422                 struct fd_cs_patch *patch = fd_patch_element(&fd4_ctx->rbrc_patches, i);
 423                 *patch->cs = patch->val | val;
 424         }
 425         util_dynarray_resize(&fd4_ctx->rbrc_patches, 0);
 426 }
 427
 428 static void
 429 update_vsc_pipe(struct fd_context *ctx)
 430 {
 431         struct fd4_context *fd4_ctx = fd4_context(ctx);
 432         struct fd_ringbuffer *ring = ctx->ring;
 433         int i;
 434
 435         OUT_PKT0(ring, REG_A4XX_VSC_SIZE_ADDRESS, 1);
 436         OUT_RELOCW(ring, fd4_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
 437
 438         OUT_PKT0(ring, REG_A4XX_VSC_PIPE_CONFIG_REG(0), 8);
 439         for (i = 0; i < 8; i++) {
 440                 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
 441                 OUT_RING(ring, A4XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
 442                                 A4XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
 443                                 A4XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
 444                                 A4XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
 445         }
 446
 447         OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(0), 8);
 448         for (i = 0; i < 8; i++) {
 449                 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
 450                 if (!pipe->bo) {
 451                         pipe->bo = fd_bo_new(ctx->dev, 0x40000,
 452                                         DRM_FREEDRENO_GEM_TYPE_KMEM);
 453                 }
 454                 OUT_RELOCW(ring, pipe->bo, 0, 0, 0);       /* VSC_PIPE_DATA_ADDRESS[i] */
 455         }
 456
 457         OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(0), 8);
 458         for (i = 0; i < 8; i++) {
 459                 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
 460                 OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
 461         }
 462 }
 463
 464 /* before first tile */
 465 static void
 466 fd4_emit_tile_init(struct fd_context *ctx)
 467 {
 468         struct fd_ringbuffer *ring = ctx->ring;
 469         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 470         uint32_t rb_render_control;
 471
 472         fd4_emit_restore(ctx);
 473
 474         OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1);
 475         OUT_RING(ring, A4XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
 476                         A4XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
 477
 478         OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
 479         OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
 480                         A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h) |
 481                         0x00010000);  /* XXX */
 482
 483         update_vsc_pipe(ctx);
 484         patch_draws(ctx, IGNORE_VISIBILITY);
 485
 486         rb_render_control = 0; // XXX or BINNING_PASS.. but maybe we can emit only from gmem
 487         patch_rbrc(ctx, rb_render_control);
 488 }
 489
 490 /* before mem2gmem */
 491 static void
 492 fd4_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
 493 {
 494         struct fd_ringbuffer *ring = ctx->ring;
 495         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 496         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 497         uint32_t reg;
 498
 499         OUT_PKT0(ring, REG_A4XX_RB_DEPTH_INFO, 3);
 500         reg = A4XX_RB_DEPTH_INFO_DEPTH_BASE(depth_base(ctx));
 501         if (pfb->zsbuf) {
 502                 reg |= A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
 503         }
 504         OUT_RING(ring, reg);
 505         if (pfb->zsbuf) {
 506                 OUT_RING(ring, A4XX_RB_DEPTH_PITCH(gmem->bin_w));
 507                 OUT_RING(ring, A4XX_RB_DEPTH_PITCH2(gmem->bin_w));
 508         } else {
 509                 OUT_RING(ring, 0x00000000);
 510                 OUT_RING(ring, 0x00000000);
 511         }
 512
 513         if (pfb->zsbuf) {
 514                 OUT_PKT0(ring, REG_A4XX_GRAS_DEPTH_CONTROL, 1);
 515                 OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(
 516                                 fd_pipe2depth(pfb->zsbuf->format)));
 517         }
 518
 519         if (ctx->needs_rb_fbd) {
 520                 fd_wfi(ctx, ring);
 521                 OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
 522                 OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
 523                                 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
 524                 ctx->needs_rb_fbd = false;
 525         }
 526 }
 527
 528 /* before IB to rendering cmds: */
 529 static void
 530 fd4_emit_tile_renderprep(struct fd_context *ctx, struct fd_tile *tile)
 531 {
 532         struct fd_ringbuffer *ring = ctx->ring;
 533         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 534         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 535
 536         uint32_t x1 = tile->xoff;
 537         uint32_t y1 = tile->yoff;
 538         uint32_t x2 = tile->xoff + tile->bin_w - 1;
 539         uint32_t y2 = tile->yoff + tile->bin_h - 1;
 540
 541         OUT_PKT3(ring, CP_SET_BIN, 3);
 542         OUT_RING(ring, 0x00000000);
 543         OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
 544         OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
 545
 546         emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, gmem->bin_w);
 547
 548         /* setup scissor/offset for current tile: */
 549         OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
 550         OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(tile->xoff) |
 551                         A4XX_RB_BIN_OFFSET_Y(tile->yoff));
 552
 553         OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 554         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
 555                         A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
 556         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
 557                         A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
 558 }
 559
 560 void
 561 fd4_gmem_init(struct pipe_context *pctx)
 562 {
 563         struct fd_context *ctx = fd_context(pctx);
 564
 565         ctx->emit_tile_init = fd4_emit_tile_init;
 566         ctx->emit_tile_prep = fd4_emit_tile_prep;
 567         ctx->emit_tile_mem2gmem = fd4_emit_tile_mem2gmem;
 568         ctx->emit_tile_renderprep = fd4_emit_tile_renderprep;
 569         ctx->emit_tile_gmem2mem = fd4_emit_tile_gmem2mem;
 570 }