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freedreno: re-order support for hw queries
[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_gmem.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_draw.h"
36 #include "freedreno_state.h"
37 #include "freedreno_resource.h"
38
39 #include "fd4_gmem.h"
40 #include "fd4_context.h"
41 #include "fd4_draw.h"
42 #include "fd4_emit.h"
43 #include "fd4_program.h"
44 #include "fd4_format.h"
45 #include "fd4_zsa.h"
46
47 static void
48 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
49 struct pipe_surface **bufs, uint32_t *bases,
50 uint32_t bin_w, bool decode_srgb)
51 {
52 enum a4xx_tile_mode tile_mode;
53 unsigned i;
54
55 if (bin_w) {
56 tile_mode = 2;
57 } else {
58 tile_mode = TILE4_LINEAR;
59 }
60
61 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
62 enum a4xx_color_fmt format = 0;
63 enum a3xx_color_swap swap = WZYX;
64 bool srgb = false;
65 struct fd_resource *rsc = NULL;
66 struct fd_resource_slice *slice = NULL;
67 uint32_t stride = 0;
68 uint32_t base = 0;
69 uint32_t offset = 0;
70
71 if ((i < nr_bufs) && bufs[i]) {
72 struct pipe_surface *psurf = bufs[i];
73 enum pipe_format pformat = psurf->format;
74
75 rsc = fd_resource(psurf->texture);
76
77 /* In case we're drawing to Z32F_S8, the "color" actually goes to
78 * the stencil
79 */
80 if (rsc->stencil) {
81 rsc = rsc->stencil;
82 pformat = rsc->base.b.format;
83 if (bases)
84 bases++;
85 }
86
87 slice = fd_resource_slice(rsc, psurf->u.tex.level);
88 format = fd4_pipe2color(pformat);
89 swap = fd4_pipe2swap(pformat);
90
91 if (decode_srgb)
92 srgb = util_format_is_srgb(pformat);
93 else
94 pformat = util_format_linear(pformat);
95
96 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
97
98 offset = fd_resource_offset(rsc, psurf->u.tex.level,
99 psurf->u.tex.first_layer);
100
101 if (bin_w) {
102 stride = bin_w * rsc->cpp;
103
104 if (bases) {
105 base = bases[i];
106 }
107 } else {
108 stride = slice->pitch * rsc->cpp;
109 }
110 } else if ((i < nr_bufs) && bases) {
111 base = bases[i];
112 }
113
114 OUT_PKT0(ring, REG_A4XX_RB_MRT_BUF_INFO(i), 3);
115 OUT_RING(ring, A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
116 A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
117 A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
118 A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
119 COND(srgb, A4XX_RB_MRT_BUF_INFO_COLOR_SRGB));
120 if (bin_w || (i >= nr_bufs) || !bufs[i]) {
121 OUT_RING(ring, base);
122 OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(stride));
123 } else {
124 OUT_RELOCW(ring, rsc->bo, offset, 0, 0);
125 /* RB_MRT[i].CONTROL3.STRIDE not emitted by c2d..
126 * not sure if we need to skip it for bypass or
127 * not.
128 */
129 OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(0));
130 }
131 }
132 }
133
134 static bool
135 use_hw_binning(struct fd_batch *batch)
136 {
137 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
138 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
139
140 /* this seems to be a hw bug.. but this hack fixes piglit fbo-maxsize: */
141 if ((pfb->width > 4096) && (pfb->height > 4096))
142 return false;
143
144 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
145 }
146
147 /* transfer from gmem to system memory (ie. normal RAM) */
148
149 static void
150 emit_gmem2mem_surf(struct fd_batch *batch, bool stencil,
151 uint32_t base, struct pipe_surface *psurf)
152 {
153 struct fd_ringbuffer *ring = batch->gmem;
154 struct fd_resource *rsc = fd_resource(psurf->texture);
155 enum pipe_format pformat = psurf->format;
156 struct fd_resource_slice *slice;
157 uint32_t offset;
158
159 if (stencil) {
160 debug_assert(rsc->stencil);
161 rsc = rsc->stencil;
162 pformat = rsc->base.b.format;
163 }
164
165 slice = &rsc->slices[psurf->u.tex.level];
166 offset = fd_resource_offset(rsc, psurf->u.tex.level,
167 psurf->u.tex.first_layer);
168
169 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
170
171 OUT_PKT0(ring, REG_A4XX_RB_COPY_CONTROL, 4);
172 OUT_RING(ring, A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
173 A4XX_RB_COPY_CONTROL_MODE(RB_COPY_RESOLVE) |
174 A4XX_RB_COPY_CONTROL_GMEM_BASE(base));
175 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* RB_COPY_DEST_BASE */
176 OUT_RING(ring, A4XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->cpp));
177 OUT_RING(ring, A4XX_RB_COPY_DEST_INFO_TILE(TILE4_LINEAR) |
178 A4XX_RB_COPY_DEST_INFO_FORMAT(fd4_pipe2color(pformat)) |
179 A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
180 A4XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
181 A4XX_RB_COPY_DEST_INFO_SWAP(fd4_pipe2swap(pformat)));
182
183 fd4_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
184 DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
185 }
186
187 static void
188 fd4_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
189 {
190 struct fd_context *ctx = batch->ctx;
191 struct fd4_context *fd4_ctx = fd4_context(ctx);
192 struct fd_gmem_stateobj *gmem = &ctx->gmem;
193 struct fd_ringbuffer *ring = batch->gmem;
194 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
195 struct fd4_emit emit = {
196 .debug = &ctx->debug,
197 .vtx = &fd4_ctx->solid_vbuf_state,
198 .prog = &ctx->solid_prog,
199 .key = {
200 .half_precision = true,
201 },
202 };
203
204 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
205 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
206
207 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
208 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
209 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
210 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
211 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
212 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
213 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
214 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
215 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
216 OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
217
218 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
219 OUT_RING(ring, 0xff000000 |
220 A4XX_RB_STENCILREFMASK_STENCILREF(0) |
221 A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
222 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
223 OUT_RING(ring, 0xff000000 |
224 A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
225 A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
226 A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0xff));
227
228 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
229 OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
230
231 fd_wfi(ctx, ring);
232
233 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
234 OUT_RING(ring, 0x80000); /* GRAS_CL_CLIP_CNTL */
235
236 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
237 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)pfb->width/2.0));
238 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)pfb->width/2.0));
239 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)pfb->height/2.0));
240 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)pfb->height/2.0));
241 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
242 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
243
244 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
245 OUT_RING(ring, A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
246 0xa); /* XXX */
247
248 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
249 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
250 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
251 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
252 A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
253
254 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
255 OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
256
257 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
258 OUT_RING(ring, 0x00000002);
259
260 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
261 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
262 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
263 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
264 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
265
266 OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
267 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
268 OUT_RING(ring, 0); /* ??? UNKNOWN_2209 */
269
270 fd4_program_emit(ring, &emit, 0, NULL);
271 fd4_emit_vertex_bufs(ring, &emit);
272
273 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
274 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
275 if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH))
276 emit_gmem2mem_surf(batch, false, ctx->gmem.zsbuf_base[0], pfb->zsbuf);
277 if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL))
278 emit_gmem2mem_surf(batch, true, ctx->gmem.zsbuf_base[1], pfb->zsbuf);
279 }
280
281 if (batch->resolve & FD_BUFFER_COLOR) {
282 unsigned i;
283 for (i = 0; i < pfb->nr_cbufs; i++) {
284 if (!pfb->cbufs[i])
285 continue;
286 if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
287 continue;
288 emit_gmem2mem_surf(batch, false, gmem->cbuf_base[i], pfb->cbufs[i]);
289 }
290 }
291
292 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
293 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
294 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
295 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
296 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
297 }
298
299 /* transfer from system memory to gmem */
300
301 static void
302 emit_mem2gmem_surf(struct fd_batch *batch, uint32_t *bases,
303 struct pipe_surface **bufs, uint32_t nr_bufs, uint32_t bin_w)
304 {
305 struct fd_ringbuffer *ring = batch->gmem;
306 struct pipe_surface *zsbufs[2];
307
308 emit_mrt(ring, nr_bufs, bufs, bases, bin_w, false);
309
310 if (bufs[0] && (bufs[0]->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)) {
311 /* The gmem_restore_tex logic will put the first buffer's stencil
312 * as color. Supply it with the proper information to make that
313 * happen.
314 */
315 zsbufs[0] = zsbufs[1] = bufs[0];
316 bufs = zsbufs;
317 nr_bufs = 2;
318 }
319
320 fd4_emit_gmem_restore_tex(ring, nr_bufs, bufs);
321
322 fd4_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
323 DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
324 }
325
326 static void
327 fd4_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
328 {
329 struct fd_context *ctx = batch->ctx;
330 struct fd4_context *fd4_ctx = fd4_context(ctx);
331 struct fd_gmem_stateobj *gmem = &ctx->gmem;
332 struct fd_ringbuffer *ring = batch->gmem;
333 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
334 struct fd4_emit emit = {
335 .debug = &ctx->debug,
336 .vtx = &fd4_ctx->blit_vbuf_state,
337 .sprite_coord_enable = 1,
338 /* NOTE: They all use the same VP, this is for vtx bufs. */
339 .prog = &ctx->blit_prog[0],
340 .key = {
341 .half_precision = fd_half_precision(pfb),
342 },
343 .no_decode_srgb = true,
344 };
345 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
346 float x0, y0, x1, y1;
347 unsigned bin_w = tile->bin_w;
348 unsigned bin_h = tile->bin_h;
349 unsigned i;
350
351 /* write texture coordinates to vertexbuf: */
352 x0 = ((float)tile->xoff) / ((float)pfb->width);
353 x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
354 y0 = ((float)tile->yoff) / ((float)pfb->height);
355 y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
356
357 OUT_PKT3(ring, CP_MEM_WRITE, 5);
358 OUT_RELOCW(ring, fd_resource(fd4_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
359 OUT_RING(ring, fui(x0));
360 OUT_RING(ring, fui(y0));
361 OUT_RING(ring, fui(x1));
362 OUT_RING(ring, fui(y1));
363
364 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
365 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
366
367 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
368 OUT_RING(ring, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
369 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
370
371 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
372 OUT_RING(ring, A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
373 A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
374 A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
375 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
376 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
377 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
378 }
379
380 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
381 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
382 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
383 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
384 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
385 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
386 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
387 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
388 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
389
390 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
391 OUT_RING(ring, 0x8); /* XXX RB_RENDER_CONTROL */
392
393 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
394 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
395
396 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
397 OUT_RING(ring, 0x280000); /* XXX GRAS_CL_CLIP_CNTL */
398
399 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
400 OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0) |
401 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
402
403 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
404 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)bin_w/2.0));
405 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)bin_w/2.0));
406 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)bin_h/2.0));
407 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)bin_h/2.0));
408 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
409 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
410
411 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
412 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
413 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
414 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
415 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
416
417 OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
418 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
419 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
420 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
421 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
422
423 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
424 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
425 A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h));
426
427 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
428 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
429 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
430 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
431 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
432 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
433 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
434 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
435 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
436 OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
437
438 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
439 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
440 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
441 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
442 A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
443
444 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
445 OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST |
446 A4XX_PC_PRIM_VTX_CNTL_VAROUT(1));
447
448 OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
449 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
450 OUT_RING(ring, 0); /* ??? UNKNOWN_2209 */
451
452 fd4_emit_vertex_bufs(ring, &emit);
453
454 /* for gmem pitch/base calculations, we need to use the non-
455 * truncated tile sizes:
456 */
457 bin_w = gmem->bin_w;
458 bin_h = gmem->bin_h;
459
460 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR)) {
461 emit.prog = &ctx->blit_prog[pfb->nr_cbufs - 1];
462 emit.fp = NULL; /* frag shader changed so clear cache */
463 fd4_program_emit(ring, &emit, pfb->nr_cbufs, pfb->cbufs);
464 emit_mem2gmem_surf(batch, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs, bin_w);
465 }
466
467 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
468 switch (pfb->zsbuf->format) {
469 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
470 case PIPE_FORMAT_Z32_FLOAT:
471 emit.prog = (pfb->zsbuf->format == PIPE_FORMAT_Z32_FLOAT) ?
472 &ctx->blit_z : &ctx->blit_zs;
473 emit.key.half_precision = false;
474
475 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
476 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_Z_ENABLE |
477 A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
478 A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS) |
479 A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE);
480
481 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
482 OUT_RING(ring, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE);
483
484 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
485 OUT_RING(ring, 0x80000); /* GRAS_CL_CLIP_CNTL */
486
487 break;
488 default:
489 /* Non-float can use a regular color write. It's split over 8-bit
490 * components, so half precision is always sufficient.
491 */
492 emit.prog = &ctx->blit_prog[0];
493 emit.key.half_precision = true;
494 break;
495 }
496 emit.fp = NULL; /* frag shader changed so clear cache */
497 fd4_program_emit(ring, &emit, 1, &pfb->zsbuf);
498 emit_mem2gmem_surf(batch, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
499 }
500
501 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
502 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
503 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
504 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
505
506 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
507 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
508 A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h) |
509 0x00010000); /* XXX */
510 }
511
512 static void
513 patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
514 {
515 unsigned i;
516 for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
517 struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
518 *patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
519 }
520 util_dynarray_resize(&batch->draw_patches, 0);
521 }
522
523 /* for rendering directly to system memory: */
524 static void
525 fd4_emit_sysmem_prep(struct fd_batch *batch)
526 {
527 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
528 struct fd_ringbuffer *ring = batch->gmem;
529
530 fd4_emit_restore(batch, ring);
531
532 OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
533 OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
534 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
535
536 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0, true);
537
538 /* setup scissor/offset for current tile: */
539 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
540 OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(0) |
541 A4XX_RB_BIN_OFFSET_Y(0));
542
543 OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
544 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
545 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
546 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
547 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
548
549 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
550 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(0) |
551 A4XX_RB_MODE_CONTROL_HEIGHT(0) |
552 0x00c00000); /* XXX */
553
554 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
555 OUT_RING(ring, 0x8);
556
557 patch_draws(batch, IGNORE_VISIBILITY);
558 }
559
560 static void
561 update_vsc_pipe(struct fd_batch *batch)
562 {
563 struct fd_context *ctx = batch->ctx;
564 struct fd4_context *fd4_ctx = fd4_context(ctx);
565 struct fd_ringbuffer *ring = batch->gmem;
566 int i;
567
568 OUT_PKT0(ring, REG_A4XX_VSC_SIZE_ADDRESS, 1);
569 OUT_RELOCW(ring, fd4_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
570
571 OUT_PKT0(ring, REG_A4XX_VSC_PIPE_CONFIG_REG(0), 8);
572 for (i = 0; i < 8; i++) {
573 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
574 OUT_RING(ring, A4XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
575 A4XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
576 A4XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
577 A4XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
578 }
579
580 OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(0), 8);
581 for (i = 0; i < 8; i++) {
582 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
583 if (!pipe->bo) {
584 pipe->bo = fd_bo_new(ctx->dev, 0x40000,
585 DRM_FREEDRENO_GEM_TYPE_KMEM);
586 }
587 OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE_DATA_ADDRESS[i] */
588 }
589
590 OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(0), 8);
591 for (i = 0; i < 8; i++) {
592 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
593 OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
594 }
595 }
596
597 static void
598 emit_binning_pass(struct fd_batch *batch)
599 {
600 struct fd_context *ctx = batch->ctx;
601 struct fd_gmem_stateobj *gmem = &ctx->gmem;
602 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
603 struct fd_ringbuffer *ring = batch->gmem;
604 int i;
605
606 uint32_t x1 = gmem->minx;
607 uint32_t y1 = gmem->miny;
608 uint32_t x2 = gmem->minx + gmem->width - 1;
609 uint32_t y2 = gmem->miny + gmem->height - 1;
610
611 OUT_PKT0(ring, REG_A4XX_PC_BINNING_COMMAND, 1);
612 OUT_RING(ring, A4XX_PC_BINNING_COMMAND_BINNING_ENABLE);
613
614 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
615 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS) |
616 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
617 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
618 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
619
620 OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
621 OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
622 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
623
624 /* setup scissor/offset for whole screen: */
625 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
626 OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(x1) |
627 A4XX_RB_BIN_OFFSET_Y(y1));
628
629 OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
630 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
631 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
632 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
633 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
634
635 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
636 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
637 OUT_RING(ring, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR) |
638 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
639 }
640
641 /* emit IB to binning drawcmds: */
642 ctx->emit_ib(ring, batch->binning);
643
644 fd_reset_wfi(ctx);
645 fd_wfi(ctx, ring);
646
647 /* and then put stuff back the way it was: */
648
649 OUT_PKT0(ring, REG_A4XX_PC_BINNING_COMMAND, 1);
650 OUT_RING(ring, 0x00000000);
651
652 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
653 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
654 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
655 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
656 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
657
658 fd_event_write(ctx, ring, CACHE_FLUSH);
659 fd_wfi(ctx, ring);
660 }
661
662 /* before first tile */
663 static void
664 fd4_emit_tile_init(struct fd_batch *batch)
665 {
666 struct fd_ringbuffer *ring = batch->gmem;
667 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
668
669 fd4_emit_restore(batch, ring);
670
671 OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1);
672 OUT_RING(ring, A4XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
673 A4XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
674
675 update_vsc_pipe(batch);
676
677 if (use_hw_binning(batch)) {
678 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
679 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
680 A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h));
681
682 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
683 OUT_RING(ring, A4XX_RB_RENDER_CONTROL_BINNING_PASS |
684 A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
685 0x8);
686
687 /* emit hw binning pass: */
688 emit_binning_pass(batch);
689
690 patch_draws(batch, USE_VISIBILITY);
691 } else {
692 patch_draws(batch, IGNORE_VISIBILITY);
693 }
694
695 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
696 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
697 A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h) |
698 A4XX_RB_MODE_CONTROL_ENABLE_GMEM);
699 }
700
701 /* before mem2gmem */
702 static void
703 fd4_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
704 {
705 struct fd_context *ctx = batch->ctx;
706 struct fd_ringbuffer *ring = batch->gmem;
707 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
708 struct fd_gmem_stateobj *gmem = &ctx->gmem;
709
710 if (pfb->zsbuf) {
711 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
712 uint32_t cpp = rsc->cpp;
713
714 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_INFO, 3);
715 OUT_RING(ring, A4XX_RB_DEPTH_INFO_DEPTH_BASE(gmem->zsbuf_base[0]) |
716 A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd4_pipe2depth(pfb->zsbuf->format)));
717 OUT_RING(ring, A4XX_RB_DEPTH_PITCH(cpp * gmem->bin_w));
718 OUT_RING(ring, A4XX_RB_DEPTH_PITCH2(cpp * gmem->bin_w));
719
720 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_INFO, 2);
721 if (rsc->stencil) {
722 OUT_RING(ring, A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL |
723 A4XX_RB_STENCIL_INFO_STENCIL_BASE(gmem->zsbuf_base[1]));
724 OUT_RING(ring, A4XX_RB_STENCIL_PITCH(rsc->stencil->cpp * gmem->bin_w));
725 } else {
726 OUT_RING(ring, 0x00000000);
727 OUT_RING(ring, 0x00000000);
728 }
729 } else {
730 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_INFO, 3);
731 OUT_RING(ring, 0x00000000);
732 OUT_RING(ring, 0x00000000);
733 OUT_RING(ring, 0x00000000);
734
735 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_INFO, 2);
736 OUT_RING(ring, 0); /* RB_STENCIL_INFO */
737 OUT_RING(ring, 0); /* RB_STENCIL_PITCH */
738 }
739
740 OUT_PKT0(ring, REG_A4XX_GRAS_DEPTH_CONTROL, 1);
741 if (pfb->zsbuf) {
742 OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(
743 fd4_pipe2depth(pfb->zsbuf->format)));
744 } else {
745 OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(DEPTH4_NONE));
746 }
747
748 if (ctx->needs_rb_fbd) {
749 fd_wfi(ctx, ring);
750 OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
751 OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
752 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
753 ctx->needs_rb_fbd = false;
754 }
755 }
756
757 /* before IB to rendering cmds: */
758 static void
759 fd4_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
760 {
761 struct fd_context *ctx = batch->ctx;
762 struct fd4_context *fd4_ctx = fd4_context(ctx);
763 struct fd_ringbuffer *ring = batch->gmem;
764 struct fd_gmem_stateobj *gmem = &ctx->gmem;
765 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
766
767 uint32_t x1 = tile->xoff;
768 uint32_t y1 = tile->yoff;
769 uint32_t x2 = tile->xoff + tile->bin_w - 1;
770 uint32_t y2 = tile->yoff + tile->bin_h - 1;
771
772 if (use_hw_binning(batch)) {
773 struct fd_vsc_pipe *pipe = &ctx->pipe[tile->p];
774
775 assert(pipe->w * pipe->h);
776
777 fd_event_write(ctx, ring, HLSQ_FLUSH);
778 fd_wfi(ctx, ring);
779
780 OUT_PKT0(ring, REG_A4XX_PC_VSTREAM_CONTROL, 1);
781 OUT_RING(ring, A4XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
782 A4XX_PC_VSTREAM_CONTROL_N(tile->n));
783
784 OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
785 OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
786 OUT_RELOCW(ring, fd4_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
787 (tile->p * 4), 0, 0);
788 } else {
789 OUT_PKT0(ring, REG_A4XX_PC_VSTREAM_CONTROL, 1);
790 OUT_RING(ring, 0x00000000);
791 }
792
793 OUT_PKT3(ring, CP_SET_BIN, 3);
794 OUT_RING(ring, 0x00000000);
795 OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
796 OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
797
798 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem->cbuf_base, gmem->bin_w, true);
799
800 /* setup scissor/offset for current tile: */
801 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
802 OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(tile->xoff) |
803 A4XX_RB_BIN_OFFSET_Y(tile->yoff));
804
805 OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
806 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
807 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
808 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
809 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
810
811 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
812 OUT_RING(ring, 0x8);
813 }
814
815 void
816 fd4_gmem_init(struct pipe_context *pctx)
817 {
818 struct fd_context *ctx = fd_context(pctx);
819
820 ctx->emit_sysmem_prep = fd4_emit_sysmem_prep;
821 ctx->emit_tile_init = fd4_emit_tile_init;
822 ctx->emit_tile_prep = fd4_emit_tile_prep;
823 ctx->emit_tile_mem2gmem = fd4_emit_tile_mem2gmem;
824 ctx->emit_tile_renderprep = fd4_emit_tile_renderprep;
825 ctx->emit_tile_gmem2mem = fd4_emit_tile_gmem2mem;
826 }