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freedreno/a4xx: fix srgb render targets
[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_gmem.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_draw.h"
36 #include "freedreno_state.h"
37 #include "freedreno_resource.h"
38
39 #include "fd4_gmem.h"
40 #include "fd4_context.h"
41 #include "fd4_draw.h"
42 #include "fd4_emit.h"
43 #include "fd4_program.h"
44 #include "fd4_format.h"
45 #include "fd4_zsa.h"
46
47 static void
48 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
49 struct pipe_surface **bufs, uint32_t *bases,
50 uint32_t bin_w, bool decode_srgb)
51 {
52 enum a4xx_tile_mode tile_mode;
53 unsigned i;
54
55 if (bin_w) {
56 tile_mode = 2;
57 } else {
58 tile_mode = TILE4_LINEAR;
59 }
60
61 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
62 enum a4xx_color_fmt format = 0;
63 enum a3xx_color_swap swap = WZYX;
64 bool srgb = false;
65 struct fd_resource *rsc = NULL;
66 struct fd_resource_slice *slice = NULL;
67 uint32_t stride = 0;
68 uint32_t base = 0;
69 uint32_t offset = 0;
70
71 if ((i < nr_bufs) && bufs[i]) {
72 struct pipe_surface *psurf = bufs[i];
73 enum pipe_format pformat = psurf->format;
74
75 rsc = fd_resource(psurf->texture);
76
77 /* In case we're drawing to Z32F_S8, the "color" actually goes to
78 * the stencil
79 */
80 if (rsc->stencil) {
81 rsc = rsc->stencil;
82 pformat = rsc->base.b.format;
83 bases++;
84 }
85
86 slice = fd_resource_slice(rsc, psurf->u.tex.level);
87 format = fd4_pipe2color(pformat);
88 swap = fd4_pipe2swap(pformat);
89
90 if (decode_srgb)
91 srgb = util_format_is_srgb(pformat);
92 else
93 pformat = util_format_linear(pformat);
94
95 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
96
97 offset = fd_resource_offset(rsc, psurf->u.tex.level,
98 psurf->u.tex.first_layer);
99
100 if (bin_w) {
101 stride = bin_w * rsc->cpp;
102
103 if (bases) {
104 base = bases[i];
105 }
106 } else {
107 stride = slice->pitch * rsc->cpp;
108 }
109 } else if ((i < nr_bufs) && bases) {
110 base = bases[i];
111 }
112
113 OUT_PKT0(ring, REG_A4XX_RB_MRT_BUF_INFO(i), 3);
114 OUT_RING(ring, A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
115 A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
116 A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
117 A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
118 COND(srgb, A4XX_RB_MRT_BUF_INFO_COLOR_SRGB));
119 if (bin_w || (i >= nr_bufs) || !bufs[i]) {
120 OUT_RING(ring, base);
121 OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(stride));
122 } else {
123 OUT_RELOCW(ring, rsc->bo, offset, 0, 0);
124 /* RB_MRT[i].CONTROL3.STRIDE not emitted by c2d..
125 * not sure if we need to skip it for bypass or
126 * not.
127 */
128 OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(0));
129 }
130 }
131 }
132
133 /* transfer from gmem to system memory (ie. normal RAM) */
134
135 static void
136 emit_gmem2mem_surf(struct fd_context *ctx, bool stencil,
137 uint32_t base, struct pipe_surface *psurf)
138 {
139 struct fd_ringbuffer *ring = ctx->ring;
140 struct fd_resource *rsc = fd_resource(psurf->texture);
141 enum pipe_format pformat = psurf->format;
142 struct fd_resource_slice *slice;
143 uint32_t offset;
144
145 if (stencil) {
146 debug_assert(rsc->stencil);
147 rsc = rsc->stencil;
148 pformat = rsc->base.b.format;
149 }
150
151 slice = &rsc->slices[psurf->u.tex.level];
152 offset = fd_resource_offset(rsc, psurf->u.tex.level,
153 psurf->u.tex.first_layer);
154
155 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
156
157 OUT_PKT0(ring, REG_A4XX_RB_COPY_CONTROL, 4);
158 OUT_RING(ring, A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
159 A4XX_RB_COPY_CONTROL_MODE(RB_COPY_RESOLVE) |
160 A4XX_RB_COPY_CONTROL_GMEM_BASE(base));
161 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* RB_COPY_DEST_BASE */
162 OUT_RING(ring, A4XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->cpp));
163 OUT_RING(ring, A4XX_RB_COPY_DEST_INFO_TILE(TILE4_LINEAR) |
164 A4XX_RB_COPY_DEST_INFO_FORMAT(fd4_pipe2color(pformat)) |
165 A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
166 A4XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
167 A4XX_RB_COPY_DEST_INFO_SWAP(fd4_pipe2swap(pformat)));
168
169 fd4_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
170 DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
171 }
172
173 static void
174 fd4_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
175 {
176 struct fd4_context *fd4_ctx = fd4_context(ctx);
177 struct fd_gmem_stateobj *gmem = &ctx->gmem;
178 struct fd_ringbuffer *ring = ctx->ring;
179 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
180 struct fd4_emit emit = {
181 .vtx = &fd4_ctx->solid_vbuf_state,
182 .prog = &ctx->solid_prog,
183 .key = {
184 .half_precision = true,
185 },
186 };
187
188 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
189 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
190
191 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
192 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
193 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
194 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
195 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
196 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
197 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
198 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
199 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
200 OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
201
202 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
203 OUT_RING(ring, 0xff000000 |
204 A4XX_RB_STENCILREFMASK_STENCILREF(0) |
205 A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
206 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
207 OUT_RING(ring, 0xff000000 |
208 A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
209 A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
210 A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0xff));
211
212 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
213 OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
214
215 fd_wfi(ctx, ring);
216
217 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
218 OUT_RING(ring, 0x80000); /* GRAS_CL_CLIP_CNTL */
219
220 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
221 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)pfb->width/2.0));
222 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)pfb->width/2.0));
223 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)pfb->height/2.0));
224 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)pfb->height/2.0));
225 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
226 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
227
228 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
229 OUT_RING(ring, A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
230 0xa); /* XXX */
231
232 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
233 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
234 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
235 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
236 A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
237
238 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
239 OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
240
241 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
242 OUT_RING(ring, 0x00000002);
243
244 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
245 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
246 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
247 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
248 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
249
250 OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
251 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
252 OUT_RING(ring, 0); /* ??? UNKNOWN_2209 */
253
254 fd4_program_emit(ring, &emit, 0, NULL);
255 fd4_emit_vertex_bufs(ring, &emit);
256
257 if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
258 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
259 if (!rsc->stencil || (ctx->resolve & FD_BUFFER_DEPTH))
260 emit_gmem2mem_surf(ctx, false, ctx->gmem.zsbuf_base[0], pfb->zsbuf);
261 if (rsc->stencil && (ctx->resolve & FD_BUFFER_STENCIL))
262 emit_gmem2mem_surf(ctx, true, ctx->gmem.zsbuf_base[1], pfb->zsbuf);
263 }
264
265 if (ctx->resolve & FD_BUFFER_COLOR) {
266 unsigned i;
267 for (i = 0; i < pfb->nr_cbufs; i++) {
268 if (!pfb->cbufs[i])
269 continue;
270 if (!(ctx->resolve & (PIPE_CLEAR_COLOR0 << i)))
271 continue;
272 emit_gmem2mem_surf(ctx, false, gmem->cbuf_base[i], pfb->cbufs[i]);
273 }
274 }
275
276 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
277 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
278 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
279 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
280 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
281 }
282
283 /* transfer from system memory to gmem */
284
285 static void
286 emit_mem2gmem_surf(struct fd_context *ctx, uint32_t *bases,
287 struct pipe_surface **bufs, uint32_t nr_bufs, uint32_t bin_w)
288 {
289 struct fd_ringbuffer *ring = ctx->ring;
290 struct pipe_surface *zsbufs[2];
291
292 emit_mrt(ring, nr_bufs, bufs, bases, bin_w, false);
293
294 if (bufs[0] && (bufs[0]->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)) {
295 /* The gmem_restore_tex logic will put the first buffer's stencil
296 * as color. Supply it with the proper information to make that
297 * happen.
298 */
299 zsbufs[0] = zsbufs[1] = bufs[0];
300 bufs = zsbufs;
301 nr_bufs = 2;
302 }
303
304 fd4_emit_gmem_restore_tex(ring, nr_bufs, bufs);
305
306 fd4_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
307 DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
308 }
309
310 static void
311 fd4_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
312 {
313 struct fd4_context *fd4_ctx = fd4_context(ctx);
314 struct fd_gmem_stateobj *gmem = &ctx->gmem;
315 struct fd_ringbuffer *ring = ctx->ring;
316 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
317 struct fd4_emit emit = {
318 .vtx = &fd4_ctx->blit_vbuf_state,
319 .sprite_coord_enable = 1,
320 /* NOTE: They all use the same VP, this is for vtx bufs. */
321 .prog = &ctx->blit_prog[0],
322 .key = {
323 .half_precision = fd_half_precision(pfb),
324 },
325 .no_decode_srgb = true,
326 };
327 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
328 float x0, y0, x1, y1;
329 unsigned bin_w = tile->bin_w;
330 unsigned bin_h = tile->bin_h;
331 unsigned i;
332
333 /* write texture coordinates to vertexbuf: */
334 x0 = ((float)tile->xoff) / ((float)pfb->width);
335 x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
336 y0 = ((float)tile->yoff) / ((float)pfb->height);
337 y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
338
339 OUT_PKT3(ring, CP_MEM_WRITE, 5);
340 OUT_RELOCW(ring, fd_resource(fd4_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
341 OUT_RING(ring, fui(x0));
342 OUT_RING(ring, fui(y0));
343 OUT_RING(ring, fui(x1));
344 OUT_RING(ring, fui(y1));
345
346 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
347 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
348
349 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
350 OUT_RING(ring, A4XX_RB_MRT_CONTROL_FASTCLEAR |
351 A4XX_RB_MRT_CONTROL_B11 |
352 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
353
354 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
355 OUT_RING(ring, A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
356 A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
357 A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
358 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
359 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
360 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
361 }
362
363 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
364 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
365 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
366 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
367 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
368 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
369 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
370 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
371 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
372
373 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
374 OUT_RING(ring, 0x8); /* XXX RB_RENDER_CONTROL */
375
376 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
377 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
378
379 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
380 OUT_RING(ring, 0x280000); /* XXX GRAS_CL_CLIP_CNTL */
381
382 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
383 OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0) |
384 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
385
386 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
387 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)bin_w/2.0));
388 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)bin_w/2.0));
389 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)bin_h/2.0));
390 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)bin_h/2.0));
391 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
392 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
393
394 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
395 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
396 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
397 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
398 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
399
400 OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
401 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
402 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
403 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
404 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
405
406 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
407 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
408 A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h));
409
410 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
411 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
412 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
413 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
414 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
415 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
416 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
417 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
418 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
419 OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
420
421 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
422 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
423 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
424 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
425 A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
426
427 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
428 OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST |
429 A4XX_PC_PRIM_VTX_CNTL_VAROUT(1));
430
431 OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
432 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
433 OUT_RING(ring, 0); /* ??? UNKNOWN_2209 */
434
435 fd4_emit_vertex_bufs(ring, &emit);
436
437 /* for gmem pitch/base calculations, we need to use the non-
438 * truncated tile sizes:
439 */
440 bin_w = gmem->bin_w;
441 bin_h = gmem->bin_h;
442
443 if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_COLOR)) {
444 emit.prog = &ctx->blit_prog[pfb->nr_cbufs - 1];
445 emit.fp = NULL; /* frag shader changed so clear cache */
446 fd4_program_emit(ring, &emit, pfb->nr_cbufs, pfb->cbufs);
447 emit_mem2gmem_surf(ctx, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs, bin_w);
448 }
449
450 if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
451 switch (pfb->zsbuf->format) {
452 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
453 case PIPE_FORMAT_Z32_FLOAT:
454 emit.prog = (pfb->zsbuf->format == PIPE_FORMAT_Z32_FLOAT) ?
455 &ctx->blit_z : &ctx->blit_zs;
456 emit.key.half_precision = false;
457
458 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
459 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_Z_ENABLE |
460 A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
461 A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS) |
462 A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE);
463
464 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
465 OUT_RING(ring, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE);
466
467 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
468 OUT_RING(ring, 0x80000); /* GRAS_CL_CLIP_CNTL */
469
470 break;
471 default:
472 /* Non-float can use a regular color write. It's split over 8-bit
473 * components, so half precision is always sufficient.
474 */
475 emit.prog = &ctx->blit_prog[0];
476 emit.key.half_precision = true;
477 break;
478 }
479 emit.fp = NULL; /* frag shader changed so clear cache */
480 fd4_program_emit(ring, &emit, 1, &pfb->zsbuf);
481 emit_mem2gmem_surf(ctx, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
482 }
483
484 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
485 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
486 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
487 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
488
489 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
490 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
491 A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h) |
492 0x00010000); /* XXX */
493 }
494
495 static void
496 patch_draws(struct fd_context *ctx, enum pc_di_vis_cull_mode vismode)
497 {
498 unsigned i;
499 for (i = 0; i < fd_patch_num_elements(&ctx->draw_patches); i++) {
500 struct fd_cs_patch *patch = fd_patch_element(&ctx->draw_patches, i);
501 *patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
502 }
503 util_dynarray_resize(&ctx->draw_patches, 0);
504 }
505
506 static void
507 patch_rbrc(struct fd_context *ctx, uint32_t val)
508 {
509 struct fd4_context *fd4_ctx = fd4_context(ctx);
510 unsigned i;
511 for (i = 0; i < fd_patch_num_elements(&fd4_ctx->rbrc_patches); i++) {
512 struct fd_cs_patch *patch = fd_patch_element(&fd4_ctx->rbrc_patches, i);
513 *patch->cs = patch->val | val;
514 }
515 util_dynarray_resize(&fd4_ctx->rbrc_patches, 0);
516 }
517
518 /* for rendering directly to system memory: */
519 static void
520 fd4_emit_sysmem_prep(struct fd_context *ctx)
521 {
522 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
523 struct fd_ringbuffer *ring = ctx->ring;
524
525 fd4_emit_restore(ctx);
526
527 OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
528 OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
529 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
530
531 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0, true);
532
533 /* setup scissor/offset for current tile: */
534 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
535 OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(0) |
536 A4XX_RB_BIN_OFFSET_Y(0));
537
538 OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
539 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
540 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
541 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
542 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
543
544 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
545 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(0) |
546 A4XX_RB_MODE_CONTROL_HEIGHT(0) |
547 0x00c00000); /* XXX */
548
549 patch_draws(ctx, IGNORE_VISIBILITY);
550 patch_rbrc(ctx, 0); // XXX
551 }
552
553 static void
554 update_vsc_pipe(struct fd_context *ctx)
555 {
556 struct fd4_context *fd4_ctx = fd4_context(ctx);
557 struct fd_ringbuffer *ring = ctx->ring;
558 int i;
559
560 OUT_PKT0(ring, REG_A4XX_VSC_SIZE_ADDRESS, 1);
561 OUT_RELOCW(ring, fd4_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
562
563 OUT_PKT0(ring, REG_A4XX_VSC_PIPE_CONFIG_REG(0), 8);
564 for (i = 0; i < 8; i++) {
565 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
566 OUT_RING(ring, A4XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
567 A4XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
568 A4XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
569 A4XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
570 }
571
572 OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(0), 8);
573 for (i = 0; i < 8; i++) {
574 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
575 if (!pipe->bo) {
576 pipe->bo = fd_bo_new(ctx->dev, 0x40000,
577 DRM_FREEDRENO_GEM_TYPE_KMEM);
578 }
579 OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* VSC_PIPE_DATA_ADDRESS[i] */
580 }
581
582 OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(0), 8);
583 for (i = 0; i < 8; i++) {
584 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
585 OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
586 }
587 }
588
589 /* before first tile */
590 static void
591 fd4_emit_tile_init(struct fd_context *ctx)
592 {
593 struct fd_ringbuffer *ring = ctx->ring;
594 struct fd_gmem_stateobj *gmem = &ctx->gmem;
595 uint32_t rb_render_control;
596
597 fd4_emit_restore(ctx);
598
599 OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1);
600 OUT_RING(ring, A4XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
601 A4XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
602
603 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
604 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
605 A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h) |
606 0x00010000); /* XXX */
607
608 update_vsc_pipe(ctx);
609 patch_draws(ctx, IGNORE_VISIBILITY);
610
611 rb_render_control = 0; // XXX or BINNING_PASS.. but maybe we can emit only from gmem
612 patch_rbrc(ctx, rb_render_control);
613 }
614
615 /* before mem2gmem */
616 static void
617 fd4_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
618 {
619 struct fd_ringbuffer *ring = ctx->ring;
620 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
621 struct fd_gmem_stateobj *gmem = &ctx->gmem;
622
623 if (pfb->zsbuf) {
624 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
625 uint32_t cpp = rsc->cpp;
626
627 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_INFO, 3);
628 OUT_RING(ring, A4XX_RB_DEPTH_INFO_DEPTH_BASE(gmem->zsbuf_base[0]) |
629 A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd4_pipe2depth(pfb->zsbuf->format)));
630 OUT_RING(ring, A4XX_RB_DEPTH_PITCH(cpp * gmem->bin_w));
631 OUT_RING(ring, A4XX_RB_DEPTH_PITCH2(cpp * gmem->bin_w));
632
633 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_INFO, 2);
634 if (rsc->stencil) {
635 OUT_RING(ring, A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL |
636 A4XX_RB_STENCIL_INFO_STENCIL_BASE(gmem->zsbuf_base[1]));
637 OUT_RING(ring, A4XX_RB_STENCIL_PITCH(rsc->stencil->cpp * gmem->bin_w));
638 } else {
639 OUT_RING(ring, 0x00000000);
640 OUT_RING(ring, 0x00000000);
641 }
642 } else {
643 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_INFO, 3);
644 OUT_RING(ring, 0x00000000);
645 OUT_RING(ring, 0x00000000);
646 OUT_RING(ring, 0x00000000);
647
648 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_INFO, 2);
649 OUT_RING(ring, 0); /* RB_STENCIL_INFO */
650 OUT_RING(ring, 0); /* RB_STENCIL_PITCH */
651 }
652
653 OUT_PKT0(ring, REG_A4XX_GRAS_DEPTH_CONTROL, 1);
654 if (pfb->zsbuf) {
655 OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(
656 fd4_pipe2depth(pfb->zsbuf->format)));
657 } else {
658 OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(DEPTH4_NONE));
659 }
660
661 if (ctx->needs_rb_fbd) {
662 fd_wfi(ctx, ring);
663 OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
664 OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
665 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
666 ctx->needs_rb_fbd = false;
667 }
668 }
669
670 /* before IB to rendering cmds: */
671 static void
672 fd4_emit_tile_renderprep(struct fd_context *ctx, struct fd_tile *tile)
673 {
674 struct fd_ringbuffer *ring = ctx->ring;
675 struct fd_gmem_stateobj *gmem = &ctx->gmem;
676 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
677
678 uint32_t x1 = tile->xoff;
679 uint32_t y1 = tile->yoff;
680 uint32_t x2 = tile->xoff + tile->bin_w - 1;
681 uint32_t y2 = tile->yoff + tile->bin_h - 1;
682
683 OUT_PKT3(ring, CP_SET_BIN, 3);
684 OUT_RING(ring, 0x00000000);
685 OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
686 OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
687
688 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem->cbuf_base, gmem->bin_w, true);
689
690 /* setup scissor/offset for current tile: */
691 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
692 OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(tile->xoff) |
693 A4XX_RB_BIN_OFFSET_Y(tile->yoff));
694
695 OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
696 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
697 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
698 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
699 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
700 }
701
702 void
703 fd4_gmem_init(struct pipe_context *pctx)
704 {
705 struct fd_context *ctx = fd_context(pctx);
706
707 ctx->emit_sysmem_prep = fd4_emit_sysmem_prep;
708 ctx->emit_tile_init = fd4_emit_tile_init;
709 ctx->emit_tile_prep = fd4_emit_tile_prep;
710 ctx->emit_tile_mem2gmem = fd4_emit_tile_mem2gmem;
711 ctx->emit_tile_renderprep = fd4_emit_tile_renderprep;
712 ctx->emit_tile_gmem2mem = fd4_emit_tile_gmem2mem;
713 }