2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/u_format.h"
32 #include "util/u_viewport.h"
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
38 #include "fd5_blend.h"
39 #include "fd5_context.h"
40 #include "fd5_program.h"
41 #include "fd5_rasterizer.h"
42 #include "fd5_texture.h"
43 #include "fd5_format.h"
46 static const enum adreno_state_block sb
[] = {
47 [SHADER_VERTEX
] = SB_VERT_SHADER
,
48 [SHADER_FRAGMENT
] = SB_FRAG_SHADER
,
51 /* regid: base const register
52 * prsc or dwords: buffer containing constant values
53 * sizedwords: size of const value buffer
56 fd5_emit_const(struct fd_ringbuffer
*ring
, enum shader_t type
,
57 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
,
58 const uint32_t *dwords
, struct pipe_resource
*prsc
)
61 enum adreno_state_src src
;
63 debug_assert((regid
% 4) == 0);
64 debug_assert((sizedwords
% 4) == 0);
74 OUT_PKT7(ring
, CP_LOAD_STATE
, 3 + sz
);
75 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/4) |
76 CP_LOAD_STATE_0_STATE_SRC(src
) |
77 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
78 CP_LOAD_STATE_0_NUM_UNIT(sizedwords
/4));
80 struct fd_bo
*bo
= fd_resource(prsc
)->bo
;
81 OUT_RELOC(ring
, bo
, offset
,
82 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
), 0);
84 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
85 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
86 OUT_RING(ring
, CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(0));
87 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
89 for (i
= 0; i
< sz
; i
++) {
90 OUT_RING(ring
, dwords
[i
]);
95 fd5_emit_const_bo(struct fd_ringbuffer
*ring
, enum shader_t type
, boolean write
,
96 uint32_t regid
, uint32_t num
, struct pipe_resource
**prscs
, uint32_t *offsets
)
98 uint32_t anum
= align(num
, 2);
101 debug_assert((regid
% 4) == 0);
103 OUT_PKT7(ring
, CP_LOAD_STATE
, 3 + (2 * anum
));
104 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/4) |
105 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
106 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
107 CP_LOAD_STATE_0_NUM_UNIT(anum
/2));
108 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
109 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
110 OUT_RING(ring
, CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(0));
112 for (i
= 0; i
< num
; i
++) {
115 OUT_RELOCW(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
117 OUT_RELOC(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
120 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
121 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
125 for (; i
< anum
; i
++) {
126 OUT_RING(ring
, 0xffffffff);
127 OUT_RING(ring
, 0xffffffff);
131 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
132 * the same as a6xx then move this somewhere common ;-)
134 * Entry layout looks like (total size, 0x60 bytes):
136 * offset | description
137 * -------+-------------
154 * 0x28 | ?? maybe padding ??
163 * 0x38 | ?? maybe padding ??
165 * Some uncertainty, because not clear that this actually works properly
166 * with blob, so who knows..
169 struct PACKED bcolor_entry
{
180 #define FD5_BORDER_COLOR_SIZE 0x60
181 #define FD5_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD5_BORDER_COLOR_SIZE)
182 #define FD5_BORDER_COLOR_OFFSET 8 /* TODO probably should be dynamic */
185 setup_border_colors(struct fd_texture_stateobj
*tex
, struct bcolor_entry
*entries
)
189 debug_assert(tex
->num_samplers
< FD5_BORDER_COLOR_OFFSET
); // TODO
191 for (i
= 0; i
< tex
->num_samplers
; i
++) {
192 struct bcolor_entry
*e
= &entries
[i
];
193 struct pipe_sampler_state
*sampler
= tex
->samplers
[i
];
194 union pipe_color_union
*bc
;
199 bc
= &sampler
->border_color
;
204 * The border colors need to be swizzled in a particular
205 * format-dependent order. Even though samplers don't know about
206 * formats, we can assume that with a GL state tracker, there's a
207 * 1:1 correspondence between sampler and texture. Take advantage
210 if ((i
>= tex
->num_textures
) || !tex
->textures
[i
])
213 const struct util_format_description
*desc
=
214 util_format_description(tex
->textures
[i
]->format
);
216 for (j
= 0; j
< 4; j
++) {
217 int c
= desc
->swizzle
[j
];
222 if (desc
->channel
[c
].pure_integer
) {
226 e
->fp16
[j
] = util_float_to_half(f
);
227 e
->ui16
[j
] = bc
->ui
[c
];
228 e
->si16
[j
] = bc
->i
[c
];
229 e
->ui8
[j
] = bc
->ui
[c
];
230 e
->si8
[j
] = bc
->i
[c
];
235 e
->fp16
[j
] = util_float_to_half(f
);
236 e
->ui16
[j
] = f
* 65535.0;
237 e
->si16
[j
] = f
* 32767.5;
238 e
->ui8
[j
] = f
* 255.0;
239 e
->si8
[j
] = f
* 128.0;
244 memset(&e
->__pad0
, 0, sizeof(e
->__pad0
));
245 memset(&e
->__pad1
, 0, sizeof(e
->__pad1
));
251 emit_border_color(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
)
253 struct fd5_context
*fd5_ctx
= fd5_context(ctx
);
254 struct bcolor_entry
*entries
;
258 STATIC_ASSERT(sizeof(struct bcolor_entry
) == FD5_BORDER_COLOR_SIZE
);
260 u_upload_alloc(fd5_ctx
->border_color_uploader
,
261 0, FD5_BORDER_COLOR_UPLOAD_SIZE
,
262 FD5_BORDER_COLOR_UPLOAD_SIZE
, &off
,
263 &fd5_ctx
->border_color_buf
,
268 setup_border_colors(&ctx
->verttex
, &entries
[0]);
269 setup_border_colors(&ctx
->fragtex
, &entries
[ctx
->verttex
.num_samplers
]);
271 OUT_PKT4(ring
, REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO
, 2);
272 OUT_RELOC(ring
, fd_resource(fd5_ctx
->border_color_buf
)->bo
, off
, 0, 0);
274 u_upload_unmap(fd5_ctx
->border_color_uploader
);
278 emit_textures(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
279 enum adreno_state_block sb
, struct fd_texture_stateobj
*tex
)
281 bool needs_border
= false;
282 unsigned bcolor_offset
= (sb
== SB_FRAG_TEX
) ? ctx
->verttex
.num_samplers
: 0;
285 if (tex
->num_samplers
> 0) {
286 /* output sampler state: */
287 OUT_PKT7(ring
, CP_LOAD_STATE
, 3 + (4 * tex
->num_samplers
));
288 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
289 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
290 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
291 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_samplers
));
292 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
293 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
294 OUT_RING(ring
, CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(0));
295 for (i
= 0; i
< tex
->num_samplers
; i
++) {
296 static const struct fd5_sampler_stateobj dummy_sampler
= {};
297 const struct fd5_sampler_stateobj
*sampler
= tex
->samplers
[i
] ?
298 fd5_sampler_stateobj(tex
->samplers
[i
]) :
300 OUT_RING(ring
, sampler
->texsamp0
);
301 OUT_RING(ring
, sampler
->texsamp1
);
302 OUT_RING(ring
, sampler
->texsamp2
|
303 A5XX_TEX_SAMP_2_BCOLOR_OFFSET(bcolor_offset
));
304 OUT_RING(ring
, sampler
->texsamp3
);
306 needs_border
|= sampler
->needs_border
;
310 if (tex
->num_textures
> 0) {
311 unsigned num_textures
= tex
->num_textures
;
313 /* emit texture state: */
314 OUT_PKT7(ring
, CP_LOAD_STATE
, 3 + (12 * num_textures
));
315 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
316 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
317 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
318 CP_LOAD_STATE_0_NUM_UNIT(num_textures
));
319 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
320 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
321 OUT_RING(ring
, CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(0));
322 for (i
= 0; i
< tex
->num_textures
; i
++) {
323 static const struct fd5_pipe_sampler_view dummy_view
= {};
324 const struct fd5_pipe_sampler_view
*view
= tex
->textures
[i
] ?
325 fd5_pipe_sampler_view(tex
->textures
[i
]) :
328 OUT_RING(ring
, view
->texconst0
);
329 OUT_RING(ring
, view
->texconst1
);
330 OUT_RING(ring
, view
->texconst2
);
331 OUT_RING(ring
, view
->texconst3
);
332 if (view
->base
.texture
) {
333 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
334 OUT_RELOC(ring
, rsc
->bo
, view
->offset
,
335 (uint64_t)view
->texconst5
<< 32, 0);
337 OUT_RING(ring
, 0x00000000);
338 OUT_RING(ring
, view
->texconst5
);
340 OUT_RING(ring
, view
->texconst6
);
341 OUT_RING(ring
, view
->texconst7
);
342 OUT_RING(ring
, view
->texconst8
);
343 OUT_RING(ring
, view
->texconst9
);
344 OUT_RING(ring
, view
->texconst10
);
345 OUT_RING(ring
, view
->texconst11
);
353 fd5_emit_vertex_bufs(struct fd_ringbuffer
*ring
, struct fd5_emit
*emit
)
356 const struct fd_vertex_state
*vtx
= emit
->vtx
;
357 const struct ir3_shader_variant
*vp
= fd5_emit_get_vp(emit
);
359 for (i
= 0, j
= 0; i
<= vp
->inputs_count
; i
++) {
360 if (vp
->inputs
[i
].sysval
)
362 if (vp
->inputs
[i
].compmask
) {
363 struct pipe_vertex_element
*elem
= &vtx
->vtx
->pipe
[i
];
364 const struct pipe_vertex_buffer
*vb
=
365 &vtx
->vertexbuf
.vb
[elem
->vertex_buffer_index
];
366 struct fd_resource
*rsc
= fd_resource(vb
->buffer
);
367 enum pipe_format pfmt
= elem
->src_format
;
368 enum a5xx_vtx_fmt fmt
= fd5_pipe2vtx(pfmt
);
369 uint32_t off
= vb
->buffer_offset
+ elem
->src_offset
;
370 uint32_t size
= fd_bo_size(rsc
->bo
) - off
;
371 debug_assert(fmt
!= ~0);
373 OUT_PKT4(ring
, REG_A5XX_VFD_FETCH(j
), 4);
374 OUT_RELOC(ring
, rsc
->bo
, off
, 0, 0);
375 OUT_RING(ring
, size
); /* VFD_FETCH[j].SIZE */
376 OUT_RING(ring
, vb
->stride
); /* VFD_FETCH[j].STRIDE */
378 OUT_PKT4(ring
, REG_A5XX_VFD_DECODE(j
), 2);
379 OUT_RING(ring
, A5XX_VFD_DECODE_INSTR_IDX(j
) |
380 A5XX_VFD_DECODE_INSTR_FORMAT(fmt
) |
381 COND(elem
->instance_divisor
, A5XX_VFD_DECODE_INSTR_INSTANCED
) |
383 OUT_RING(ring
, MAX2(1, elem
->instance_divisor
)); /* VFD_DECODE[j].STEP_RATE */
385 OUT_PKT4(ring
, REG_A5XX_VFD_DEST_CNTL(j
), 1);
386 OUT_RING(ring
, A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp
->inputs
[i
].compmask
) |
387 A5XX_VFD_DEST_CNTL_INSTR_REGID(vp
->inputs
[i
].regid
));
393 OUT_PKT4(ring
, REG_A5XX_VFD_CONTROL_0
, 1);
394 OUT_RING(ring
, A5XX_VFD_CONTROL_0_VTXCNT(j
));
398 fd5_emit_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
399 struct fd5_emit
*emit
)
401 const struct ir3_shader_variant
*vp
= fd5_emit_get_vp(emit
);
402 const struct ir3_shader_variant
*fp
= fd5_emit_get_fp(emit
);
403 uint32_t dirty
= emit
->dirty
;
404 bool needs_border
= false;
406 emit_marker5(ring
, 5);
408 if ((dirty
& FD_DIRTY_FRAMEBUFFER
) && !emit
->key
.binning_pass
) {
409 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
410 unsigned char mrt_comp
[A5XX_MAX_RENDER_TARGETS
] = {0};
412 for (unsigned i
= 0; i
< A5XX_MAX_RENDER_TARGETS
; i
++) {
413 mrt_comp
[i
] = ((i
< pfb
->nr_cbufs
) && pfb
->cbufs
[i
]) ? 0xf : 0;
416 OUT_PKT4(ring
, REG_A5XX_RB_RENDER_COMPONENTS
, 1);
417 OUT_RING(ring
, A5XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
418 A5XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
419 A5XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
420 A5XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
421 A5XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
422 A5XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
423 A5XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
424 A5XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
427 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_FRAMEBUFFER
)) {
428 struct fd5_zsa_stateobj
*zsa
= fd5_zsa_stateobj(ctx
->zsa
);
429 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
430 uint32_t rb_alpha_control
= zsa
->rb_alpha_control
;
432 if (util_format_is_pure_integer(pipe_surface_format(pfb
->cbufs
[0])))
433 rb_alpha_control
&= ~A5XX_RB_ALPHA_CONTROL_ALPHA_TEST
;
435 OUT_PKT4(ring
, REG_A5XX_RB_ALPHA_CONTROL
, 1);
436 OUT_RING(ring
, rb_alpha_control
);
438 OUT_PKT4(ring
, REG_A5XX_RB_STENCIL_CONTROL
, 1);
439 OUT_RING(ring
, zsa
->rb_stencil_control
);
442 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_STENCIL_REF
)) {
443 struct fd5_zsa_stateobj
*zsa
= fd5_zsa_stateobj(ctx
->zsa
);
444 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
446 OUT_PKT4(ring
, REG_A5XX_RB_STENCILREFMASK
, 1);
447 OUT_RING(ring
, zsa
->rb_stencilrefmask
|
448 A5XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
451 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
452 struct fd5_zsa_stateobj
*zsa
= fd5_zsa_stateobj(ctx
->zsa
);
453 bool fragz
= fp
->has_kill
| fp
->writes_pos
;
455 OUT_PKT4(ring
, REG_A5XX_RB_DEPTH_CNTL
, 1);
456 OUT_RING(ring
, zsa
->rb_depth_cntl
);
458 OUT_PKT4(ring
, REG_A5XX_RB_DEPTH_PLANE_CNTL
, 1);
459 OUT_RING(ring
, COND(fragz
, A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
) |
460 COND(fragz
&& fp
->frag_coord
, A5XX_RB_DEPTH_PLANE_CNTL_UNK1
));
462 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL
, 1);
463 OUT_RING(ring
, COND(fragz
, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
) |
464 COND(fragz
&& fp
->frag_coord
, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1
));
467 if (dirty
& FD_DIRTY_RASTERIZER
) {
468 struct fd5_rasterizer_stateobj
*rasterizer
=
469 fd5_rasterizer_stateobj(ctx
->rasterizer
);
471 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_CNTL
, 1);
472 OUT_RING(ring
, rasterizer
->gras_su_cntl
);
474 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_POINT_MINMAX
, 2);
475 OUT_RING(ring
, rasterizer
->gras_su_point_minmax
);
476 OUT_RING(ring
, rasterizer
->gras_su_point_size
);
478 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE
, 3);
479 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_scale
);
480 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_offset
);
481 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_clamp
);
484 /* NOTE: since primitive_restart is not actually part of any
485 * state object, we need to make sure that we always emit
486 * PRIM_VTX_CNTL.. either that or be more clever and detect
490 struct fd5_rasterizer_stateobj
*rast
=
491 fd5_rasterizer_stateobj(ctx
->rasterizer
);
492 uint32_t val
= rast
->pc_prim_vtx_cntl
;
494 val
|= COND(vp
->writes_psize
, A5XX_PC_PRIM_VTX_CNTL_PSIZE
);
496 OUT_PKT4(ring
, REG_A5XX_PC_PRIM_VTX_CNTL
, 1);
500 if (dirty
& FD_DIRTY_SCISSOR
) {
501 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
503 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0
, 2);
504 OUT_RING(ring
, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor
->minx
) |
505 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor
->miny
));
506 OUT_RING(ring
, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor
->maxx
- 1) |
507 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor
->maxy
- 1));
509 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0
, 2);
510 OUT_RING(ring
, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor
->minx
) |
511 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor
->miny
));
512 OUT_RING(ring
, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor
->maxx
- 1) |
513 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor
->maxy
- 1));
515 ctx
->batch
->max_scissor
.minx
= MIN2(ctx
->batch
->max_scissor
.minx
, scissor
->minx
);
516 ctx
->batch
->max_scissor
.miny
= MIN2(ctx
->batch
->max_scissor
.miny
, scissor
->miny
);
517 ctx
->batch
->max_scissor
.maxx
= MAX2(ctx
->batch
->max_scissor
.maxx
, scissor
->maxx
);
518 ctx
->batch
->max_scissor
.maxy
= MAX2(ctx
->batch
->max_scissor
.maxy
, scissor
->maxy
);
521 if (dirty
& FD_DIRTY_VIEWPORT
) {
522 fd_wfi(ctx
->batch
, ring
);
523 OUT_PKT4(ring
, REG_A5XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
524 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_XOFFSET_0(ctx
->viewport
.translate
[0]));
525 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_XSCALE_0(ctx
->viewport
.scale
[0]));
526 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_YOFFSET_0(ctx
->viewport
.translate
[1]));
527 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_YSCALE_0(ctx
->viewport
.scale
[1]));
528 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_ZOFFSET_0(ctx
->viewport
.translate
[2]));
529 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_ZSCALE_0(ctx
->viewport
.scale
[2]));
532 if (dirty
& FD_DIRTY_PROG
)
533 fd5_program_emit(ring
, emit
);
535 if (dirty
& (FD_DIRTY_FRAMEBUFFER
| FD_DIRTY_RASTERIZER
)) {
536 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
537 uint32_t posz_regid
= ir3_find_output_regid(fp
, FRAG_RESULT_DEPTH
);
538 unsigned nr
= pfb
->nr_cbufs
;
540 if (emit
->key
.binning_pass
)
542 else if (ctx
->rasterizer
->rasterizer_discard
)
545 OUT_PKT4(ring
, REG_A5XX_RB_FS_OUTPUT_CNTL
, 1);
546 OUT_RING(ring
, A5XX_RB_FS_OUTPUT_CNTL_MRT(nr
) |
547 COND(fp
->writes_pos
, A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z
));
549 OUT_PKT4(ring
, REG_A5XX_SP_FS_OUTPUT_CNTL
, 1);
550 OUT_RING(ring
, A5XX_SP_FS_OUTPUT_CNTL_MRT(nr
) |
551 A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(posz_regid
) |
552 A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(regid(63, 0)));
555 if (emit
->prog
== &ctx
->prog
) { /* evil hack to deal sanely with clear path */
556 ir3_emit_consts(vp
, ring
, ctx
, emit
->info
, dirty
);
557 if (!emit
->key
.binning_pass
)
558 ir3_emit_consts(fp
, ring
, ctx
, emit
->info
, dirty
);
560 struct pipe_stream_output_info
*info
= &vp
->shader
->stream_output
;
561 if (info
->num_outputs
) {
562 struct fd_streamout_stateobj
*so
= &ctx
->streamout
;
564 for (unsigned i
= 0; i
< so
->num_targets
; i
++) {
565 struct pipe_stream_output_target
*target
= so
->targets
[i
];
570 unsigned offset
= (so
->offsets
[i
] * info
->stride
[i
] * 4) +
571 target
->buffer_offset
;
573 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_BASE_LO(i
), 3);
574 /* VPC_SO[i].BUFFER_BASE_LO: */
575 OUT_RELOCW(ring
, fd_resource(target
->buffer
)->bo
, 0, 0, 0);
576 OUT_RING(ring
, target
->buffer_size
+ offset
);
578 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(i
), 3);
579 OUT_RING(ring
, offset
);
580 /* VPC_SO[i].FLUSH_BASE_LO/HI: */
581 // TODO just give hw a dummy addr for now.. we should
582 // be using this an then CP_MEM_TO_REG to set the
583 // VPC_SO[i].BUFFER_OFFSET for the next draw..
584 OUT_RELOCW(ring
, fd5_context(ctx
)->blit_mem
, 0x100, 0, 0);
586 emit
->streamout_mask
|= (1 << i
);
591 if ((dirty
& FD_DIRTY_BLEND
)) {
592 struct fd5_blend_stateobj
*blend
= fd5_blend_stateobj(ctx
->blend
);
595 for (i
= 0; i
< A5XX_MAX_RENDER_TARGETS
; i
++) {
596 enum pipe_format format
= pipe_surface_format(
597 ctx
->batch
->framebuffer
.cbufs
[i
]);
598 bool is_int
= util_format_is_pure_integer(format
);
599 bool has_alpha
= util_format_has_alpha(format
);
600 uint32_t control
= blend
->rb_mrt
[i
].control
;
601 uint32_t blend_control
= blend
->rb_mrt
[i
].blend_control_alpha
;
604 control
&= A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
;
605 // control |= A5XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
609 blend_control
|= blend
->rb_mrt
[i
].blend_control_rgb
;
611 blend_control
|= blend
->rb_mrt
[i
].blend_control_no_alpha_rgb
;
612 control
&= ~A5XX_RB_MRT_CONTROL_BLEND2
;
615 OUT_PKT4(ring
, REG_A5XX_RB_MRT_CONTROL(i
), 1);
616 OUT_RING(ring
, control
);
618 OUT_PKT4(ring
, REG_A5XX_RB_MRT_BLEND_CONTROL(i
), 1);
619 OUT_RING(ring
, blend_control
);
622 OUT_PKT4(ring
, REG_A5XX_RB_BLEND_CNTL
, 1);
623 OUT_RING(ring
, blend
->rb_blend_cntl
|
624 A5XX_RB_BLEND_CNTL_SAMPLE_MASK(0xffff));
626 OUT_PKT4(ring
, REG_A5XX_SP_BLEND_CNTL
, 1);
627 OUT_RING(ring
, 0x00000100);
630 if (dirty
& FD_DIRTY_BLEND_COLOR
) {
631 struct pipe_blend_color
*bcolor
= &ctx
->blend_color
;
633 OUT_PKT4(ring
, REG_A5XX_RB_BLEND_RED
, 8);
634 OUT_RING(ring
, A5XX_RB_BLEND_RED_FLOAT(bcolor
->color
[0]) |
635 A5XX_RB_BLEND_RED_UINT(bcolor
->color
[0] * 0xff) |
636 A5XX_RB_BLEND_RED_SINT(bcolor
->color
[0] * 0x7f));
637 OUT_RING(ring
, A5XX_RB_BLEND_RED_F32(bcolor
->color
[0]));
638 OUT_RING(ring
, A5XX_RB_BLEND_GREEN_FLOAT(bcolor
->color
[1]) |
639 A5XX_RB_BLEND_GREEN_UINT(bcolor
->color
[1] * 0xff) |
640 A5XX_RB_BLEND_GREEN_SINT(bcolor
->color
[1] * 0x7f));
641 OUT_RING(ring
, A5XX_RB_BLEND_RED_F32(bcolor
->color
[1]));
642 OUT_RING(ring
, A5XX_RB_BLEND_BLUE_FLOAT(bcolor
->color
[2]) |
643 A5XX_RB_BLEND_BLUE_UINT(bcolor
->color
[2] * 0xff) |
644 A5XX_RB_BLEND_BLUE_SINT(bcolor
->color
[2] * 0x7f));
645 OUT_RING(ring
, A5XX_RB_BLEND_BLUE_F32(bcolor
->color
[2]));
646 OUT_RING(ring
, A5XX_RB_BLEND_ALPHA_FLOAT(bcolor
->color
[3]) |
647 A5XX_RB_BLEND_ALPHA_UINT(bcolor
->color
[3] * 0xff) |
648 A5XX_RB_BLEND_ALPHA_SINT(bcolor
->color
[3] * 0x7f));
649 OUT_RING(ring
, A5XX_RB_BLEND_ALPHA_F32(bcolor
->color
[3]));
652 if (dirty
& FD_DIRTY_VERTTEX
) {
654 needs_border
|= emit_textures(ctx
, ring
, SB_VERT_TEX
, &ctx
->verttex
);
655 OUT_PKT4(ring
, REG_A5XX_TPL1_VS_TEX_COUNT
, 1);
656 OUT_RING(ring
, ctx
->verttex
.num_textures
);
658 dirty
&= ~FD_DIRTY_VERTTEX
;
662 if (dirty
& FD_DIRTY_FRAGTEX
) {
664 needs_border
|= emit_textures(ctx
, ring
, SB_FRAG_TEX
, &ctx
->fragtex
);
665 OUT_PKT4(ring
, REG_A5XX_TPL1_FS_TEX_COUNT
, 1);
666 OUT_RING(ring
, ctx
->fragtex
.num_textures
);
668 dirty
&= ~FD_DIRTY_FRAGTEX
;
673 emit_border_color(ctx
, ring
);
675 ctx
->dirty
&= ~dirty
;
678 /* emit setup at begin of new cmdstream buffer (don't rely on previous
679 * state, there could have been a context switch between ioctls):
682 fd5_emit_restore(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
684 struct fd_context
*ctx
= batch
->ctx
;
686 fd5_set_render_mode(ctx
, ring
, BYPASS
);
687 fd5_cache_flush(batch
, ring
);
689 OUT_PKT4(ring
, REG_A5XX_HLSQ_UPDATE_CNTL
, 1);
690 OUT_RING(ring
, 0xfffff);
693 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
694 0000000500024048: 70d08003 00000000 001c5000 00000005
695 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
696 0000000500024058: 70d08003 00000010 001c7000 00000005
698 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
699 0000000500024068: 70268000
702 OUT_PKT4(ring
, REG_A5XX_PC_RESTART_INDEX
, 1);
703 OUT_RING(ring
, 0xffffffff);
705 OUT_PKT4(ring
, REG_A5XX_PC_RASTER_CNTL
, 1);
706 OUT_RING(ring
, 0x00000012);
708 OUT_PKT4(ring
, REG_A5XX_GRAS_LRZ_CNTL
, 1);
709 OUT_RING(ring
, 0x00000000);
711 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_POINT_MINMAX
, 2);
712 OUT_RING(ring
, A5XX_GRAS_SU_POINT_MINMAX_MIN(1.0) |
713 A5XX_GRAS_SU_POINT_MINMAX_MAX(4092.0));
714 OUT_RING(ring
, A5XX_GRAS_SU_POINT_SIZE(0.5));
716 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL
, 1);
717 OUT_RING(ring
, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
719 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL
, 1);
720 OUT_RING(ring
, 0x00000000); /* GRAS_SC_SCREEN_SCISSOR_CNTL */
722 OUT_PKT4(ring
, REG_A5XX_SP_VS_CONFIG_MAX_CONST
, 1);
723 OUT_RING(ring
, 0); /* SP_VS_CONFIG_MAX_CONST */
725 OUT_PKT4(ring
, REG_A5XX_SP_FS_CONFIG_MAX_CONST
, 1);
726 OUT_RING(ring
, 0); /* SP_FS_CONFIG_MAX_CONST */
728 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E292
, 2);
729 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E292 */
730 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E293 */
732 OUT_PKT4(ring
, REG_A5XX_RB_MODE_CNTL
, 1);
733 OUT_RING(ring
, 0x00000044); /* RB_MODE_CNTL */
735 OUT_PKT4(ring
, REG_A5XX_RB_DBG_ECO_CNTL
, 1);
736 OUT_RING(ring
, 0x00100000); /* RB_DBG_ECO_CNTL */
738 OUT_PKT4(ring
, REG_A5XX_VFD_MODE_CNTL
, 1);
739 OUT_RING(ring
, 0x00000000); /* VFD_MODE_CNTL */
741 OUT_PKT4(ring
, REG_A5XX_PC_MODE_CNTL
, 1);
742 OUT_RING(ring
, 0x0000001f); /* PC_MODE_CNTL */
744 OUT_PKT4(ring
, REG_A5XX_SP_MODE_CNTL
, 1);
745 OUT_RING(ring
, 0x0000001e); /* SP_MODE_CNTL */
747 OUT_PKT4(ring
, REG_A5XX_SP_DBG_ECO_CNTL
, 1);
748 OUT_RING(ring
, 0x40000800); /* SP_DBG_ECO_CNTL */
750 OUT_PKT4(ring
, REG_A5XX_TPL1_MODE_CNTL
, 1);
751 OUT_RING(ring
, 0x00000544); /* TPL1_MODE_CNTL */
753 OUT_PKT4(ring
, REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0
, 2);
754 OUT_RING(ring
, 0x00000080); /* HLSQ_TIMEOUT_THRESHOLD_0 */
755 OUT_RING(ring
, 0x00000000); /* HLSQ_TIMEOUT_THRESHOLD_1 */
757 OUT_PKT4(ring
, REG_A5XX_VPC_DBG_ECO_CNTL
, 1);
758 OUT_RING(ring
, 0x00000400); /* VPC_DBG_ECO_CNTL */
760 OUT_PKT4(ring
, REG_A5XX_HLSQ_MODE_CNTL
, 1);
761 OUT_RING(ring
, 0x00000001); /* HLSQ_MODE_CNTL */
763 OUT_PKT4(ring
, REG_A5XX_VPC_MODE_CNTL
, 1);
764 OUT_RING(ring
, 0x00000000); /* VPC_MODE_CNTL */
766 /* we don't use this yet.. probably best to disable.. */
767 OUT_PKT7(ring
, CP_SET_DRAW_STATE
, 3);
768 OUT_RING(ring
, CP_SET_DRAW_STATE__0_COUNT(0) |
769 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
770 CP_SET_DRAW_STATE__0_GROUP_ID(0));
771 OUT_RING(ring
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
772 OUT_RING(ring
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
774 /* other regs not used (yet?) and always seem to have same value: */
775 OUT_PKT4(ring
, REG_A5XX_GRAS_CL_CNTL
, 1);
776 OUT_RING(ring
, 0x00000080); /* GRAS_CL_CNTL */
778 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL
, 1);
779 OUT_RING(ring
, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
781 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_BIN_CNTL
, 1);
782 OUT_RING(ring
, 0x00000000); /* GRAS_SC_BIN_CNTL */
784 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_BIN_CNTL
, 1);
785 OUT_RING(ring
, 0x00000000); /* GRAS_SC_BIN_CNTL */
787 OUT_PKT4(ring
, REG_A5XX_VPC_FS_PRIMITIVEID_CNTL
, 1);
788 OUT_RING(ring
, 0x000000ff); /* VPC_FS_PRIMITIVEID_CNTL */
790 OUT_PKT4(ring
, REG_A5XX_VPC_SO_OVERRIDE
, 1);
791 OUT_RING(ring
, A5XX_VPC_SO_OVERRIDE_SO_DISABLE
);
793 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_BASE_LO(0), 3);
794 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
795 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
796 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
798 OUT_PKT4(ring
, REG_A5XX_VPC_SO_FLUSH_BASE_LO(0), 2);
799 OUT_RING(ring
, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
800 OUT_RING(ring
, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
802 OUT_PKT4(ring
, REG_A5XX_PC_GS_PARAM
, 1);
803 OUT_RING(ring
, 0x00000000); /* PC_GS_PARAM */
805 OUT_PKT4(ring
, REG_A5XX_PC_HS_PARAM
, 1);
806 OUT_RING(ring
, 0x00000000); /* PC_HS_PARAM */
808 OUT_PKT4(ring
, REG_A5XX_TPL1_TP_FS_ROTATION_CNTL
, 1);
809 OUT_RING(ring
, 0x00000000); /* TPL1_TP_FS_ROTATION_CNTL */
811 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E001
, 1);
812 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E001 */
814 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E004
, 1);
815 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E004 */
817 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E093
, 1);
818 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E093 */
820 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E1C7
, 1);
821 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E1C7 */
823 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E29A
, 1);
824 OUT_RING(ring
, 0x00ffff00); /* UNKNOWN_E29A */
826 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUF_CNTL
, 1);
827 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUF_CNTL */
829 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(0), 1);
830 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E2AB */
832 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E389
, 1);
833 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E389 */
835 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E38D
, 1);
836 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E38D */
838 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E5AB
, 1);
839 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E5AB */
841 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E5C2
, 1);
842 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E5C2 */
844 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_BASE_LO(1), 3);
845 OUT_RING(ring
, 0x00000000);
846 OUT_RING(ring
, 0x00000000);
847 OUT_RING(ring
, 0x00000000);
849 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(1), 6);
850 OUT_RING(ring
, 0x00000000);
851 OUT_RING(ring
, 0x00000000);
852 OUT_RING(ring
, 0x00000000);
853 OUT_RING(ring
, 0x00000000);
854 OUT_RING(ring
, 0x00000000);
855 OUT_RING(ring
, 0x00000000);
857 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(2), 6);
858 OUT_RING(ring
, 0x00000000);
859 OUT_RING(ring
, 0x00000000);
860 OUT_RING(ring
, 0x00000000);
861 OUT_RING(ring
, 0x00000000);
862 OUT_RING(ring
, 0x00000000);
863 OUT_RING(ring
, 0x00000000);
865 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(3), 3);
866 OUT_RING(ring
, 0x00000000);
867 OUT_RING(ring
, 0x00000000);
868 OUT_RING(ring
, 0x00000000);
870 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E5DB
, 1);
871 OUT_RING(ring
, 0x00000000);
873 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E600
, 1);
874 OUT_RING(ring
, 0x00000000);
876 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E640
, 1);
877 OUT_RING(ring
, 0x00000000);
879 OUT_PKT4(ring
, REG_A5XX_TPL1_VS_TEX_COUNT
, 4);
880 OUT_RING(ring
, 0x00000000);
881 OUT_RING(ring
, 0x00000000);
882 OUT_RING(ring
, 0x00000000);
883 OUT_RING(ring
, 0x00000000);
885 OUT_PKT4(ring
, REG_A5XX_TPL1_FS_TEX_COUNT
, 2);
886 OUT_RING(ring
, 0x00000000);
887 OUT_RING(ring
, 0x00000000);
889 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7C0
, 3);
890 OUT_RING(ring
, 0x00000000);
891 OUT_RING(ring
, 0x00000000);
892 OUT_RING(ring
, 0x00000000);
894 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7C5
, 3);
895 OUT_RING(ring
, 0x00000000);
896 OUT_RING(ring
, 0x00000000);
897 OUT_RING(ring
, 0x00000000);
899 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7CA
, 3);
900 OUT_RING(ring
, 0x00000000);
901 OUT_RING(ring
, 0x00000000);
902 OUT_RING(ring
, 0x00000000);
904 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7CF
, 3);
905 OUT_RING(ring
, 0x00000000);
906 OUT_RING(ring
, 0x00000000);
907 OUT_RING(ring
, 0x00000000);
909 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7D4
, 3);
910 OUT_RING(ring
, 0x00000000);
911 OUT_RING(ring
, 0x00000000);
912 OUT_RING(ring
, 0x00000000);
914 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7D9
, 3);
915 OUT_RING(ring
, 0x00000000);
916 OUT_RING(ring
, 0x00000000);
917 OUT_RING(ring
, 0x00000000);
919 // TODO hacks.. these should not be hardcoded:
920 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_CNTL
, 1);
921 OUT_RING(ring
, 0x00000008); /* GRAS_SC_CNTL */
923 fd_hw_query_enable(batch
, ring
);
927 fd5_emit_ib(struct fd_ringbuffer
*ring
, struct fd_ringbuffer
*target
)
929 __OUT_IB5(ring
, target
);
933 fd5_emit_init(struct pipe_context
*pctx
)
935 struct fd_context
*ctx
= fd_context(pctx
);
936 ctx
->emit_const
= fd5_emit_const
;
937 ctx
->emit_const_bo
= fd5_emit_const_bo
;
938 ctx
->emit_ib
= fd5_emit_ib
;