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freedreno/a6xx: Handle srgb blits on the blitter
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_blitter.c
1 /*
2 * Copyright (C) 2017 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "util/u_dump.h"
29 #include "util/half_float.h"
30
31 #include "freedreno_blitter.h"
32 #include "freedreno_fence.h"
33 #include "freedreno_resource.h"
34
35 #include "fd6_blitter.h"
36 #include "fd6_format.h"
37 #include "fd6_emit.h"
38 #include "fd6_resource.h"
39 #include "fd6_pack.h"
40
41 /* Make sure none of the requested dimensions extend beyond the size of the
42 * resource. Not entirely sure why this happens, but sometimes it does, and
43 * w/ 2d blt doesn't have wrap modes like a sampler, so force those cases
44 * back to u_blitter
45 */
46 static bool
47 ok_dims(const struct pipe_resource *r, const struct pipe_box *b, int lvl)
48 {
49 int last_layer =
50 r->target == PIPE_TEXTURE_3D ? u_minify(r->depth0, lvl)
51 : r->array_size;
52
53 return (b->x >= 0) && (b->x + b->width <= u_minify(r->width0, lvl)) &&
54 (b->y >= 0) && (b->y + b->height <= u_minify(r->height0, lvl)) &&
55 (b->z >= 0) && (b->z + b->depth <= last_layer);
56 }
57
58 static bool
59 ok_format(enum pipe_format pfmt)
60 {
61 enum a6xx_color_fmt fmt = fd6_pipe2color(pfmt);
62
63 switch (pfmt) {
64 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
65 case PIPE_FORMAT_Z24X8_UNORM:
66 case PIPE_FORMAT_Z16_UNORM:
67 case PIPE_FORMAT_Z32_UNORM:
68 case PIPE_FORMAT_Z32_FLOAT:
69 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
70 case PIPE_FORMAT_S8_UINT:
71 return true;
72 default:
73 break;
74 }
75
76 if (fmt == ~0)
77 return false;
78
79 if (fd6_ifmt(fmt) == 0)
80 return false;
81
82 return true;
83 }
84
85 #define DEBUG_BLIT 0
86 #define DEBUG_BLIT_FALLBACK 0
87
88 #define fail_if(cond) \
89 do { \
90 if (cond) { \
91 if (DEBUG_BLIT_FALLBACK) { \
92 fprintf(stderr, "falling back: %s for blit:\n", #cond); \
93 util_dump_blit_info(stderr, info); \
94 fprintf(stderr, "\nsrc: "); \
95 util_dump_resource(stderr, info->src.resource); \
96 fprintf(stderr, "\ndst: "); \
97 util_dump_resource(stderr, info->dst.resource); \
98 fprintf(stderr, "\n"); \
99 } \
100 return false; \
101 } \
102 } while (0)
103
104 static bool
105 can_do_blit(const struct pipe_blit_info *info)
106 {
107 /* I think we can do scaling, but not in z dimension since that would
108 * require blending..
109 */
110 fail_if(info->dst.box.depth != info->src.box.depth);
111
112 /* Fail if unsupported format: */
113 fail_if(!ok_format(info->src.format));
114 fail_if(!ok_format(info->dst.format));
115
116 /* We can blit if both or neither formats are compressed formats... */
117 fail_if(util_format_is_compressed(info->src.format) !=
118 util_format_is_compressed(info->src.format));
119
120 /* ... but only if they're the same compression format. */
121 fail_if(util_format_is_compressed(info->src.format) &&
122 info->src.format != info->dst.format);
123
124 fail_if(!ok_dims(info->src.resource, &info->src.box, info->src.level));
125
126 fail_if(!ok_dims(info->dst.resource, &info->dst.box, info->dst.level));
127
128 debug_assert(info->dst.box.width >= 0);
129 debug_assert(info->dst.box.height >= 0);
130 debug_assert(info->dst.box.depth >= 0);
131
132 fail_if(info->dst.resource->nr_samples > 1);
133
134 fail_if(info->window_rectangle_include);
135
136 const struct util_format_description *src_desc =
137 util_format_description(info->src.format);
138 const struct util_format_description *dst_desc =
139 util_format_description(info->dst.format);
140 const int common_channels = MIN2(src_desc->nr_channels, dst_desc->nr_channels);
141
142 if (info->mask & PIPE_MASK_RGBA) {
143 for (int i = 0; i < common_channels; i++) {
144 fail_if(memcmp(&src_desc->channel[i],
145 &dst_desc->channel[i],
146 sizeof(src_desc->channel[0])));
147 }
148 }
149
150 fail_if(info->alpha_blend);
151
152 return true;
153 }
154
155 static void
156 emit_setup(struct fd_batch *batch)
157 {
158 struct fd_ringbuffer *ring = batch->draw;
159
160 fd6_event_write(batch, ring, 0x1d, true);
161 fd6_event_write(batch, ring, FACENESS_FLUSH, true);
162 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
163 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_DEPTH, false);
164 }
165
166 static uint32_t
167 blit_control(enum a6xx_color_fmt fmt, bool is_srgb)
168 {
169 enum a6xx_2d_ifmt ifmt = fd6_ifmt(fmt);
170
171 if (is_srgb) {
172 assert(ifmt == R2D_UNORM8);
173 ifmt = R2D_UNORM8_SRGB;
174 }
175
176 return A6XX_RB_2D_BLIT_CNTL_MASK(0xf) |
177 A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(fmt) |
178 A6XX_RB_2D_BLIT_CNTL_IFMT(ifmt);
179 }
180
181 /* buffers need to be handled specially since x/width can exceed the bounds
182 * supported by hw.. if necessary decompose into (potentially) two 2D blits
183 */
184 static void
185 emit_blit_buffer(struct fd_context *ctx, struct fd_ringbuffer *ring,
186 const struct pipe_blit_info *info)
187 {
188 const struct pipe_box *sbox = &info->src.box;
189 const struct pipe_box *dbox = &info->dst.box;
190 struct fd_resource *src, *dst;
191 unsigned sshift, dshift;
192
193 if (DEBUG_BLIT) {
194 fprintf(stderr, "buffer blit: ");
195 util_dump_blit_info(stderr, info);
196 fprintf(stderr, "\ndst resource: ");
197 util_dump_resource(stderr, info->dst.resource);
198 fprintf(stderr, "\nsrc resource: ");
199 util_dump_resource(stderr, info->src.resource);
200 fprintf(stderr, "\n");
201 }
202
203 src = fd_resource(info->src.resource);
204 dst = fd_resource(info->dst.resource);
205
206 debug_assert(src->layout.cpp == 1);
207 debug_assert(dst->layout.cpp == 1);
208 debug_assert(info->src.resource->format == info->dst.resource->format);
209 debug_assert((sbox->y == 0) && (sbox->height == 1));
210 debug_assert((dbox->y == 0) && (dbox->height == 1));
211 debug_assert((sbox->z == 0) && (sbox->depth == 1));
212 debug_assert((dbox->z == 0) && (dbox->depth == 1));
213 debug_assert(sbox->width == dbox->width);
214 debug_assert(info->src.level == 0);
215 debug_assert(info->dst.level == 0);
216
217 /*
218 * Buffers can have dimensions bigger than max width, remap into
219 * multiple 1d blits to fit within max dimension
220 *
221 * Note that blob uses .ARRAY_PITCH=128 for blitting buffers, which
222 * seems to prevent overfetch related faults. Not quite sure what
223 * the deal is there.
224 *
225 * Low 6 bits of SRC/DST addresses need to be zero (ie. address
226 * aligned to 64) so we need to shift src/dst x1/x2 to make up the
227 * difference. On top of already splitting up the blit so width
228 * isn't > 16k.
229 *
230 * We perhaps could do a bit better, if src and dst are aligned but
231 * in the worst case this means we have to split the copy up into
232 * 16k (0x4000) minus 64 (0x40).
233 */
234
235 sshift = sbox->x & 0x3f;
236 dshift = dbox->x & 0x3f;
237
238 OUT_PKT7(ring, CP_SET_MARKER, 1);
239 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
240
241 uint32_t blit_cntl = blit_control(RB6_R8_UNORM, false) | 0x20000000;
242 OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
243 OUT_RING(ring, blit_cntl);
244
245 OUT_PKT4(ring, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);
246 OUT_RING(ring, blit_cntl);
247
248 for (unsigned off = 0; off < sbox->width; off += (0x4000 - 0x40)) {
249 unsigned soff, doff, w, p;
250
251 soff = (sbox->x + off) & ~0x3f;
252 doff = (dbox->x + off) & ~0x3f;
253
254 w = MIN2(sbox->width - off, (0x4000 - 0x40));
255 p = align(w, 64);
256
257 debug_assert((soff + w) <= fd_bo_size(src->bo));
258 debug_assert((doff + w) <= fd_bo_size(dst->bo));
259
260 /*
261 * Emit source:
262 */
263 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 10);
264 OUT_RING(ring, A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(RB6_R8_UNORM) |
265 A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(TILE6_LINEAR) |
266 A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(WZYX) |
267 0x500000);
268 OUT_RING(ring, A6XX_SP_PS_2D_SRC_SIZE_WIDTH(sshift + w) |
269 A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(1)); /* SP_PS_2D_SRC_SIZE */
270 OUT_RELOC(ring, src->bo, soff, 0, 0); /* SP_PS_2D_SRC_LO/HI */
271 OUT_RING(ring, A6XX_SP_PS_2D_SRC_PITCH_PITCH(p));
272
273 OUT_RING(ring, 0x00000000);
274 OUT_RING(ring, 0x00000000);
275 OUT_RING(ring, 0x00000000);
276 OUT_RING(ring, 0x00000000);
277 OUT_RING(ring, 0x00000000);
278
279 /*
280 * Emit destination:
281 */
282 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
283 OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(RB6_R8_UNORM) |
284 A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
285 A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
286 OUT_RELOCW(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
287 OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(p));
288 OUT_RING(ring, 0x00000000);
289 OUT_RING(ring, 0x00000000);
290 OUT_RING(ring, 0x00000000);
291 OUT_RING(ring, 0x00000000);
292 OUT_RING(ring, 0x00000000);
293
294 /*
295 * Blit command:
296 */
297 OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
298 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X_X(sshift));
299 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X_X(sshift + w - 1));
300 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y_Y(0));
301 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y_Y(0));
302
303 OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
304 OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(dshift) | A6XX_GRAS_2D_DST_TL_Y(0));
305 OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(dshift + w - 1) | A6XX_GRAS_2D_DST_BR_Y(0));
306
307 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
308 OUT_RING(ring, 0x3f);
309 OUT_WFI5(ring);
310
311 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1);
312 OUT_RING(ring, 0);
313
314 OUT_PKT4(ring, REG_A6XX_SP_2D_SRC_FORMAT, 1);
315 OUT_RING(ring, 0xf180);
316
317 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
318 OUT_RING(ring, fd6_context(ctx)->magic.RB_UNKNOWN_8E04_blit);
319
320 OUT_PKT7(ring, CP_BLIT, 1);
321 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
322
323 OUT_WFI5(ring);
324
325 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
326 OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
327 }
328 }
329
330 static void
331 emit_blit_or_clear_texture(struct fd_context *ctx, struct fd_ringbuffer *ring,
332 const struct pipe_blit_info *info, union pipe_color_union *color)
333 {
334 const struct pipe_box *sbox = &info->src.box;
335 const struct pipe_box *dbox = &info->dst.box;
336 struct fd_resource *src, *dst;
337 struct fdl_slice *sslice, *dslice;
338 enum a6xx_color_fmt sfmt, dfmt;
339 enum a6xx_tile_mode stile, dtile;
340 enum a3xx_color_swap sswap, dswap;
341 unsigned spitch, dpitch;
342 int sx1, sy1, sx2, sy2;
343 int dx1, dy1, dx2, dy2;
344
345 if (DEBUG_BLIT) {
346 fprintf(stderr, "texture blit: ");
347 util_dump_blit_info(stderr, info);
348 fprintf(stderr, "\ndst resource: ");
349 util_dump_resource(stderr, info->dst.resource);
350 fprintf(stderr, "\nsrc resource: ");
351 util_dump_resource(stderr, info->src.resource);
352 fprintf(stderr, "\n");
353 }
354
355 src = fd_resource(info->src.resource);
356 dst = fd_resource(info->dst.resource);
357
358 sslice = fd_resource_slice(src, info->src.level);
359 dslice = fd_resource_slice(dst, info->dst.level);
360
361 sfmt = fd6_pipe2color(info->src.format);
362 dfmt = fd6_pipe2color(info->dst.format);
363
364 int blocksize = util_format_get_blocksize(info->src.format);
365 int blockwidth = util_format_get_blockwidth(info->src.format);
366 int blockheight = util_format_get_blockheight(info->src.format);
367 int nelements;
368
369 stile = fd_resource_tile_mode(info->src.resource, info->src.level);
370 dtile = fd_resource_tile_mode(info->dst.resource, info->dst.level);
371
372 /* Linear levels of a tiled resource are always WZYX, so look at
373 * rsc->tile_mode to determine the swap.
374 */
375 sswap = fd6_resource_swap(src, info->src.format);
376 dswap = fd6_resource_swap(dst, info->dst.format);
377
378 if (util_format_is_compressed(info->src.format)) {
379 debug_assert(info->src.format == info->dst.format);
380 sfmt = dfmt = RB6_R8_UNORM;
381 nelements = blocksize;
382 } else {
383 debug_assert(!util_format_is_compressed(info->dst.format));
384 nelements = (dst->base.nr_samples ? dst->base.nr_samples : 1);
385 }
386
387 spitch = DIV_ROUND_UP(sslice->pitch, blockwidth) * src->layout.cpp;
388 dpitch = DIV_ROUND_UP(dslice->pitch, blockwidth) * dst->layout.cpp;
389
390 sx1 = sbox->x / blockwidth * nelements;
391 sy1 = sbox->y / blockheight;
392 sx2 = DIV_ROUND_UP(sbox->x + sbox->width, blockwidth) * nelements - 1;
393 sy2 = DIV_ROUND_UP(sbox->y + sbox->height, blockheight) - 1;
394
395 dx1 = dbox->x / blockwidth * nelements;
396 dy1 = dbox->y / blockheight;
397 dx2 = DIV_ROUND_UP(dbox->x + dbox->width, blockwidth) * nelements - 1;
398 dy2 = DIV_ROUND_UP(dbox->y + dbox->height, blockheight) - 1;
399
400 uint32_t width = DIV_ROUND_UP(u_minify(src->base.width0, info->src.level), blockwidth) * nelements;
401 uint32_t height = DIV_ROUND_UP(u_minify(src->base.height0, info->src.level), blockheight);
402
403 OUT_PKT7(ring, CP_SET_MARKER, 1);
404 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
405
406 uint32_t blit_cntl = blit_control(dfmt, util_format_is_srgb(info->dst.format));
407
408 if (color) {
409 blit_cntl |= A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR;
410
411 switch (info->dst.format) {
412 case PIPE_FORMAT_Z24X8_UNORM:
413 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
414 case PIPE_FORMAT_X24S8_UINT: {
415 uint32_t depth_unorm24 = color->f[0] * ((1u << 24) - 1);
416 uint8_t stencil = color->ui[1];
417 color->ui[0] = depth_unorm24 & 0xff;
418 color->ui[1] = (depth_unorm24 >> 8) & 0xff;
419 color->ui[2] = (depth_unorm24 >> 16) & 0xff;
420 color->ui[3] = stencil;
421
422 dfmt = RB6_Z24_UNORM_S8_UINT_AS_R8G8B8A8;
423 break;
424 }
425 case PIPE_FORMAT_B5G6R5_UNORM:
426 case PIPE_FORMAT_B5G5R5A1_UNORM:
427 case PIPE_FORMAT_B5G5R5X1_UNORM:
428 case PIPE_FORMAT_B4G4R4A4_UNORM:
429 color->ui[0] = float_to_ubyte(color->f[0]);
430 color->ui[1] = float_to_ubyte(color->f[1]);
431 color->ui[2] = float_to_ubyte(color->f[2]);
432 color->ui[3] = float_to_ubyte(color->f[3]);
433 break;
434 default:
435 break;
436 }
437
438 OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
439
440 switch (fd6_ifmt(dfmt)) {
441 case R2D_UNORM8:
442 case R2D_UNORM8_SRGB:
443 OUT_RING(ring, float_to_ubyte(color->f[0]));
444 OUT_RING(ring, float_to_ubyte(color->f[1]));
445 OUT_RING(ring, float_to_ubyte(color->f[2]));
446 OUT_RING(ring, float_to_ubyte(color->f[3]));
447 break;
448 case R2D_FLOAT16:
449 OUT_RING(ring, _mesa_float_to_half(color->f[0]));
450 OUT_RING(ring, _mesa_float_to_half(color->f[1]));
451 OUT_RING(ring, _mesa_float_to_half(color->f[2]));
452 OUT_RING(ring, _mesa_float_to_half(color->f[3]));
453 sfmt = RB6_R16G16B16A16_FLOAT;
454 break;
455
456 case R2D_FLOAT32:
457 case R2D_INT32:
458 case R2D_INT16:
459 case R2D_INT8:
460 case R2D_RAW:
461 default:
462 OUT_RING(ring, color->ui[0]);
463 OUT_RING(ring, color->ui[1]);
464 OUT_RING(ring, color->ui[2]);
465 OUT_RING(ring, color->ui[3]);
466 break;
467 }
468 }
469
470 if (dtile != stile)
471 blit_cntl |= 0x20000000;
472
473 if (info->scissor_enable) {
474 OUT_PKT4(ring, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
475 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_1_X(info->scissor.minx) |
476 A6XX_GRAS_RESOLVE_CNTL_1_Y(info->scissor.miny));
477 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_1_X(info->scissor.maxx - 1) |
478 A6XX_GRAS_RESOLVE_CNTL_1_Y(info->scissor.maxy - 1));
479 blit_cntl |= A6XX_RB_2D_BLIT_CNTL_SCISSOR;
480 }
481
482 OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
483 OUT_RING(ring, blit_cntl);
484
485 OUT_PKT4(ring, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);
486 OUT_RING(ring, blit_cntl);
487
488 for (unsigned i = 0; i < info->dst.box.depth; i++) {
489 unsigned soff = fd_resource_offset(src, info->src.level, sbox->z + i);
490 unsigned doff = fd_resource_offset(dst, info->dst.level, dbox->z + i);
491 bool subwc_enabled = fd_resource_ubwc_enabled(src, info->src.level);
492 bool dubwc_enabled = fd_resource_ubwc_enabled(dst, info->dst.level);
493
494 /*
495 * Emit source:
496 */
497 uint32_t filter = 0;
498 if (info->filter == PIPE_TEX_FILTER_LINEAR)
499 filter = A6XX_SP_PS_2D_SRC_INFO_FILTER;
500
501 enum a3xx_msaa_samples samples = fd_msaa_samples(src->base.nr_samples);
502
503 if (sfmt == RB6_R10G10B10A2_UNORM)
504 sfmt = RB6_R10G10B10A2_FLOAT16;
505
506 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 10);
507 OUT_RING(ring, A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(sfmt) |
508 A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(stile) |
509 A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(sswap) |
510 A6XX_SP_PS_2D_SRC_INFO_SAMPLES(samples) |
511 COND(samples > MSAA_ONE && (info->mask & PIPE_MASK_RGBA),
512 A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE) |
513 COND(subwc_enabled, A6XX_SP_PS_2D_SRC_INFO_FLAGS) |
514 COND(util_format_is_srgb(info->src.format), A6XX_SP_PS_2D_SRC_INFO_SRGB) |
515 0x500000 | filter);
516 OUT_RING(ring, A6XX_SP_PS_2D_SRC_SIZE_WIDTH(width) |
517 A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(height)); /* SP_PS_2D_SRC_SIZE */
518 OUT_RELOC(ring, src->bo, soff, 0, 0); /* SP_PS_2D_SRC_LO/HI */
519 OUT_RING(ring, A6XX_SP_PS_2D_SRC_PITCH_PITCH(spitch));
520
521 OUT_RING(ring, 0x00000000);
522 OUT_RING(ring, 0x00000000);
523 OUT_RING(ring, 0x00000000);
524 OUT_RING(ring, 0x00000000);
525 OUT_RING(ring, 0x00000000);
526
527 if (subwc_enabled) {
528 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_FLAGS_LO, 6);
529 fd6_emit_flag_reference(ring, src, info->src.level, sbox->z + i);
530 OUT_RING(ring, 0x00000000);
531 OUT_RING(ring, 0x00000000);
532 OUT_RING(ring, 0x00000000);
533 }
534
535 /*
536 * Emit destination:
537 */
538 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
539 OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(dfmt) |
540 A6XX_RB_2D_DST_INFO_TILE_MODE(dtile) |
541 A6XX_RB_2D_DST_INFO_COLOR_SWAP(dswap) |
542 COND(util_format_is_srgb(info->dst.format), A6XX_RB_2D_DST_INFO_SRGB) |
543 COND(dubwc_enabled, A6XX_RB_2D_DST_INFO_FLAGS));
544 OUT_RELOCW(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
545 OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(dpitch));
546 OUT_RING(ring, 0x00000000);
547 OUT_RING(ring, 0x00000000);
548 OUT_RING(ring, 0x00000000);
549 OUT_RING(ring, 0x00000000);
550 OUT_RING(ring, 0x00000000);
551
552 if (dubwc_enabled) {
553 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_FLAGS_LO, 6);
554 fd6_emit_flag_reference(ring, dst, info->dst.level, dbox->z + i);
555 OUT_RING(ring, 0x00000000);
556 OUT_RING(ring, 0x00000000);
557 OUT_RING(ring, 0x00000000);
558 }
559
560 /*
561 * Blit command:
562 */
563 OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
564 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X_X(sx1));
565 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X_X(sx2));
566 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y_Y(sy1));
567 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y_Y(sy2));
568
569 OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
570 OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(dx1) | A6XX_GRAS_2D_DST_TL_Y(dy1));
571 OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(dx2) | A6XX_GRAS_2D_DST_BR_Y(dy2));
572
573 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
574 OUT_RING(ring, 0x3f);
575 OUT_WFI5(ring);
576
577 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1);
578 OUT_RING(ring, 0);
579
580 if (dfmt == RB6_R10G10B10A2_UNORM)
581 sfmt = RB6_R16G16B16A16_FLOAT;
582
583 /* This register is probably badly named... it seems that it's
584 * controlling the internal/accumulator format or something like
585 * that. It's certainly not tied to only the src format.
586 */
587 OUT_PKT4(ring, REG_A6XX_SP_2D_SRC_FORMAT, 1);
588 OUT_RING(ring, A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT(sfmt) |
589 COND(util_format_is_pure_sint(info->src.format),
590 A6XX_SP_2D_SRC_FORMAT_SINT) |
591 COND(util_format_is_pure_uint(info->src.format),
592 A6XX_SP_2D_SRC_FORMAT_UINT) |
593 COND(util_format_is_snorm(info->src.format),
594 A6XX_SP_2D_SRC_FORMAT_SINT |
595 A6XX_SP_2D_SRC_FORMAT_NORM) |
596 COND(util_format_is_unorm(info->src.format),
597 // TODO sometimes blob uses UINT+NORM but dEQP seems unhappy about that
598 // A6XX_SP_2D_SRC_FORMAT_UINT |
599 A6XX_SP_2D_SRC_FORMAT_NORM) |
600 COND(util_format_is_srgb(info->dst.format), A6XX_SP_2D_SRC_FORMAT_SRGB) |
601 A6XX_SP_2D_SRC_FORMAT_MASK(0xf));
602
603 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
604 OUT_RING(ring, fd6_context(ctx)->magic.RB_UNKNOWN_8E04_blit);
605
606 OUT_PKT7(ring, CP_BLIT, 1);
607 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
608
609 OUT_WFI5(ring);
610
611 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
612 OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
613 }
614 }
615
616 void
617 fd6_clear_surface(struct fd_context *ctx,
618 struct fd_ringbuffer *ring, struct pipe_surface *psurf,
619 uint32_t width, uint32_t height, union pipe_color_union *color)
620 {
621 struct pipe_blit_info info = {};
622
623 info.dst.resource = psurf->texture;
624 info.dst.level = psurf->u.tex.level;
625 info.dst.box.x = 0;
626 info.dst.box.y = 0;
627 info.dst.box.z = psurf->u.tex.first_layer;
628 info.dst.box.width = width;
629 info.dst.box.height = height;
630 info.dst.box.depth = psurf->u.tex.last_layer + 1 - psurf->u.tex.first_layer;
631 info.dst.format = psurf->format;
632 info.src = info.dst;
633 info.mask = util_format_get_mask(psurf->format);
634 info.filter = PIPE_TEX_FILTER_NEAREST;
635 info.scissor_enable = 0;
636
637 emit_blit_or_clear_texture(ctx, ring, &info, color);
638 }
639
640 static bool handle_rgba_blit(struct fd_context *ctx, const struct pipe_blit_info *info);
641
642 /**
643 * Re-written z/s blits can still fail for various reasons (for example MSAA).
644 * But we want to do the fallback blit with the re-written pipe_blit_info,
645 * in particular as u_blitter cannot blit stencil. So handle the fallback
646 * ourself and never "fail".
647 */
648 static bool
649 do_rewritten_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
650 {
651 bool success = handle_rgba_blit(ctx, info);
652 if (!success)
653 success = fd_blitter_blit(ctx, info);
654 debug_assert(success); /* fallback should never fail! */
655 return success;
656 }
657
658 /**
659 * Handle depth/stencil blits either via u_blitter and/or re-writing the
660 * blit into an equivilant format that we can handle
661 */
662 static bool
663 handle_zs_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
664 {
665 struct pipe_blit_info blit = *info;
666
667 if (DEBUG_BLIT) {
668 fprintf(stderr, "---- handle_zs_blit: ");
669 util_dump_blit_info(stderr, info);
670 fprintf(stderr, "\ndst resource: ");
671 util_dump_resource(stderr, info->dst.resource);
672 fprintf(stderr, "\nsrc resource: ");
673 util_dump_resource(stderr, info->src.resource);
674 fprintf(stderr, "\n");
675 }
676
677 switch (info->dst.format) {
678 case PIPE_FORMAT_S8_UINT:
679 debug_assert(info->mask == PIPE_MASK_S);
680 blit.mask = PIPE_MASK_R;
681 blit.src.format = PIPE_FORMAT_R8_UINT;
682 blit.dst.format = PIPE_FORMAT_R8_UINT;
683 return do_rewritten_blit(ctx, &blit);
684
685 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
686 if (info->mask & PIPE_MASK_Z) {
687 blit.mask = PIPE_MASK_R;
688 blit.src.format = PIPE_FORMAT_R32_FLOAT;
689 blit.dst.format = PIPE_FORMAT_R32_FLOAT;
690 do_rewritten_blit(ctx, &blit);
691 }
692
693 if (info->mask & PIPE_MASK_S) {
694 blit.mask = PIPE_MASK_R;
695 blit.src.format = PIPE_FORMAT_R8_UINT;
696 blit.dst.format = PIPE_FORMAT_R8_UINT;
697 blit.src.resource = &fd_resource(info->src.resource)->stencil->base;
698 blit.dst.resource = &fd_resource(info->dst.resource)->stencil->base;
699 do_rewritten_blit(ctx, &blit);
700 }
701
702 return true;
703
704 case PIPE_FORMAT_Z16_UNORM:
705 blit.mask = PIPE_MASK_R;
706 blit.src.format = PIPE_FORMAT_R16_UNORM;
707 blit.dst.format = PIPE_FORMAT_R16_UNORM;
708 return do_rewritten_blit(ctx, &blit);
709
710 case PIPE_FORMAT_Z32_UNORM:
711 case PIPE_FORMAT_Z32_FLOAT:
712 debug_assert(info->mask == PIPE_MASK_Z);
713 blit.mask = PIPE_MASK_R;
714 blit.src.format = PIPE_FORMAT_R32_UINT;
715 blit.dst.format = PIPE_FORMAT_R32_UINT;
716 return do_rewritten_blit(ctx, &blit);
717
718 case PIPE_FORMAT_Z24X8_UNORM:
719 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
720 blit.mask = 0;
721 if (info->mask & PIPE_MASK_Z)
722 blit.mask |= PIPE_MASK_R | PIPE_MASK_G | PIPE_MASK_B;
723 if (info->mask & PIPE_MASK_S)
724 blit.mask |= PIPE_MASK_A;
725 blit.src.format = PIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8;
726 blit.dst.format = PIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8;
727 return fd_blitter_blit(ctx, &blit);
728
729 default:
730 return false;
731 }
732 }
733
734 static bool
735 handle_rgba_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
736 {
737 struct fd_batch *batch;
738
739 debug_assert(!(info->mask & PIPE_MASK_ZS));
740
741 if (!can_do_blit(info))
742 return false;
743
744 fd_fence_ref(&ctx->last_fence, NULL);
745
746 batch = fd_bc_alloc_batch(&ctx->screen->batch_cache, ctx, true);
747
748 fd6_emit_restore(batch, batch->draw);
749 fd6_emit_lrz_flush(batch->draw);
750
751 mtx_lock(&ctx->screen->lock);
752
753 fd_batch_resource_used(batch, fd_resource(info->src.resource), false);
754 fd_batch_resource_used(batch, fd_resource(info->dst.resource), true);
755
756 mtx_unlock(&ctx->screen->lock);
757
758 emit_setup(batch);
759
760 if ((info->src.resource->target == PIPE_BUFFER) &&
761 (info->dst.resource->target == PIPE_BUFFER)) {
762 assert(fd_resource(info->src.resource)->layout.tile_mode == TILE6_LINEAR);
763 assert(fd_resource(info->dst.resource)->layout.tile_mode == TILE6_LINEAR);
764 emit_blit_buffer(ctx, batch->draw, info);
765 } else {
766 /* I don't *think* we need to handle blits between buffer <-> !buffer */
767 debug_assert(info->src.resource->target != PIPE_BUFFER);
768 debug_assert(info->dst.resource->target != PIPE_BUFFER);
769 emit_blit_or_clear_texture(ctx, batch->draw, info, NULL);
770 }
771
772 fd6_event_write(batch, batch->draw, 0x1d, true);
773 fd6_event_write(batch, batch->draw, FACENESS_FLUSH, true);
774 fd6_event_write(batch, batch->draw, CACHE_FLUSH_TS, true);
775 fd6_cache_inv(batch, batch->draw);
776
777 fd_resource(info->dst.resource)->valid = true;
778 batch->needs_flush = true;
779
780 fd_batch_flush(batch, false);
781 fd_batch_reference(&batch, NULL);
782
783 return true;
784 }
785
786 static bool
787 fd6_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
788 {
789 if (info->mask & PIPE_MASK_ZS)
790 return handle_zs_blit(ctx, info);
791 return handle_rgba_blit(ctx, info);
792 }
793
794 void
795 fd6_blitter_init(struct pipe_context *pctx)
796 {
797 if (fd_mesa_debug & FD_DBG_NOBLIT)
798 return;
799
800 fd_context(pctx)->blit = fd6_blit;
801 }
802
803 unsigned
804 fd6_tile_mode(const struct pipe_resource *tmpl)
805 {
806 /* if the mipmap level 0 is still too small to be tiled, then don't
807 * bother pretending:
808 */
809 if (fd_resource_level_linear(tmpl, 0))
810 return TILE6_LINEAR;
811
812 /* basically just has to be a format we can blit, so uploads/downloads
813 * via linear staging buffer works:
814 */
815 if (ok_format(tmpl->format))
816 return TILE6_3;
817
818 return TILE6_LINEAR;
819 }