src/gallium/drivers/freedreno/a6xx/fd6_context.h

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Rob Clark <robclark@freedesktop.org>
  26  */
  27
  28 #ifndef FD6_CONTEXT_H_
  29 #define FD6_CONTEXT_H_
  30
  31 #include "util/u_upload_mgr.h"
  32
  33 #include "freedreno_context.h"
  34
  35 #include "ir3/ir3_shader.h"
  36
  37 #include "a6xx.xml.h"
  38
  39 struct fd6_context {
  40         struct fd_context base;
  41
  42         /* Two buffers related to hw binning / visibility stream (VSC).
  43          * Compared to previous generations
  44          *   (1) we cannot specify individual buffers per VSC, instead
  45          *       just a pitch and base address
  46          *   (2) there is a second smaller buffer, for something.. we
  47          *       also stash VSC_BIN_SIZE at end of 2nd buffer.
  48          */
  49         struct fd_bo *vsc_data, *vsc_data2;
  50
  51         unsigned vsc_data_pitch, vsc_data2_pitch;
  52
  53         /* The 'control' mem BO is used for various housekeeping
  54          * functions.  See 'struct fd6_control'
  55          */
  56         struct fd_bo *control_mem;
  57         uint32_t seqno;
  58
  59         struct u_upload_mgr *border_color_uploader;
  60         struct pipe_resource *border_color_buf;
  61
  62         /* if *any* of bits are set in {v,f}saturate_{s,t,r} */
  63         bool vsaturate, fsaturate;
  64
  65         /* bitmask of sampler which needs coords clamped for vertex
  66          * shader:
  67          */
  68         uint16_t vsaturate_s, vsaturate_t, vsaturate_r;
  69
  70         /* bitmask of sampler which needs coords clamped for frag
  71          * shader:
  72          */
  73         uint16_t fsaturate_s, fsaturate_t, fsaturate_r;
  74
  75         /* some state changes require a different shader variant.  Keep
  76          * track of this so we know when we need to re-emit shader state
  77          * due to variant change.  See fixup_shader_state()
  78          */
  79         struct ir3_shader_key last_key;
  80
  81         /* number of active samples-passed queries: */
  82         int samples_passed_queries;
  83
  84         /* maps per-shader-stage state plus variant key to hw
  85          * program stateobj:
  86          */
  87         struct ir3_cache *shader_cache;
  88
  89         /* cached stateobjs to avoid hashtable lookup when not dirty: */
  90         const struct fd6_program_state *prog;
  91
  92         uint16_t tex_seqno;
  93         struct hash_table *tex_cache;
  94 };
  95
  96 static inline struct fd6_context *
  97 fd6_context(struct fd_context *ctx)
  98 {
  99         return (struct fd6_context *)ctx;
 100 }
 101
 102 struct pipe_context *
 103 fd6_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags);
 104
 105
 106 /* This struct defines the layout of the fd6_context::control buffer: */
 107 struct fd6_control {
 108         uint32_t seqno;          /* seqno for async CP_EVENT_WRITE, etc */
 109         uint32_t _pad0;
 110         uint32_t flush_base;     /* dummy address for VPC_SO[i].FLUSH_BASE_LO/HI */
 111         uint32_t _pad1;
 112         /* flag set from cmdstream when VSC overflow detected: */
 113         volatile uint32_t vsc_overflow;
 114         uint32_t _pad2;
 115         uint32_t vsc_scratch;
 116         uint32_t _pad3;
 117 };
 118
 119 #define control_ptr(fd6_ctx, member)  \
 120         (fd6_ctx)->control_mem, offsetof(struct fd6_control, member), 0, 0
 121
 122
 123 static inline void
 124 emit_marker6(struct fd_ringbuffer *ring, int scratch_idx)
 125 {
 126         extern unsigned marker_cnt;
 127         unsigned reg = REG_A6XX_CP_SCRATCH_REG(scratch_idx);
 128         OUT_PKT4(ring, reg, 1);
 129         OUT_RING(ring, ++marker_cnt);
 130 }
 131
 132 #endif /* FD6_CONTEXT_H_ */