src/gallium/drivers/freedreno/a6xx/fd6_draw.c

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Rob Clark <robclark@freedesktop.org>
  26  */
  27
  28 #include "pipe/p_state.h"
  29 #include "util/u_string.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_prim.h"
  32
  33 #include "freedreno_state.h"
  34 #include "freedreno_resource.h"
  35
  36 #include "fd6_draw.h"
  37 #include "fd6_context.h"
  38 #include "fd6_emit.h"
  39 #include "fd6_program.h"
  40 #include "fd6_format.h"
  41 #include "fd6_vsc.h"
  42 #include "fd6_zsa.h"
  43
  44 #include "fd6_pack.h"
  45
  46 static void
  47 draw_emit_indirect(struct fd_ringbuffer *ring,
  48                                    struct CP_DRAW_INDX_OFFSET_0 *draw0,
  49                                    const struct pipe_draw_info *info,
  50                                    unsigned index_offset)
  51 {
  52         struct fd_resource *ind = fd_resource(info->indirect->buffer);
  53
  54         if (info->index_size) {
  55                 struct pipe_resource *idx = info->index.resource;
  56                 unsigned max_indices = (idx->width0 - index_offset) / info->index_size;
  57
  58                 OUT_PKT(ring, CP_DRAW_INDX_INDIRECT,
  59                                 pack_CP_DRAW_INDX_OFFSET_0(*draw0),
  60                                 A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE(
  61                                                 fd_resource(idx)->bo, index_offset),
  62                                 A5XX_CP_DRAW_INDX_INDIRECT_3(.max_indices = max_indices),
  63                                 A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT(
  64                                                 ind->bo, info->indirect->offset)
  65                         );
  66         } else {
  67                 OUT_PKT(ring, CP_DRAW_INDIRECT,
  68                                 pack_CP_DRAW_INDX_OFFSET_0(*draw0),
  69                                 A5XX_CP_DRAW_INDIRECT_INDIRECT(
  70                                                 ind->bo, info->indirect->offset)
  71                         );
  72         }
  73 }
  74
  75 static void
  76 draw_emit(struct fd_ringbuffer *ring,
  77                   struct CP_DRAW_INDX_OFFSET_0 *draw0,
  78                   const struct pipe_draw_info *info,
  79                   unsigned index_offset)
  80 {
  81         if (info->index_size) {
  82                 assert(!info->has_user_indices);
  83
  84                 struct pipe_resource *idx_buffer = info->index.resource;
  85                 unsigned max_indices = (idx_buffer->width0 - index_offset) / info->index_size;
  86
  87                 OUT_PKT(ring, CP_DRAW_INDX_OFFSET,
  88                                 pack_CP_DRAW_INDX_OFFSET_0(*draw0),
  89                                 CP_DRAW_INDX_OFFSET_1(.num_instances = info->instance_count),
  90                                 CP_DRAW_INDX_OFFSET_2(.num_indices = info->count),
  91                                 CP_DRAW_INDX_OFFSET_3(.first_indx = info->start),
  92                                 A5XX_CP_DRAW_INDX_OFFSET_INDX_BASE(
  93                                                 fd_resource(idx_buffer)->bo, index_offset),
  94                                 A5XX_CP_DRAW_INDX_OFFSET_6(.max_indices = max_indices)
  95                         );
  96         } else {
  97                 OUT_PKT(ring, CP_DRAW_INDX_OFFSET,
  98                                 pack_CP_DRAW_INDX_OFFSET_0(*draw0),
  99                                 CP_DRAW_INDX_OFFSET_1(.num_instances = info->instance_count),
 100                                 CP_DRAW_INDX_OFFSET_2(.num_indices = info->count)
 101                         );
 102         }
 103 }
 104
 105 /* fixup dirty shader state in case some "unrelated" (from the state-
 106  * tracker's perspective) state change causes us to switch to a
 107  * different variant.
 108  */
 109 static void
 110 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
 111 {
 112         struct fd6_context *fd6_ctx = fd6_context(ctx);
 113         struct ir3_shader_key *last_key = &fd6_ctx->last_key;
 114
 115         if (!ir3_shader_key_equal(last_key, key)) {
 116                 if (ir3_shader_key_changes_fs(last_key, key)) {
 117                         ctx->dirty_shader[PIPE_SHADER_FRAGMENT] |= FD_DIRTY_SHADER_PROG;
 118                         ctx->dirty |= FD_DIRTY_PROG;
 119                 }
 120
 121                 if (ir3_shader_key_changes_vs(last_key, key)) {
 122                         ctx->dirty_shader[PIPE_SHADER_VERTEX] |= FD_DIRTY_SHADER_PROG;
 123                         ctx->dirty |= FD_DIRTY_PROG;
 124                 }
 125
 126                 fd6_ctx->last_key = *key;
 127         }
 128 }
 129
 130 static void
 131 fixup_draw_state(struct fd_context *ctx, struct fd6_emit *emit)
 132 {
 133         if (ctx->last.dirty ||
 134                         (ctx->last.primitive_restart != emit->primitive_restart)) {
 135                 /* rasterizer state is effected by primitive-restart: */
 136                 ctx->dirty |= FD_DIRTY_RASTERIZER;
 137                 ctx->last.primitive_restart = emit->primitive_restart;
 138         }
 139 }
 140
 141 static bool
 142 fd6_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
 143              unsigned index_offset)
 144 {
 145         struct fd6_context *fd6_ctx = fd6_context(ctx);
 146         struct fd6_emit emit = {
 147                 .ctx = ctx,
 148                 .vtx  = &ctx->vtx,
 149                 .info = info,
 150                 .key = {
 151                         .vs = ctx->prog.vs,
 152                         .gs = ctx->prog.gs,
 153                         .fs = ctx->prog.fs,
 154                         .key = {
 155                                 .color_two_side = ctx->rasterizer->light_twoside,
 156                                 .vclamp_color = ctx->rasterizer->clamp_vertex_color,
 157                                 .fclamp_color = ctx->rasterizer->clamp_fragment_color,
 158                                 .rasterflat = ctx->rasterizer->flatshade,
 159                                 .ucp_enables = ctx->rasterizer->clip_plane_enable,
 160                                 .has_per_samp = (fd6_ctx->fsaturate || fd6_ctx->vsaturate),
 161                                 .vsaturate_s = fd6_ctx->vsaturate_s,
 162                                 .vsaturate_t = fd6_ctx->vsaturate_t,
 163                                 .vsaturate_r = fd6_ctx->vsaturate_r,
 164                                 .fsaturate_s = fd6_ctx->fsaturate_s,
 165                                 .fsaturate_t = fd6_ctx->fsaturate_t,
 166                                 .fsaturate_r = fd6_ctx->fsaturate_r,
 167                                 .vsamples = ctx->tex[PIPE_SHADER_VERTEX].samples,
 168                                 .fsamples = ctx->tex[PIPE_SHADER_FRAGMENT].samples,
 169                                 .sample_shading = (ctx->min_samples > 1),
 170                                 .msaa = (ctx->framebuffer.samples > 1),
 171                         },
 172                 },
 173                 .rasterflat = ctx->rasterizer->flatshade,
 174                 .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
 175                 .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
 176                 .primitive_restart = info->primitive_restart && info->index_size,
 177         };
 178
 179         if (info->mode == PIPE_PRIM_PATCHES) {
 180                 emit.key.hs = ctx->prog.hs;
 181                 emit.key.ds = ctx->prog.ds;
 182
 183                 shader_info *ds_info = &emit.key.ds->nir->info;
 184                 emit.key.key.tessellation = ir3_tess_mode(ds_info->tess.primitive_mode);
 185         }
 186
 187         if (emit.key.gs)
 188                 emit.key.key.has_gs = true;
 189
 190         if (!(emit.key.hs || emit.key.ds || emit.key.gs || info->indirect))
 191                 fd6_vsc_update_sizes(ctx->batch, info);
 192
 193         fixup_shader_state(ctx, &emit.key.key);
 194
 195         if (!(ctx->dirty & FD_DIRTY_PROG)) {
 196                 emit.prog = fd6_ctx->prog;
 197         } else {
 198                 fd6_ctx->prog = fd6_emit_get_prog(&emit);
 199         }
 200
 201         /* bail if compile failed: */
 202         if (!fd6_ctx->prog)
 203                 return NULL;
 204
 205         emit.dirty = ctx->dirty;      /* *after* fixup_shader_state() */
 206         emit.bs = fd6_emit_get_prog(&emit)->bs;
 207         emit.vs = fd6_emit_get_prog(&emit)->vs;
 208         emit.hs = fd6_emit_get_prog(&emit)->hs;
 209         emit.ds = fd6_emit_get_prog(&emit)->ds;
 210         emit.gs = fd6_emit_get_prog(&emit)->gs;
 211         emit.fs = fd6_emit_get_prog(&emit)->fs;
 212
 213         ctx->stats.vs_regs += ir3_shader_halfregs(emit.vs);
 214         ctx->stats.hs_regs += COND(emit.hs, ir3_shader_halfregs(emit.hs));
 215         ctx->stats.ds_regs += COND(emit.ds, ir3_shader_halfregs(emit.ds));
 216         ctx->stats.gs_regs += COND(emit.gs, ir3_shader_halfregs(emit.gs));
 217         ctx->stats.fs_regs += ir3_shader_halfregs(emit.fs);
 218
 219         struct fd_ringbuffer *ring = ctx->batch->draw;
 220
 221         struct CP_DRAW_INDX_OFFSET_0 draw0 = {
 222                         .prim_type = ctx->primtypes[info->mode],
 223                         .vis_cull  = USE_VISIBILITY,
 224                         .gs_enable = !!emit.key.gs,
 225         };
 226
 227         if (info->index_size) {
 228                 draw0.source_select = DI_SRC_SEL_DMA;
 229                 draw0.index_size = fd4_size2indextype(info->index_size);
 230         } else {
 231                 draw0.source_select = DI_SRC_SEL_AUTO_INDEX;
 232         }
 233
 234         if (info->mode == PIPE_PRIM_PATCHES) {
 235                 shader_info *ds_info = &emit.ds->shader->nir->info;
 236                 uint32_t factor_stride;
 237
 238                 switch (ds_info->tess.primitive_mode) {
 239                 case GL_ISOLINES:
 240                         draw0.patch_type = TESS_ISOLINES;
 241                         factor_stride = 12;
 242                         break;
 243                 case GL_TRIANGLES:
 244                         draw0.patch_type = TESS_TRIANGLES;
 245                         factor_stride = 20;
 246                         break;
 247                 case GL_QUADS:
 248                         draw0.patch_type = TESS_QUADS;
 249                         factor_stride = 28;
 250                         break;
 251                 default:
 252                         unreachable("bad tessmode");
 253                 }
 254
 255                 draw0.prim_type = DI_PT_PATCHES0 + info->vertices_per_patch;
 256                 draw0.tess_enable = true;
 257
 258                 ctx->batch->tessellation = true;
 259                 ctx->batch->tessparam_size = MAX2(ctx->batch->tessparam_size,
 260                                 emit.hs->output_size * 4 * info->count);
 261                 ctx->batch->tessfactor_size = MAX2(ctx->batch->tessfactor_size,
 262                                 factor_stride * info->count);
 263
 264                 if (!ctx->batch->tess_addrs_constobj) {
 265                         /* Reserve space for the bo address - we'll write them later in
 266                          * setup_tess_buffers().  We need 2 bo address, but indirect
 267                          * constant upload needs at least 4 vec4s.
 268                          */
 269                         unsigned size = 4 * 16;
 270
 271                         ctx->batch->tess_addrs_constobj = fd_submit_new_ringbuffer(
 272                                 ctx->batch->submit, size, FD_RINGBUFFER_STREAMING);
 273
 274                         ctx->batch->tess_addrs_constobj->cur += size;
 275                 }
 276         }
 277
 278         uint32_t index_start = info->index_size ? info->index_bias : info->start;
 279         if (ctx->last.dirty || (ctx->last.index_start != index_start)) {
 280                 OUT_PKT4(ring, REG_A6XX_VFD_INDEX_OFFSET, 1);
 281                 OUT_RING(ring, index_start); /* VFD_INDEX_OFFSET */
 282                 ctx->last.index_start = index_start;
 283         }
 284
 285         if (ctx->last.dirty || (ctx->last.instance_start != info->start_instance)) {
 286                 OUT_PKT4(ring, REG_A6XX_VFD_INSTANCE_START_OFFSET, 1);
 287                 OUT_RING(ring, info->start_instance); /* VFD_INSTANCE_START_OFFSET */
 288                 ctx->last.instance_start = info->start_instance;
 289         }
 290
 291         uint32_t restart_index = info->primitive_restart ? info->restart_index : 0xffffffff;
 292         if (ctx->last.dirty || (ctx->last.restart_index != restart_index)) {
 293                 OUT_PKT4(ring, REG_A6XX_PC_RESTART_INDEX, 1);
 294                 OUT_RING(ring, restart_index); /* PC_RESTART_INDEX */
 295                 ctx->last.restart_index = restart_index;
 296         }
 297
 298         fixup_draw_state(ctx, &emit);
 299
 300         fd6_emit_state(ring, &emit);
 301
 302         /* for debug after a lock up, write a unique counter value
 303          * to scratch7 for each draw, to make it easier to match up
 304          * register dumps to cmdstream.  The combination of IB
 305          * (scratch6) and DRAW is enough to "triangulate" the
 306          * particular draw that caused lockup.
 307          */
 308         emit_marker6(ring, 7);
 309
 310         if (info->indirect) {
 311                 draw_emit_indirect(ring, &draw0, info, index_offset);
 312         } else {
 313                 draw_emit(ring, &draw0, info, index_offset);
 314         }
 315
 316         emit_marker6(ring, 7);
 317         fd_reset_wfi(ctx->batch);
 318
 319         if (emit.streamout_mask) {
 320                 struct fd_ringbuffer *ring = ctx->batch->draw;
 321
 322                 for (unsigned i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
 323                         if (emit.streamout_mask & (1 << i)) {
 324                                 fd6_event_write(ctx->batch, ring, FLUSH_SO_0 + i, false);
 325                         }
 326                 }
 327         }
 328
 329         fd_context_all_clean(ctx);
 330
 331         return true;
 332 }
 333
 334 static void
 335 fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
 336 {
 337         struct fd_ringbuffer *ring;
 338         struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
 339
 340         if (batch->lrz_clear) {
 341                 fd_ringbuffer_del(batch->lrz_clear);
 342         }
 343
 344         batch->lrz_clear = fd_submit_new_ringbuffer(batch->submit, 0x1000, 0);
 345         ring = batch->lrz_clear;
 346
 347         emit_marker6(ring, 7);
 348         OUT_PKT7(ring, CP_SET_MARKER, 1);
 349         OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
 350         emit_marker6(ring, 7);
 351
 352         OUT_WFI5(ring);
 353
 354         OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
 355         OUT_RING(ring, fd6_ctx->magic.RB_CCU_CNTL_bypass);
 356
 357         OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
 358         OUT_RING(ring, 0x7ffff);
 359
 360         emit_marker6(ring, 7);
 361         OUT_PKT7(ring, CP_SET_MARKER, 1);
 362         OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
 363         emit_marker6(ring, 7);
 364
 365         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1);
 366         OUT_RING(ring, 0x0);
 367
 368         OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 13);
 369         OUT_RING(ring, 0x00000000);
 370         OUT_RING(ring, 0x00000000);
 371         OUT_RING(ring, 0x00000000);
 372         OUT_RING(ring, 0x00000000);
 373         OUT_RING(ring, 0x00000000);
 374         OUT_RING(ring, 0x00000000);
 375         OUT_RING(ring, 0x00000000);
 376         OUT_RING(ring, 0x00000000);
 377         OUT_RING(ring, 0x00000000);
 378         OUT_RING(ring, 0x00000000);
 379         OUT_RING(ring, 0x00000000);
 380         OUT_RING(ring, 0x00000000);
 381         OUT_RING(ring, 0x00000000);
 382
 383         OUT_PKT4(ring, REG_A6XX_SP_2D_SRC_FORMAT, 1);
 384         OUT_RING(ring, 0x0000f410);
 385
 386         OUT_PKT4(ring, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);
 387         OUT_RING(ring, A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(FMT6_16_UNORM) |
 388                         0x4f00080);
 389
 390         OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
 391         OUT_RING(ring, A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(FMT6_16_UNORM) |
 392                         0x4f00080);
 393
 394         fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
 395         fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
 396
 397         OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
 398         OUT_RING(ring, fui(depth));
 399         OUT_RING(ring, 0x00000000);
 400         OUT_RING(ring, 0x00000000);
 401         OUT_RING(ring, 0x00000000);
 402
 403         OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
 404         OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(FMT6_16_UNORM) |
 405                         A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
 406                         A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
 407         OUT_RELOC(ring, zsbuf->lrz, 0, 0, 0);
 408         OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(zsbuf->lrz_pitch * 2));
 409         OUT_RING(ring, 0x00000000);
 410         OUT_RING(ring, 0x00000000);
 411         OUT_RING(ring, 0x00000000);
 412         OUT_RING(ring, 0x00000000);
 413         OUT_RING(ring, 0x00000000);
 414
 415         OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
 416         OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X_X(0));
 417         OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X_X(0));
 418         OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y_Y(0));
 419         OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y_Y(0));
 420
 421         OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
 422         OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(0) |
 423                         A6XX_GRAS_2D_DST_TL_Y(0));
 424         OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(zsbuf->lrz_width - 1) |
 425                         A6XX_GRAS_2D_DST_BR_Y(zsbuf->lrz_height - 1));
 426
 427         fd6_event_write(batch, ring, 0x3f, false);
 428
 429         OUT_WFI5(ring);
 430
 431         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
 432         OUT_RING(ring, fd6_ctx->magic.RB_UNKNOWN_8E04_blit);
 433
 434         OUT_PKT7(ring, CP_BLIT, 1);
 435         OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
 436
 437         OUT_WFI5(ring);
 438
 439         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
 440         OUT_RING(ring, 0x0);               /* RB_UNKNOWN_8E04 */
 441
 442         fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
 443         fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
 444         fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
 445
 446         fd6_cache_inv(batch, ring);
 447 }
 448
 449 static bool is_z32(enum pipe_format format)
 450 {
 451         switch (format) {
 452         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 453         case PIPE_FORMAT_Z32_UNORM:
 454         case PIPE_FORMAT_Z32_FLOAT:
 455                 return true;
 456         default:
 457                 return false;
 458         }
 459 }
 460
 461 static bool
 462 fd6_clear(struct fd_context *ctx, unsigned buffers,
 463                 const union pipe_color_union *color, double depth, unsigned stencil)
 464 {
 465         struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
 466         const bool has_depth = pfb->zsbuf;
 467         unsigned color_buffers = buffers >> 2;
 468
 469         /* If we're clearing after draws, fallback to 3D pipe clears.  We could
 470          * use blitter clears in the draw batch but then we'd have to patch up the
 471          * gmem offsets. This doesn't seem like a useful thing to optimize for
 472          * however.*/
 473         if (ctx->batch->num_draws > 0)
 474                 return false;
 475
 476         foreach_bit(i, color_buffers)
 477                 ctx->batch->clear_color[i] = *color;
 478         if (buffers & PIPE_CLEAR_DEPTH)
 479                 ctx->batch->clear_depth = depth;
 480         if (buffers & PIPE_CLEAR_STENCIL)
 481                 ctx->batch->clear_stencil = stencil;
 482
 483         ctx->batch->fast_cleared |= buffers;
 484
 485         if (has_depth && (buffers & PIPE_CLEAR_DEPTH)) {
 486                 struct fd_resource *zsbuf = fd_resource(pfb->zsbuf->texture);
 487                 if (zsbuf->lrz && !is_z32(pfb->zsbuf->format)) {
 488                         zsbuf->lrz_valid = true;
 489                         zsbuf->lrz_direction = FD_LRZ_UNKNOWN;
 490                         fd6_clear_lrz(ctx->batch, zsbuf, depth);
 491                 }
 492         }
 493
 494         return true;
 495 }
 496
 497 void
 498 fd6_draw_init(struct pipe_context *pctx)
 499 {
 500         struct fd_context *ctx = fd_context(pctx);
 501         ctx->draw_vbo = fd6_draw_vbo;
 502         ctx->clear = fd6_clear;
 503 }