src/gallium/drivers/freedreno/a6xx/fd6_draw.c

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Rob Clark <robclark@freedesktop.org>
  26  */
  27
  28 #include "pipe/p_state.h"
  29 #include "util/u_string.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_prim.h"
  32
  33 #include "freedreno_state.h"
  34 #include "freedreno_resource.h"
  35
  36 #include "fd6_draw.h"
  37 #include "fd6_context.h"
  38 #include "fd6_emit.h"
  39 #include "fd6_program.h"
  40 #include "fd6_format.h"
  41 #include "fd6_zsa.h"
  42
  43 /* some bits in common w/ a4xx: */
  44 #include "a4xx/fd4_draw.h"
  45
  46 static void
  47 draw_emit_indirect(struct fd_batch *batch, struct fd_ringbuffer *ring,
  48                                    enum pc_di_primtype primtype,
  49                                    const struct pipe_draw_info *info,
  50                                    unsigned index_offset)
  51 {
  52         struct fd_resource *ind = fd_resource(info->indirect->buffer);
  53
  54         if (info->index_size) {
  55                 struct pipe_resource *idx = info->index.resource;
  56                 unsigned max_indicies = (idx->width0 - info->indirect->offset) /
  57                         info->index_size;
  58
  59                 OUT_PKT7(ring, CP_DRAW_INDX_INDIRECT, 6);
  60                 OUT_RINGP(ring, DRAW4(primtype, DI_SRC_SEL_DMA,
  61                                                           fd4_size2indextype(info->index_size), 0),
  62                                   &batch->draw_patches);
  63                 OUT_RELOC(ring, fd_resource(idx)->bo,
  64                                   index_offset, 0, 0);
  65                 // XXX: Check A5xx vs A6xx
  66                 OUT_RING(ring, A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies));
  67                 OUT_RELOC(ring, ind->bo, info->indirect->offset, 0, 0);
  68         } else {
  69                 OUT_PKT7(ring, CP_DRAW_INDIRECT, 3);
  70                 OUT_RINGP(ring, DRAW4(primtype, DI_SRC_SEL_AUTO_INDEX, 0, 0),
  71                                   &batch->draw_patches);
  72                 OUT_RELOC(ring, ind->bo, info->indirect->offset, 0, 0);
  73         }
  74 }
  75
  76 static void
  77 draw_emit(struct fd_batch *batch, struct fd_ringbuffer *ring,
  78                   enum pc_di_primtype primtype,
  79                   const struct pipe_draw_info *info,
  80                   unsigned index_offset)
  81 {
  82         if (info->index_size) {
  83                 assert(!info->has_user_indices);
  84
  85                 struct pipe_resource *idx_buffer = info->index.resource;
  86                 uint32_t idx_size = info->index_size * info->count;
  87                 uint32_t idx_offset = index_offset + info->start * info->index_size;
  88
  89                 /* leave vis mode blank for now, it will be patched up when
  90                  * we know if we are binning or not
  91                  */
  92                 uint32_t draw = CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
  93                         CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
  94                         CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(fd4_size2indextype(info->index_size)) |
  95                         0x2000;
  96
  97                 OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, 7);
  98                 OUT_RINGP(ring, draw, &batch->draw_patches);
  99                 OUT_RING(ring, info->instance_count);    /* NumInstances */
 100                 OUT_RING(ring, info->count);             /* NumIndices */
 101                 OUT_RING(ring, 0x0);           /* XXX */
 102                 OUT_RELOC(ring, fd_resource(idx_buffer)->bo, idx_offset, 0, 0);
 103                 OUT_RING (ring, idx_size);
 104         } else {
 105                 /* leave vis mode blank for now, it will be patched up when
 106                  * we know if we are binning or not
 107                  */
 108                 uint32_t draw = CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
 109                         CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
 110                         0x2000;
 111
 112                 OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, 3);
 113                 OUT_RINGP(ring, draw, &batch->draw_patches);
 114                 OUT_RING(ring, info->instance_count);    /* NumInstances */
 115                 OUT_RING(ring, info->count);             /* NumIndices */
 116         }
 117 }
 118
 119 /* fixup dirty shader state in case some "unrelated" (from the state-
 120  * tracker's perspective) state change causes us to switch to a
 121  * different variant.
 122  */
 123 static void
 124 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
 125 {
 126         struct fd6_context *fd6_ctx = fd6_context(ctx);
 127         struct ir3_shader_key *last_key = &fd6_ctx->last_key;
 128
 129         if (!ir3_shader_key_equal(last_key, key)) {
 130                 if (ir3_shader_key_changes_fs(last_key, key)) {
 131                         ctx->dirty_shader[PIPE_SHADER_FRAGMENT] |= FD_DIRTY_SHADER_PROG;
 132                         ctx->dirty |= FD_DIRTY_PROG;
 133                 }
 134
 135                 if (ir3_shader_key_changes_vs(last_key, key)) {
 136                         ctx->dirty_shader[PIPE_SHADER_VERTEX] |= FD_DIRTY_SHADER_PROG;
 137                         ctx->dirty |= FD_DIRTY_PROG;
 138                 }
 139
 140                 fd6_ctx->last_key = *key;
 141         }
 142 }
 143
 144 static bool
 145 fd6_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
 146              unsigned index_offset)
 147 {
 148         struct fd6_context *fd6_ctx = fd6_context(ctx);
 149         struct fd6_emit emit = {
 150                 .ctx = ctx,
 151                 .vtx  = &ctx->vtx,
 152                 .info = info,
 153                 .key = {
 154                         .vs = ctx->prog.vp,
 155                         .fs = ctx->prog.fp,
 156                         .key = {
 157                                 .color_two_side = ctx->rasterizer->light_twoside,
 158                                 .vclamp_color = ctx->rasterizer->clamp_vertex_color,
 159                                 .fclamp_color = ctx->rasterizer->clamp_fragment_color,
 160                                 .rasterflat = ctx->rasterizer->flatshade,
 161                                 .ucp_enables = ctx->rasterizer->clip_plane_enable,
 162                                 .has_per_samp = (fd6_ctx->fsaturate || fd6_ctx->vsaturate ||
 163                                                 fd6_ctx->fastc_srgb || fd6_ctx->vastc_srgb),
 164                                 .vsaturate_s = fd6_ctx->vsaturate_s,
 165                                 .vsaturate_t = fd6_ctx->vsaturate_t,
 166                                 .vsaturate_r = fd6_ctx->vsaturate_r,
 167                                 .fsaturate_s = fd6_ctx->fsaturate_s,
 168                                 .fsaturate_t = fd6_ctx->fsaturate_t,
 169                                 .fsaturate_r = fd6_ctx->fsaturate_r,
 170                                 .vastc_srgb = fd6_ctx->vastc_srgb,
 171                                 .fastc_srgb = fd6_ctx->fastc_srgb,
 172                                 .vsamples = ctx->tex[PIPE_SHADER_VERTEX].samples,
 173                                 .fsamples = ctx->tex[PIPE_SHADER_FRAGMENT].samples,
 174                         }
 175                 },
 176                 .rasterflat = ctx->rasterizer->flatshade,
 177                 .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
 178                 .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
 179         };
 180
 181         fixup_shader_state(ctx, &emit.key.key);
 182
 183         if (!(ctx->dirty & FD_DIRTY_PROG)) {
 184                 emit.prog = fd6_ctx->prog;
 185         } else {
 186                 fd6_ctx->prog = fd6_emit_get_prog(&emit);
 187         }
 188
 189         emit.dirty = ctx->dirty;      /* *after* fixup_shader_state() */
 190         emit.bs = fd6_emit_get_prog(&emit)->bs;
 191         emit.vs = fd6_emit_get_prog(&emit)->vs;
 192         emit.fs = fd6_emit_get_prog(&emit)->fs;
 193
 194         const struct ir3_shader_variant *vp = emit.vs;
 195         const struct ir3_shader_variant *fp = emit.fs;
 196
 197         /* do regular pass first, since that is more likely to fail compiling: */
 198
 199         if (!vp || !fp)
 200                 return false;
 201
 202         ctx->stats.vs_regs += ir3_shader_halfregs(vp);
 203         ctx->stats.fs_regs += ir3_shader_halfregs(fp);
 204
 205         /* figure out whether we need to disable LRZ write for binning
 206          * pass using draw pass's fp:
 207          */
 208         emit.no_lrz_write = fp->writes_pos || fp->has_kill;
 209
 210         struct fd_ringbuffer *ring = ctx->batch->draw;
 211         enum pc_di_primtype primtype = ctx->primtypes[info->mode];
 212
 213         fd6_emit_state(ring, &emit);
 214
 215         OUT_PKT4(ring, REG_A6XX_VFD_INDEX_OFFSET, 2);
 216         OUT_RING(ring, info->index_size ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
 217         OUT_RING(ring, info->start_instance);   /* VFD_INSTANCE_START_OFFSET */
 218
 219         OUT_PKT4(ring, REG_A6XX_PC_RESTART_INDEX, 1);
 220         OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
 221                         info->restart_index : 0xffffffff);
 222
 223         /* for debug after a lock up, write a unique counter value
 224          * to scratch7 for each draw, to make it easier to match up
 225          * register dumps to cmdstream.  The combination of IB
 226          * (scratch6) and DRAW is enough to "triangulate" the
 227          * particular draw that caused lockup.
 228          */
 229         emit_marker6(ring, 7);
 230
 231         if (info->indirect) {
 232                 draw_emit_indirect(ctx->batch, ring, primtype,
 233                                                    info, index_offset);
 234         } else {
 235                 draw_emit(ctx->batch, ring, primtype,
 236                                   info, index_offset);
 237         }
 238
 239         emit_marker6(ring, 7);
 240         fd_reset_wfi(ctx->batch);
 241
 242         if (emit.streamout_mask) {
 243                 struct fd_ringbuffer *ring = ctx->batch->draw;
 244
 245                 for (unsigned i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
 246                         if (emit.streamout_mask & (1 << i)) {
 247                                 fd6_event_write(ctx->batch, ring, FLUSH_SO_0 + i, false);
 248                         }
 249                 }
 250         }
 251
 252         fd_context_all_clean(ctx);
 253
 254         return true;
 255 }
 256
 257 static void
 258 fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
 259 {
 260         struct fd_ringbuffer *ring;
 261
 262         // TODO mid-frame clears (ie. app doing crazy stuff)??  Maybe worth
 263         // splitting both clear and lrz clear out into their own rb's.  And
 264         // just throw away any draws prior to clear.  (Anything not fullscreen
 265         // clear, just fallback to generic path that treats it as a normal
 266         // draw
 267
 268         if (!batch->lrz_clear) {
 269                 batch->lrz_clear = fd_submit_new_ringbuffer(batch->submit, 0x1000, 0);
 270         }
 271
 272         ring = batch->lrz_clear;
 273
 274         emit_marker6(ring, 7);
 275         OUT_PKT7(ring, CP_SET_MARKER, 1);
 276         OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
 277         emit_marker6(ring, 7);
 278
 279         OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
 280         OUT_RING(ring, 0x10000000);
 281
 282         OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
 283         OUT_RING(ring, 0x7ffff);
 284
 285         emit_marker6(ring, 7);
 286         OUT_PKT7(ring, CP_SET_MARKER, 1);
 287         OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(0xc));
 288         emit_marker6(ring, 7);
 289
 290         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1);
 291         OUT_RING(ring, 0x0);
 292
 293         OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 13);
 294         OUT_RING(ring, 0x00000000);
 295         OUT_RING(ring, 0x00000000);
 296         OUT_RING(ring, 0x00000000);
 297         OUT_RING(ring, 0x00000000);
 298         OUT_RING(ring, 0x00000000);
 299         OUT_RING(ring, 0x00000000);
 300         OUT_RING(ring, 0x00000000);
 301         OUT_RING(ring, 0x00000000);
 302         OUT_RING(ring, 0x00000000);
 303         OUT_RING(ring, 0x00000000);
 304         OUT_RING(ring, 0x00000000);
 305         OUT_RING(ring, 0x00000000);
 306         OUT_RING(ring, 0x00000000);
 307
 308         OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_ACC0, 1);
 309         OUT_RING(ring, 0x0000f410);
 310
 311         OUT_PKT4(ring, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);
 312         OUT_RING(ring, A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(RB6_R16_UNORM) |
 313                         0x4f00080);
 314
 315         OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
 316         OUT_RING(ring, A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(RB6_R16_UNORM) |
 317                         0x4f00080);
 318
 319         fd6_event_write(batch, ring, UNK_1D, true);
 320         fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
 321
 322         OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
 323         OUT_RING(ring, fui(depth));
 324         OUT_RING(ring, 0x00000000);
 325         OUT_RING(ring, 0x00000000);
 326         OUT_RING(ring, 0x00000000);
 327
 328         OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
 329         OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(RB6_R16_UNORM) |
 330                         A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
 331                         A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
 332         OUT_RELOCW(ring, zsbuf->lrz, 0, 0, 0);
 333         OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(zsbuf->lrz_pitch * 2));
 334         OUT_RING(ring, 0x00000000);
 335         OUT_RING(ring, 0x00000000);
 336         OUT_RING(ring, 0x00000000);
 337         OUT_RING(ring, 0x00000000);
 338         OUT_RING(ring, 0x00000000);
 339
 340         OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
 341         OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X_X(0));
 342         OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X_X(0));
 343         OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y_Y(0));
 344         OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y_Y(0));
 345
 346         OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
 347         OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(0) |
 348                         A6XX_GRAS_2D_DST_TL_Y(0));
 349         OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(zsbuf->lrz_width - 1) |
 350                         A6XX_GRAS_2D_DST_BR_Y(zsbuf->lrz_height - 1));
 351
 352         fd6_event_write(batch, ring, 0x3f, false);
 353
 354         OUT_WFI5(ring);
 355
 356         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
 357         OUT_RING(ring, 0x1000000);
 358
 359         OUT_PKT7(ring, CP_BLIT, 1);
 360         OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
 361
 362         OUT_WFI5(ring);
 363
 364         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
 365         OUT_RING(ring, 0x0);
 366
 367         fd6_event_write(batch, ring, UNK_1D, true);
 368         fd6_event_write(batch, ring, FACENESS_FLUSH, true);
 369         fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
 370
 371         fd6_cache_flush(batch, ring);
 372 }
 373
 374 static bool is_z32(enum pipe_format format)
 375 {
 376         switch (format) {
 377         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 378         case PIPE_FORMAT_Z32_UNORM:
 379         case PIPE_FORMAT_Z32_FLOAT:
 380                 return true;
 381         default:
 382                 return false;
 383         }
 384 }
 385
 386 static bool
 387 fd6_clear(struct fd_context *ctx, unsigned buffers,
 388                 const union pipe_color_union *color, double depth, unsigned stencil)
 389 {
 390         struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
 391         const bool has_depth = pfb->zsbuf;
 392         unsigned color_buffers = buffers >> 2;
 393         unsigned i;
 394
 395         /* If we're clearing after draws, fallback to 3D pipe clears.  We could
 396          * use blitter clears in the draw batch but then we'd have to patch up the
 397          * gmem offsets. This doesn't seem like a useful thing to optimize for
 398          * however.*/
 399         if (ctx->batch->num_draws > 0)
 400                 return false;
 401
 402         foreach_bit(i, color_buffers)
 403                 ctx->batch->clear_color[i] = *color;
 404         if (buffers & PIPE_CLEAR_DEPTH)
 405                 ctx->batch->clear_depth = depth;
 406         if (buffers & PIPE_CLEAR_STENCIL)
 407                 ctx->batch->clear_stencil = stencil;
 408
 409         ctx->batch->fast_cleared |= buffers;
 410
 411         if (has_depth && (buffers & PIPE_CLEAR_DEPTH)) {
 412                 struct fd_resource *zsbuf = fd_resource(pfb->zsbuf->texture);
 413                 if (zsbuf->lrz && !is_z32(pfb->zsbuf->format)) {
 414                         zsbuf->lrz_valid = true;
 415                         fd6_clear_lrz(ctx->batch, zsbuf, depth);
 416                 }
 417         }
 418
 419         return true;
 420 }
 421
 422 void
 423 fd6_draw_init(struct pipe_context *pctx)
 424 {
 425         struct fd_context *ctx = fd_context(pctx);
 426         ctx->draw_vbo = fd6_draw_vbo;
 427         ctx->clear = fd6_clear;
 428 }