2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Rob Clark <robclark@freedesktop.org>
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_prim.h"
33 #include "freedreno_state.h"
34 #include "freedreno_resource.h"
37 #include "fd6_context.h"
39 #include "fd6_program.h"
40 #include "fd6_format.h"
43 /* some bits in common w/ a4xx: */
44 #include "a4xx/fd4_draw.h"
47 draw_emit_indirect(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
,
48 enum pc_di_primtype primtype
,
49 enum pc_di_vis_cull_mode vismode
,
50 const struct pipe_draw_info
*info
,
51 unsigned index_offset
)
53 struct fd_resource
*ind
= fd_resource(info
->indirect
->buffer
);
55 if (info
->index_size
) {
56 struct pipe_resource
*idx
= info
->index
.resource
;
57 unsigned max_indicies
= (idx
->width0
- info
->indirect
->offset
) /
60 OUT_PKT7(ring
, CP_DRAW_INDX_INDIRECT
, 6);
61 OUT_RINGP(ring
, DRAW4(primtype
, DI_SRC_SEL_DMA
,
62 fd4_size2indextype(info
->index_size
), 0),
63 &batch
->draw_patches
);
64 OUT_RELOC(ring
, fd_resource(idx
)->bo
,
66 // XXX: Check A5xx vs A6xx
67 OUT_RING(ring
, A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies
));
68 OUT_RELOC(ring
, ind
->bo
, info
->indirect
->offset
, 0, 0);
70 OUT_PKT7(ring
, CP_DRAW_INDIRECT
, 3);
71 OUT_RINGP(ring
, DRAW4(primtype
, DI_SRC_SEL_AUTO_INDEX
, 0, 0),
72 &batch
->draw_patches
);
73 OUT_RELOC(ring
, ind
->bo
, info
->indirect
->offset
, 0, 0);
78 draw_emit(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
,
79 enum pc_di_primtype primtype
,
80 enum pc_di_vis_cull_mode vismode
,
81 const struct pipe_draw_info
*info
,
82 unsigned index_offset
)
84 if (info
->index_size
) {
85 assert(!info
->has_user_indices
);
87 struct pipe_resource
*idx_buffer
= info
->index
.resource
;
88 uint32_t idx_size
= info
->index_size
* info
->count
;
89 uint32_t idx_offset
= index_offset
+ info
->start
* info
->index_size
;
91 /* leave vis mode blank for now, it will be patched up when
92 * we know if we are binning or not
94 uint32_t draw
= CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
95 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA
) |
96 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(fd4_size2indextype(info
->index_size
)) |
99 OUT_PKT7(ring
, CP_DRAW_INDX_OFFSET
, 7);
100 if (vismode
== USE_VISIBILITY
) {
101 OUT_RINGP(ring
, draw
, &batch
->draw_patches
);
103 OUT_RING(ring
, draw
);
105 OUT_RING(ring
, info
->instance_count
); /* NumInstances */
106 OUT_RING(ring
, info
->count
); /* NumIndices */
107 OUT_RING(ring
, 0x0); /* XXX */
108 OUT_RELOC(ring
, fd_resource(idx_buffer
)->bo
, idx_offset
, 0, 0);
109 OUT_RING (ring
, idx_size
);
111 /* leave vis mode blank for now, it will be patched up when
112 * we know if we are binning or not
114 uint32_t draw
= CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
115 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX
) |
118 OUT_PKT7(ring
, CP_DRAW_INDX_OFFSET
, 3);
119 if (vismode
== USE_VISIBILITY
) {
120 OUT_RINGP(ring
, draw
, &batch
->draw_patches
);
122 OUT_RING(ring
, draw
);
124 OUT_RING(ring
, info
->instance_count
); /* NumInstances */
125 OUT_RING(ring
, info
->count
); /* NumIndices */
130 draw_impl(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
131 struct fd6_emit
*emit
, unsigned index_offset
)
133 const struct pipe_draw_info
*info
= emit
->info
;
134 enum pc_di_primtype primtype
= ctx
->primtypes
[info
->mode
];
136 fd6_emit_state(ctx
, ring
, emit
);
138 if (emit
->dirty
& (FD_DIRTY_VTXBUF
| FD_DIRTY_VTXSTATE
))
139 fd6_emit_vertex_bufs(ring
, emit
);
141 OUT_PKT4(ring
, REG_A6XX_VFD_INDEX_OFFSET
, 2);
142 OUT_RING(ring
, info
->index_size
? info
->index_bias
: info
->start
); /* VFD_INDEX_OFFSET */
143 OUT_RING(ring
, info
->start_instance
); /* VFD_INSTANCE_START_OFFSET */
145 OUT_PKT4(ring
, REG_A6XX_PC_RESTART_INDEX
, 1);
146 OUT_RING(ring
, info
->primitive_restart
? /* PC_RESTART_INDEX */
147 info
->restart_index
: 0xffffffff);
149 /* for debug after a lock up, write a unique counter value
150 * to scratch7 for each draw, to make it easier to match up
151 * register dumps to cmdstream. The combination of IB
152 * (scratch6) and DRAW is enough to "triangulate" the
153 * particular draw that caused lockup.
155 emit_marker6(ring
, 7);
157 if (info
->indirect
) {
158 draw_emit_indirect(ctx
->batch
, ring
, primtype
,
159 emit
->binning_pass
? IGNORE_VISIBILITY
: USE_VISIBILITY
,
162 draw_emit(ctx
->batch
, ring
, primtype
,
163 emit
->binning_pass
? IGNORE_VISIBILITY
: USE_VISIBILITY
,
167 emit_marker6(ring
, 7);
168 fd_reset_wfi(ctx
->batch
);
171 /* fixup dirty shader state in case some "unrelated" (from the state-
172 * tracker's perspective) state change causes us to switch to a
176 fixup_shader_state(struct fd_context
*ctx
, struct ir3_shader_key
*key
)
178 struct fd6_context
*fd6_ctx
= fd6_context(ctx
);
179 struct ir3_shader_key
*last_key
= &fd6_ctx
->last_key
;
181 if (!ir3_shader_key_equal(last_key
, key
)) {
182 if (ir3_shader_key_changes_fs(last_key
, key
)) {
183 ctx
->dirty_shader
[PIPE_SHADER_FRAGMENT
] |= FD_DIRTY_SHADER_PROG
;
184 ctx
->dirty
|= FD_DIRTY_PROG
;
187 if (ir3_shader_key_changes_vs(last_key
, key
)) {
188 ctx
->dirty_shader
[PIPE_SHADER_VERTEX
] |= FD_DIRTY_SHADER_PROG
;
189 ctx
->dirty
|= FD_DIRTY_PROG
;
192 fd6_ctx
->last_key
= *key
;
197 fd6_draw_vbo(struct fd_context
*ctx
, const struct pipe_draw_info
*info
,
198 unsigned index_offset
)
200 struct fd6_context
*fd6_ctx
= fd6_context(ctx
);
201 struct fd6_emit emit
= {
202 .debug
= &ctx
->debug
,
207 .color_two_side
= ctx
->rasterizer
->light_twoside
,
208 .vclamp_color
= ctx
->rasterizer
->clamp_vertex_color
,
209 .fclamp_color
= ctx
->rasterizer
->clamp_fragment_color
,
210 .rasterflat
= ctx
->rasterizer
->flatshade
,
211 .half_precision
= ctx
->in_blit
&&
212 fd_half_precision(&ctx
->batch
->framebuffer
),
213 .ucp_enables
= ctx
->rasterizer
->clip_plane_enable
,
214 .has_per_samp
= (fd6_ctx
->fsaturate
|| fd6_ctx
->vsaturate
||
215 fd6_ctx
->fastc_srgb
|| fd6_ctx
->vastc_srgb
),
216 .vsaturate_s
= fd6_ctx
->vsaturate_s
,
217 .vsaturate_t
= fd6_ctx
->vsaturate_t
,
218 .vsaturate_r
= fd6_ctx
->vsaturate_r
,
219 .fsaturate_s
= fd6_ctx
->fsaturate_s
,
220 .fsaturate_t
= fd6_ctx
->fsaturate_t
,
221 .fsaturate_r
= fd6_ctx
->fsaturate_r
,
222 .vastc_srgb
= fd6_ctx
->vastc_srgb
,
223 .fastc_srgb
= fd6_ctx
->fastc_srgb
,
224 .vsamples
= ctx
->tex
[PIPE_SHADER_VERTEX
].samples
,
225 .fsamples
= ctx
->tex
[PIPE_SHADER_FRAGMENT
].samples
,
227 .rasterflat
= ctx
->rasterizer
->flatshade
,
228 .sprite_coord_enable
= ctx
->rasterizer
->sprite_coord_enable
,
229 .sprite_coord_mode
= ctx
->rasterizer
->sprite_coord_mode
,
232 fixup_shader_state(ctx
, &emit
.key
);
234 unsigned dirty
= ctx
->dirty
;
235 const struct ir3_shader_variant
*vp
= fd6_emit_get_vp(&emit
);
236 const struct ir3_shader_variant
*fp
= fd6_emit_get_fp(&emit
);
238 /* do regular pass first, since that is more likely to fail compiling: */
243 ctx
->stats
.vs_regs
+= ir3_shader_halfregs(vp
);
244 ctx
->stats
.fs_regs
+= ir3_shader_halfregs(fp
);
246 /* figure out whether we need to disable LRZ write for binning
247 * pass using draw pass's fp:
249 emit
.no_lrz_write
= fp
->writes_pos
|| fp
->has_kill
;
251 emit
.binning_pass
= false;
254 draw_impl(ctx
, ctx
->batch
->draw
, &emit
, index_offset
);
256 /* and now binning pass: */
257 emit
.binning_pass
= true;
258 emit
.dirty
= dirty
& ~(FD_DIRTY_BLEND
);
259 emit
.vp
= NULL
; /* we changed key so need to refetch vp */
261 draw_impl(ctx
, ctx
->batch
->binning
, &emit
, index_offset
);
263 if (emit
.streamout_mask
) {
264 struct fd_ringbuffer
*ring
= ctx
->batch
->draw
;
266 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
267 if (emit
.streamout_mask
& (1 << i
)) {
268 fd6_event_write(ctx
->batch
, ring
, FLUSH_SO_0
+ i
, false);
273 fd_context_all_clean(ctx
);
278 static bool is_z32(enum pipe_format format
)
281 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
282 case PIPE_FORMAT_Z32_UNORM
:
283 case PIPE_FORMAT_Z32_FLOAT
:
291 fd6_clear_lrz(struct fd_batch
*batch
, struct fd_resource
*zsbuf
, double depth
)
293 struct fd_ringbuffer
*ring
;
295 // TODO mid-frame clears (ie. app doing crazy stuff)?? Maybe worth
296 // splitting both clear and lrz clear out into their own rb's. And
297 // just throw away any draws prior to clear. (Anything not fullscreen
298 // clear, just fallback to generic path that treats it as a normal
301 if (!batch
->lrz_clear
) {
302 batch
->lrz_clear
= fd_ringbuffer_new(batch
->ctx
->pipe
, 0x1000);
303 fd_ringbuffer_set_parent(batch
->lrz_clear
, batch
->gmem
);
306 ring
= batch
->lrz_clear
;
308 emit_marker6(ring
, 7);
309 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
310 OUT_RING(ring
, A2XX_CP_SET_MARKER_0_MODE(RM6_BYPASS
));
311 emit_marker6(ring
, 7);
313 OUT_PKT4(ring
, REG_A6XX_RB_CCU_CNTL
, 1);
314 OUT_RING(ring
, 0x10000000);
316 OUT_PKT4(ring
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
317 OUT_RING(ring
, 0x7ffff);
319 emit_marker6(ring
, 7);
320 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
321 OUT_RING(ring
, A2XX_CP_SET_MARKER_0_MODE(0xc));
322 emit_marker6(ring
, 7);
324 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_8C01
, 1);
327 OUT_PKT4(ring
, REG_A6XX_SP_PS_2D_SRC_INFO
, 13);
328 OUT_RING(ring
, 0x00000000);
329 OUT_RING(ring
, 0x00000000);
330 OUT_RING(ring
, 0x00000000);
331 OUT_RING(ring
, 0x00000000);
332 OUT_RING(ring
, 0x00000000);
333 OUT_RING(ring
, 0x00000000);
334 OUT_RING(ring
, 0x00000000);
335 OUT_RING(ring
, 0x00000000);
336 OUT_RING(ring
, 0x00000000);
337 OUT_RING(ring
, 0x00000000);
338 OUT_RING(ring
, 0x00000000);
339 OUT_RING(ring
, 0x00000000);
340 OUT_RING(ring
, 0x00000000);
342 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_ACC0
, 1);
343 OUT_RING(ring
, 0x0000f410);
345 OUT_PKT4(ring
, REG_A6XX_GRAS_2D_BLIT_CNTL
, 1);
346 OUT_RING(ring
, A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(RB6_R16_UNORM
) |
349 OUT_PKT4(ring
, REG_A6XX_RB_2D_BLIT_CNTL
, 1);
350 OUT_RING(ring
, A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(RB6_R16_UNORM
) |
353 fd6_event_write(batch
, ring
, UNK_1D
, true);
354 fd6_event_write(batch
, ring
, PC_CCU_INVALIDATE_COLOR
, false);
356 OUT_PKT4(ring
, REG_A6XX_RB_2D_SRC_SOLID_C0
, 4);
357 OUT_RING(ring
, fui(depth
));
358 OUT_RING(ring
, 0x00000000);
359 OUT_RING(ring
, 0x00000000);
360 OUT_RING(ring
, 0x00000000);
362 OUT_PKT4(ring
, REG_A6XX_RB_2D_DST_INFO
, 9);
363 OUT_RING(ring
, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(RB6_R16_UNORM
) |
364 A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR
) |
365 A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX
));
366 OUT_RELOCW(ring
, zsbuf
->lrz
, 0, 0, 0);
367 OUT_RING(ring
, A6XX_RB_2D_DST_SIZE_PITCH(zsbuf
->lrz_pitch
* 2));
368 OUT_RING(ring
, 0x00000000);
369 OUT_RING(ring
, 0x00000000);
370 OUT_RING(ring
, 0x00000000);
371 OUT_RING(ring
, 0x00000000);
372 OUT_RING(ring
, 0x00000000);
374 OUT_PKT4(ring
, REG_A6XX_GRAS_2D_SRC_TL_X
, 4);
375 OUT_RING(ring
, A6XX_GRAS_2D_SRC_TL_X_X(0));
376 OUT_RING(ring
, A6XX_GRAS_2D_SRC_BR_X_X(0));
377 OUT_RING(ring
, A6XX_GRAS_2D_SRC_TL_Y_Y(0));
378 OUT_RING(ring
, A6XX_GRAS_2D_SRC_BR_Y_Y(0));
380 OUT_PKT4(ring
, REG_A6XX_GRAS_2D_DST_TL
, 2);
381 OUT_RING(ring
, A6XX_GRAS_2D_DST_TL_X(0) |
382 A6XX_GRAS_2D_DST_TL_Y(0));
383 OUT_RING(ring
, A6XX_GRAS_2D_DST_BR_X(zsbuf
->lrz_width
- 1) |
384 A6XX_GRAS_2D_DST_BR_Y(zsbuf
->lrz_height
- 1));
386 fd6_event_write(batch
, ring
, 0x3f, false);
390 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_8E04
, 1);
391 OUT_RING(ring
, 0x1000000);
393 OUT_PKT7(ring
, CP_BLIT
, 1);
394 OUT_RING(ring
, CP_BLIT_0_OP(BLIT_OP_SCALE
));
398 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_8E04
, 1);
401 fd6_event_write(batch
, ring
, UNK_1D
, true);
402 fd6_event_write(batch
, ring
, FACENESS_FLUSH
, true);
403 fd6_event_write(batch
, ring
, CACHE_FLUSH_TS
, true);
405 fd6_cache_flush(batch
, ring
);
409 fd6_clear(struct fd_context
*ctx
, unsigned buffers
,
410 const union pipe_color_union
*color
, double depth
, unsigned stencil
)
412 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
413 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
414 struct fd_ringbuffer
*ring
= ctx
->batch
->draw
;
416 if ((buffers
& (PIPE_CLEAR_DEPTH
| PIPE_CLEAR_STENCIL
)) &&
417 is_z32(pfb
->zsbuf
->format
))
420 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_SCISSOR_TL
, 2);
421 OUT_RING(ring
, A6XX_RB_BLIT_SCISSOR_TL_X(scissor
->minx
) |
422 A6XX_RB_BLIT_SCISSOR_TL_Y(scissor
->miny
));
423 OUT_RING(ring
, A6XX_RB_BLIT_SCISSOR_BR_X(scissor
->maxx
- 1) |
424 A6XX_RB_BLIT_SCISSOR_BR_Y(scissor
->maxy
- 1));
426 if (buffers
& PIPE_CLEAR_COLOR
) {
427 for (int i
= 0; i
< pfb
->nr_cbufs
; i
++) {
428 union util_color uc
= {0};
433 if (!(buffers
& (PIPE_CLEAR_COLOR0
<< i
)))
436 enum pipe_format pfmt
= pfb
->cbufs
[i
]->format
;
438 // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
439 union pipe_color_union swapped
;
440 switch (fd6_pipe2swap(pfmt
)) {
442 swapped
.ui
[0] = color
->ui
[0];
443 swapped
.ui
[1] = color
->ui
[1];
444 swapped
.ui
[2] = color
->ui
[2];
445 swapped
.ui
[3] = color
->ui
[3];
448 swapped
.ui
[2] = color
->ui
[0];
449 swapped
.ui
[1] = color
->ui
[1];
450 swapped
.ui
[0] = color
->ui
[2];
451 swapped
.ui
[3] = color
->ui
[3];
454 swapped
.ui
[3] = color
->ui
[0];
455 swapped
.ui
[0] = color
->ui
[1];
456 swapped
.ui
[1] = color
->ui
[2];
457 swapped
.ui
[2] = color
->ui
[3];
460 swapped
.ui
[3] = color
->ui
[0];
461 swapped
.ui
[2] = color
->ui
[1];
462 swapped
.ui
[1] = color
->ui
[2];
463 swapped
.ui
[0] = color
->ui
[3];
467 if (util_format_is_pure_uint(pfmt
)) {
468 util_format_write_4ui(pfmt
, swapped
.ui
, 0, &uc
, 0, 0, 0, 1, 1);
469 } else if (util_format_is_pure_sint(pfmt
)) {
470 util_format_write_4i(pfmt
, swapped
.i
, 0, &uc
, 0, 0, 0, 1, 1);
472 util_pack_color(swapped
.f
, pfmt
, &uc
);
475 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_DST_INFO
, 1);
476 OUT_RING(ring
, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR
) |
477 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt
)));
479 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_INFO
, 1);
480 OUT_RING(ring
, A6XX_RB_BLIT_INFO_GMEM
|
481 A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
483 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_BASE_GMEM
, 1);
484 OUT_RINGP(ring
, i
, &ctx
->batch
->gmem_patches
);
486 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_88D0
, 1);
489 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0
, 4);
490 OUT_RING(ring
, uc
.ui
[0]);
491 OUT_RING(ring
, uc
.ui
[1]);
492 OUT_RING(ring
, uc
.ui
[2]);
493 OUT_RING(ring
, uc
.ui
[3]);
495 fd6_emit_blit(ctx
->batch
, ring
);
499 if (pfb
->zsbuf
&& (buffers
& (PIPE_CLEAR_DEPTH
| PIPE_CLEAR_STENCIL
))) {
500 enum pipe_format pfmt
= pfb
->zsbuf
->format
;
501 uint32_t clear
= util_pack_z_stencil(pfmt
, depth
, stencil
);
504 if (buffers
& PIPE_CLEAR_DEPTH
)
507 if (buffers
& PIPE_CLEAR_STENCIL
)
510 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_DST_INFO
, 1);
511 OUT_RING(ring
, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR
) |
512 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt
)));
514 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_INFO
, 1);
515 OUT_RING(ring
, A6XX_RB_BLIT_INFO_GMEM
|
516 // XXX UNK0 for separate stencil ??
517 A6XX_RB_BLIT_INFO_DEPTH
|
518 A6XX_RB_BLIT_INFO_CLEAR_MASK(mask
));
520 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_BASE_GMEM
, 1);
521 OUT_RINGP(ring
, MAX_RENDER_TARGETS
, &ctx
->batch
->gmem_patches
);
523 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_88D0
, 1);
526 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0
, 1);
527 OUT_RING(ring
, clear
);
529 fd6_emit_blit(ctx
->batch
, ring
);
531 if (pfb
->zsbuf
&& (buffers
& PIPE_CLEAR_DEPTH
)) {
532 struct fd_resource
*zsbuf
= fd_resource(pfb
->zsbuf
->texture
);
534 zsbuf
->lrz_valid
= true;
535 fd6_clear_lrz(ctx
->batch
, zsbuf
, depth
);
544 fd6_draw_init(struct pipe_context
*pctx
)
546 struct fd_context
*ctx
= fd_context(pctx
);
547 ctx
->draw_vbo
= fd6_draw_vbo
;
548 ctx
->clear
= fd6_clear
;