src/gallium/drivers/freedreno/a6xx/fd6_draw.c

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Rob Clark <robclark@freedesktop.org>
  26  */
  27
  28 #include "pipe/p_state.h"
  29 #include "util/u_string.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_prim.h"
  32
  33 #include "freedreno_state.h"
  34 #include "freedreno_resource.h"
  35
  36 #include "fd6_draw.h"
  37 #include "fd6_context.h"
  38 #include "fd6_emit.h"
  39 #include "fd6_program.h"
  40 #include "fd6_format.h"
  41 #include "fd6_zsa.h"
  42
  43 /* some bits in common w/ a4xx: */
  44 #include "a4xx/fd4_draw.h"
  45
  46 static void
  47 draw_emit_indirect(struct fd_batch *batch, struct fd_ringbuffer *ring,
  48                                    enum pc_di_primtype primtype,
  49                                    const struct pipe_draw_info *info,
  50                                    unsigned index_offset)
  51 {
  52         struct fd_resource *ind = fd_resource(info->indirect->buffer);
  53
  54         if (info->index_size) {
  55                 struct pipe_resource *idx = info->index.resource;
  56                 unsigned max_indicies = (idx->width0 - info->indirect->offset) /
  57                         info->index_size;
  58
  59                 OUT_PKT7(ring, CP_DRAW_INDX_INDIRECT, 6);
  60                 OUT_RINGP(ring, DRAW4(primtype, DI_SRC_SEL_DMA,
  61                                                           fd4_size2indextype(info->index_size), 0),
  62                                   &batch->draw_patches);
  63                 OUT_RELOC(ring, fd_resource(idx)->bo,
  64                                   index_offset, 0, 0);
  65                 // XXX: Check A5xx vs A6xx
  66                 OUT_RING(ring, A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies));
  67                 OUT_RELOC(ring, ind->bo, info->indirect->offset, 0, 0);
  68         } else {
  69                 OUT_PKT7(ring, CP_DRAW_INDIRECT, 3);
  70                 OUT_RINGP(ring, DRAW4(primtype, DI_SRC_SEL_AUTO_INDEX, 0, 0),
  71                                   &batch->draw_patches);
  72                 OUT_RELOC(ring, ind->bo, info->indirect->offset, 0, 0);
  73         }
  74 }
  75
  76 static void
  77 draw_emit(struct fd_batch *batch, struct fd_ringbuffer *ring,
  78                   enum pc_di_primtype primtype,
  79                   const struct pipe_draw_info *info,
  80                   unsigned index_offset)
  81 {
  82         if (info->index_size) {
  83                 assert(!info->has_user_indices);
  84
  85                 struct pipe_resource *idx_buffer = info->index.resource;
  86                 uint32_t idx_size = info->index_size * info->count;
  87                 uint32_t idx_offset = index_offset + info->start * info->index_size;
  88
  89                 /* leave vis mode blank for now, it will be patched up when
  90                  * we know if we are binning or not
  91                  */
  92                 uint32_t draw = CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
  93                         CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
  94                         CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(fd4_size2indextype(info->index_size)) |
  95                         0x2000;
  96
  97                 OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, 7);
  98                 OUT_RINGP(ring, draw, &batch->draw_patches);
  99                 OUT_RING(ring, info->instance_count);    /* NumInstances */
 100                 OUT_RING(ring, info->count);             /* NumIndices */
 101                 OUT_RING(ring, 0x0);           /* XXX */
 102                 OUT_RELOC(ring, fd_resource(idx_buffer)->bo, idx_offset, 0, 0);
 103                 OUT_RING (ring, idx_size);
 104         } else {
 105                 /* leave vis mode blank for now, it will be patched up when
 106                  * we know if we are binning or not
 107                  */
 108                 uint32_t draw = CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
 109                         CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
 110                         0x2000;
 111
 112                 OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, 3);
 113                 OUT_RINGP(ring, draw, &batch->draw_patches);
 114                 OUT_RING(ring, info->instance_count);    /* NumInstances */
 115                 OUT_RING(ring, info->count);             /* NumIndices */
 116         }
 117 }
 118
 119 static void
 120 draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
 121                 struct fd6_emit *emit, unsigned index_offset)
 122 {
 123         const struct pipe_draw_info *info = emit->info;
 124         enum pc_di_primtype primtype = ctx->primtypes[info->mode];
 125
 126         if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE)) {
 127                 struct fd_ringbuffer *state;
 128
 129                 state = fd6_build_vbo_state(emit, emit->vs);
 130                 fd6_emit_add_group(emit, state, FD6_GROUP_VBO, 0x6);
 131                 fd_ringbuffer_del(state);
 132
 133                 state = fd6_build_vbo_state(emit, emit->bs);
 134                 fd6_emit_add_group(emit, state, FD6_GROUP_VBO_BINNING, 0x1);
 135                 fd_ringbuffer_del(state);
 136         }
 137
 138         fd6_emit_state(ring, emit);
 139
 140         OUT_PKT4(ring, REG_A6XX_VFD_INDEX_OFFSET, 2);
 141         OUT_RING(ring, info->index_size ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
 142         OUT_RING(ring, info->start_instance);   /* VFD_INSTANCE_START_OFFSET */
 143
 144         OUT_PKT4(ring, REG_A6XX_PC_RESTART_INDEX, 1);
 145         OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
 146                         info->restart_index : 0xffffffff);
 147
 148         /* for debug after a lock up, write a unique counter value
 149          * to scratch7 for each draw, to make it easier to match up
 150          * register dumps to cmdstream.  The combination of IB
 151          * (scratch6) and DRAW is enough to "triangulate" the
 152          * particular draw that caused lockup.
 153          */
 154         emit_marker6(ring, 7);
 155
 156         if (info->indirect) {
 157                 draw_emit_indirect(ctx->batch, ring, primtype,
 158                                                    info, index_offset);
 159         } else {
 160                 draw_emit(ctx->batch, ring, primtype,
 161                                   info, index_offset);
 162         }
 163
 164         emit_marker6(ring, 7);
 165         fd_reset_wfi(ctx->batch);
 166 }
 167
 168 /* fixup dirty shader state in case some "unrelated" (from the state-
 169  * tracker's perspective) state change causes us to switch to a
 170  * different variant.
 171  */
 172 static void
 173 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
 174 {
 175         struct fd6_context *fd6_ctx = fd6_context(ctx);
 176         struct ir3_shader_key *last_key = &fd6_ctx->last_key;
 177
 178         if (!ir3_shader_key_equal(last_key, key)) {
 179                 if (ir3_shader_key_changes_fs(last_key, key)) {
 180                         ctx->dirty_shader[PIPE_SHADER_FRAGMENT] |= FD_DIRTY_SHADER_PROG;
 181                         ctx->dirty |= FD_DIRTY_PROG;
 182                 }
 183
 184                 if (ir3_shader_key_changes_vs(last_key, key)) {
 185                         ctx->dirty_shader[PIPE_SHADER_VERTEX] |= FD_DIRTY_SHADER_PROG;
 186                         ctx->dirty |= FD_DIRTY_PROG;
 187                 }
 188
 189                 fd6_ctx->last_key = *key;
 190         }
 191 }
 192
 193 static bool
 194 fd6_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
 195              unsigned index_offset)
 196 {
 197         struct fd6_context *fd6_ctx = fd6_context(ctx);
 198         struct fd6_emit emit = {
 199                 .ctx = ctx,
 200                 .vtx  = &ctx->vtx,
 201                 .info = info,
 202                 .key = {
 203                         .vs = ctx->prog.vp,
 204                         .fs = ctx->prog.fp,
 205                         .key = {
 206                                 .color_two_side = ctx->rasterizer->light_twoside,
 207                                 .vclamp_color = ctx->rasterizer->clamp_vertex_color,
 208                                 .fclamp_color = ctx->rasterizer->clamp_fragment_color,
 209                                 .rasterflat = ctx->rasterizer->flatshade,
 210                                 .ucp_enables = ctx->rasterizer->clip_plane_enable,
 211                                 .has_per_samp = (fd6_ctx->fsaturate || fd6_ctx->vsaturate ||
 212                                                 fd6_ctx->fastc_srgb || fd6_ctx->vastc_srgb),
 213                                 .vsaturate_s = fd6_ctx->vsaturate_s,
 214                                 .vsaturate_t = fd6_ctx->vsaturate_t,
 215                                 .vsaturate_r = fd6_ctx->vsaturate_r,
 216                                 .fsaturate_s = fd6_ctx->fsaturate_s,
 217                                 .fsaturate_t = fd6_ctx->fsaturate_t,
 218                                 .fsaturate_r = fd6_ctx->fsaturate_r,
 219                                 .vastc_srgb = fd6_ctx->vastc_srgb,
 220                                 .fastc_srgb = fd6_ctx->fastc_srgb,
 221                                 .vsamples = ctx->tex[PIPE_SHADER_VERTEX].samples,
 222                                 .fsamples = ctx->tex[PIPE_SHADER_FRAGMENT].samples,
 223                         }
 224                 },
 225                 .rasterflat = ctx->rasterizer->flatshade,
 226                 .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
 227                 .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
 228         };
 229
 230         fixup_shader_state(ctx, &emit.key.key);
 231
 232         unsigned dirty = ctx->dirty;
 233
 234         if (!(dirty & FD_DIRTY_PROG)) {
 235                 emit.prog = fd6_ctx->prog;
 236         } else {
 237                 fd6_ctx->prog = fd6_emit_get_prog(&emit);
 238         }
 239
 240         emit.bs = fd6_emit_get_prog(&emit)->bs;
 241         emit.vs = fd6_emit_get_prog(&emit)->vs;
 242         emit.fs = fd6_emit_get_prog(&emit)->fs;
 243
 244         const struct ir3_shader_variant *vp = emit.vs;
 245         const struct ir3_shader_variant *fp = emit.fs;
 246
 247         /* do regular pass first, since that is more likely to fail compiling: */
 248
 249         if (!vp || !fp)
 250                 return false;
 251
 252         ctx->stats.vs_regs += ir3_shader_halfregs(vp);
 253         ctx->stats.fs_regs += ir3_shader_halfregs(fp);
 254
 255         /* figure out whether we need to disable LRZ write for binning
 256          * pass using draw pass's fp:
 257          */
 258         emit.no_lrz_write = fp->writes_pos || fp->has_kill;
 259
 260         emit.binning_pass = false;
 261         emit.dirty = dirty;
 262
 263         draw_impl(ctx, ctx->batch->draw, &emit, index_offset);
 264
 265         /* and now binning pass: */
 266         emit.binning_pass = true;
 267         emit.dirty = dirty & ~(FD_DIRTY_BLEND);
 268         emit.vs = fd6_emit_get_prog(&emit)->bs;
 269
 270         draw_impl(ctx, ctx->batch->binning, &emit, index_offset);
 271
 272         if (emit.streamout_mask) {
 273                 struct fd_ringbuffer *ring = ctx->batch->draw;
 274
 275                 for (unsigned i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
 276                         if (emit.streamout_mask & (1 << i)) {
 277                                 fd6_event_write(ctx->batch, ring, FLUSH_SO_0 + i, false);
 278                         }
 279                 }
 280         }
 281
 282         fd_context_all_clean(ctx);
 283
 284         return true;
 285 }
 286
 287 static bool is_z32(enum pipe_format format)
 288 {
 289         switch (format) {
 290         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 291         case PIPE_FORMAT_Z32_UNORM:
 292         case PIPE_FORMAT_Z32_FLOAT:
 293                 return true;
 294         default:
 295                 return false;
 296         }
 297 }
 298
 299 static void
 300 fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
 301 {
 302         struct fd_ringbuffer *ring;
 303
 304         // TODO mid-frame clears (ie. app doing crazy stuff)??  Maybe worth
 305         // splitting both clear and lrz clear out into their own rb's.  And
 306         // just throw away any draws prior to clear.  (Anything not fullscreen
 307         // clear, just fallback to generic path that treats it as a normal
 308         // draw
 309
 310         if (!batch->lrz_clear) {
 311                 batch->lrz_clear = fd_ringbuffer_new(batch->ctx->pipe, 0x1000);
 312                 fd_ringbuffer_set_parent(batch->lrz_clear, batch->gmem);
 313         }
 314
 315         ring = batch->lrz_clear;
 316
 317         emit_marker6(ring, 7);
 318         OUT_PKT7(ring, CP_SET_MARKER, 1);
 319         OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
 320         emit_marker6(ring, 7);
 321
 322         OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
 323         OUT_RING(ring, 0x10000000);
 324
 325         OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
 326         OUT_RING(ring, 0x7ffff);
 327
 328         emit_marker6(ring, 7);
 329         OUT_PKT7(ring, CP_SET_MARKER, 1);
 330         OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(0xc));
 331         emit_marker6(ring, 7);
 332
 333         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1);
 334         OUT_RING(ring, 0x0);
 335
 336         OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 13);
 337         OUT_RING(ring, 0x00000000);
 338         OUT_RING(ring, 0x00000000);
 339         OUT_RING(ring, 0x00000000);
 340         OUT_RING(ring, 0x00000000);
 341         OUT_RING(ring, 0x00000000);
 342         OUT_RING(ring, 0x00000000);
 343         OUT_RING(ring, 0x00000000);
 344         OUT_RING(ring, 0x00000000);
 345         OUT_RING(ring, 0x00000000);
 346         OUT_RING(ring, 0x00000000);
 347         OUT_RING(ring, 0x00000000);
 348         OUT_RING(ring, 0x00000000);
 349         OUT_RING(ring, 0x00000000);
 350
 351         OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_ACC0, 1);
 352         OUT_RING(ring, 0x0000f410);
 353
 354         OUT_PKT4(ring, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);
 355         OUT_RING(ring, A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(RB6_R16_UNORM) |
 356                         0x4f00080);
 357
 358         OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
 359         OUT_RING(ring, A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(RB6_R16_UNORM) |
 360                         0x4f00080);
 361
 362         fd6_event_write(batch, ring, UNK_1D, true);
 363         fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
 364
 365         OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
 366         OUT_RING(ring, fui(depth));
 367         OUT_RING(ring, 0x00000000);
 368         OUT_RING(ring, 0x00000000);
 369         OUT_RING(ring, 0x00000000);
 370
 371         OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
 372         OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(RB6_R16_UNORM) |
 373                         A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
 374                         A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
 375         OUT_RELOCW(ring, zsbuf->lrz, 0, 0, 0);
 376         OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(zsbuf->lrz_pitch * 2));
 377         OUT_RING(ring, 0x00000000);
 378         OUT_RING(ring, 0x00000000);
 379         OUT_RING(ring, 0x00000000);
 380         OUT_RING(ring, 0x00000000);
 381         OUT_RING(ring, 0x00000000);
 382
 383         OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
 384         OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X_X(0));
 385         OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X_X(0));
 386         OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y_Y(0));
 387         OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y_Y(0));
 388
 389         OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
 390         OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(0) |
 391                         A6XX_GRAS_2D_DST_TL_Y(0));
 392         OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(zsbuf->lrz_width - 1) |
 393                         A6XX_GRAS_2D_DST_BR_Y(zsbuf->lrz_height - 1));
 394
 395         fd6_event_write(batch, ring, 0x3f, false);
 396
 397         OUT_WFI5(ring);
 398
 399         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
 400         OUT_RING(ring, 0x1000000);
 401
 402         OUT_PKT7(ring, CP_BLIT, 1);
 403         OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
 404
 405         OUT_WFI5(ring);
 406
 407         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
 408         OUT_RING(ring, 0x0);
 409
 410         fd6_event_write(batch, ring, UNK_1D, true);
 411         fd6_event_write(batch, ring, FACENESS_FLUSH, true);
 412         fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
 413
 414         fd6_cache_flush(batch, ring);
 415 }
 416
 417 static bool
 418 fd6_clear(struct fd_context *ctx, unsigned buffers,
 419                 const union pipe_color_union *color, double depth, unsigned stencil)
 420 {
 421         struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
 422         struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
 423         struct fd_ringbuffer *ring = ctx->batch->draw;
 424
 425         if ((buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) &&
 426                         is_z32(pfb->zsbuf->format))
 427                 return false;
 428
 429         OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
 430         OUT_RING(ring, A6XX_RB_BLIT_SCISSOR_TL_X(scissor->minx) |
 431                          A6XX_RB_BLIT_SCISSOR_TL_Y(scissor->miny));
 432         OUT_RING(ring, A6XX_RB_BLIT_SCISSOR_BR_X(scissor->maxx - 1) |
 433                          A6XX_RB_BLIT_SCISSOR_BR_Y(scissor->maxy - 1));
 434
 435         if (buffers & PIPE_CLEAR_COLOR) {
 436                 for (int i = 0; i < pfb->nr_cbufs; i++) {
 437                         union util_color uc = {0};
 438
 439                         if (!pfb->cbufs[i])
 440                                 continue;
 441
 442                         if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
 443                                 continue;
 444
 445                         enum pipe_format pfmt = pfb->cbufs[i]->format;
 446
 447                         // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
 448                         union pipe_color_union swapped;
 449                         switch (fd6_pipe2swap(pfmt)) {
 450                         case WZYX:
 451                                 swapped.ui[0] = color->ui[0];
 452                                 swapped.ui[1] = color->ui[1];
 453                                 swapped.ui[2] = color->ui[2];
 454                                 swapped.ui[3] = color->ui[3];
 455                                 break;
 456                         case WXYZ:
 457                                 swapped.ui[2] = color->ui[0];
 458                                 swapped.ui[1] = color->ui[1];
 459                                 swapped.ui[0] = color->ui[2];
 460                                 swapped.ui[3] = color->ui[3];
 461                                 break;
 462                         case ZYXW:
 463                                 swapped.ui[3] = color->ui[0];
 464                                 swapped.ui[0] = color->ui[1];
 465                                 swapped.ui[1] = color->ui[2];
 466                                 swapped.ui[2] = color->ui[3];
 467                                 break;
 468                         case XYZW:
 469                                 swapped.ui[3] = color->ui[0];
 470                                 swapped.ui[2] = color->ui[1];
 471                                 swapped.ui[1] = color->ui[2];
 472                                 swapped.ui[0] = color->ui[3];
 473                                 break;
 474                         }
 475
 476                         if (util_format_is_pure_uint(pfmt)) {
 477                                 util_format_write_4ui(pfmt, swapped.ui, 0, &uc, 0, 0, 0, 1, 1);
 478                         } else if (util_format_is_pure_sint(pfmt)) {
 479                                 util_format_write_4i(pfmt, swapped.i, 0, &uc, 0, 0, 0, 1, 1);
 480                         } else {
 481                                 util_pack_color(swapped.f, pfmt, &uc);
 482                         }
 483
 484                         OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
 485                         OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
 486                                 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
 487
 488                         OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
 489                         OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
 490                                 A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
 491
 492                         OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
 493                         OUT_RINGP(ring, i, &ctx->batch->gmem_patches);
 494
 495                         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
 496                         OUT_RING(ring, 0);
 497
 498                         OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
 499                         OUT_RING(ring, uc.ui[0]);
 500                         OUT_RING(ring, uc.ui[1]);
 501                         OUT_RING(ring, uc.ui[2]);
 502                         OUT_RING(ring, uc.ui[3]);
 503
 504                         fd6_emit_blit(ctx->batch, ring);
 505                 }
 506         }
 507
 508         if (pfb->zsbuf && (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL))) {
 509                 enum pipe_format pfmt = pfb->zsbuf->format;
 510                 uint32_t clear = util_pack_z_stencil(pfmt, depth, stencil);
 511                 uint32_t mask = 0;
 512
 513                 if (buffers & PIPE_CLEAR_DEPTH)
 514                         mask |= 0x1;
 515
 516                 if (buffers & PIPE_CLEAR_STENCIL)
 517                         mask |= 0x2;
 518
 519                 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
 520                 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
 521                         A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
 522
 523                 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
 524                 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
 525                         // XXX UNK0 for separate stencil ??
 526                         A6XX_RB_BLIT_INFO_DEPTH |
 527                         A6XX_RB_BLIT_INFO_CLEAR_MASK(mask));
 528
 529                 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
 530                 OUT_RINGP(ring, MAX_RENDER_TARGETS, &ctx->batch->gmem_patches);
 531
 532                 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
 533                 OUT_RING(ring, 0);
 534
 535                 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
 536                 OUT_RING(ring, clear);
 537
 538                 fd6_emit_blit(ctx->batch, ring);
 539
 540                 if (pfb->zsbuf && (buffers & PIPE_CLEAR_DEPTH)) {
 541                         struct fd_resource *zsbuf = fd_resource(pfb->zsbuf->texture);
 542                         if (zsbuf->lrz) {
 543                                 zsbuf->lrz_valid = true;
 544                                 fd6_clear_lrz(ctx->batch, zsbuf, depth);
 545                         }
 546                 }
 547         }
 548
 549         return true;
 550 }
 551
 552 void
 553 fd6_draw_init(struct pipe_context *pctx)
 554 {
 555         struct fd_context *ctx = fd_context(pctx);
 556         ctx->draw_vbo = fd6_draw_vbo;
 557         ctx->clear = fd6_clear;
 558 }