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freedreno/a6xx: Simplify draw_emit() branches a bit
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_draw.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_prim.h"
32
33 #include "freedreno_state.h"
34 #include "freedreno_resource.h"
35
36 #include "fd6_draw.h"
37 #include "fd6_context.h"
38 #include "fd6_emit.h"
39 #include "fd6_program.h"
40 #include "fd6_format.h"
41 #include "fd6_zsa.h"
42
43 /* some bits in common w/ a4xx: */
44 #include "a4xx/fd4_draw.h"
45
46 static void
47 draw_emit_indirect(struct fd_batch *batch, struct fd_ringbuffer *ring,
48 enum pc_di_primtype primtype,
49 enum pc_di_vis_cull_mode vismode,
50 const struct pipe_draw_info *info,
51 unsigned index_offset)
52 {
53 struct fd_resource *ind = fd_resource(info->indirect->buffer);
54
55 if (info->index_size) {
56 struct pipe_resource *idx = info->index.resource;
57 unsigned max_indicies = (idx->width0 - info->indirect->offset) /
58 info->index_size;
59
60 OUT_PKT7(ring, CP_DRAW_INDX_INDIRECT, 6);
61 OUT_RINGP(ring, DRAW4(primtype, DI_SRC_SEL_DMA,
62 fd4_size2indextype(info->index_size), 0),
63 &batch->draw_patches);
64 OUT_RELOC(ring, fd_resource(idx)->bo,
65 index_offset, 0, 0);
66 // XXX: Check A5xx vs A6xx
67 OUT_RING(ring, A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies));
68 OUT_RELOC(ring, ind->bo, info->indirect->offset, 0, 0);
69 } else {
70 OUT_PKT7(ring, CP_DRAW_INDIRECT, 3);
71 OUT_RINGP(ring, DRAW4(primtype, DI_SRC_SEL_AUTO_INDEX, 0, 0),
72 &batch->draw_patches);
73 OUT_RELOC(ring, ind->bo, info->indirect->offset, 0, 0);
74 }
75 }
76
77 static void
78 draw_emit(struct fd_batch *batch, struct fd_ringbuffer *ring,
79 enum pc_di_primtype primtype,
80 enum pc_di_vis_cull_mode vismode,
81 const struct pipe_draw_info *info,
82 unsigned index_offset)
83 {
84 enum pc_di_src_sel src_sel;
85
86 if (info->index_size) {
87 assert(!info->has_user_indices);
88
89 struct pipe_resource *idx_buffer = info->index.resource;
90 uint32_t idx_size = info->index_size * info->count;
91 uint32_t idx_offset = index_offset + info->start * info->index_size;
92 enum a4xx_index_size idx_type = fd4_size2indextype(info->index_size);
93 src_sel = DI_SRC_SEL_DMA;
94
95 OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, 7);
96 if (vismode == USE_VISIBILITY) {
97 /* leave vis mode blank for now, it will be patched up when
98 * we know if we are binning or not
99 */
100 OUT_RINGP(ring, DRAW4(primtype, src_sel, idx_type, 0) | 0x2000,
101 &batch->draw_patches);
102 } else {
103 OUT_RING(ring, DRAW4(primtype, src_sel, idx_type, vismode) | 0x2000);
104 }
105 OUT_RING(ring, info->instance_count); /* NumInstances */
106 OUT_RING(ring, info->count); /* NumIndices */
107 OUT_RING(ring, 0x0); /* XXX */
108 OUT_RELOC(ring, fd_resource(idx_buffer)->bo, idx_offset, 0, 0);
109 OUT_RING (ring, idx_size);
110 } else {
111 src_sel = DI_SRC_SEL_AUTO_INDEX;
112
113 OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, 3);
114 if (vismode == USE_VISIBILITY) {
115 /* leave vis mode blank for now, it will be patched up when
116 * we know if we are binning or not
117 */
118 OUT_RINGP(ring, DRAW4(primtype, src_sel, INDEX4_SIZE_32_BIT, 0) | 0x2000,
119 &batch->draw_patches);
120 } else {
121 OUT_RING(ring, DRAW4(primtype, src_sel, INDEX4_SIZE_32_BIT, vismode) | 0x2000);
122 }
123 OUT_RING(ring, info->instance_count); /* NumInstances */
124 OUT_RING(ring, info->count); /* NumIndices */
125 }
126 }
127
128 static void
129 draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
130 struct fd6_emit *emit, unsigned index_offset)
131 {
132 const struct pipe_draw_info *info = emit->info;
133 enum pc_di_primtype primtype = ctx->primtypes[info->mode];
134
135 fd6_emit_state(ctx, ring, emit);
136
137 if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
138 fd6_emit_vertex_bufs(ring, emit);
139
140 OUT_PKT4(ring, REG_A6XX_VFD_INDEX_OFFSET, 2);
141 OUT_RING(ring, info->index_size ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
142 OUT_RING(ring, info->start_instance); /* VFD_INSTANCE_START_OFFSET */
143
144 OUT_PKT4(ring, REG_A6XX_PC_RESTART_INDEX, 1);
145 OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
146 info->restart_index : 0xffffffff);
147
148 fd6_emit_render_cntl(ctx, false, emit->key.binning_pass);
149
150 /* for debug after a lock up, write a unique counter value
151 * to scratch7 for each draw, to make it easier to match up
152 * register dumps to cmdstream. The combination of IB
153 * (scratch6) and DRAW is enough to "triangulate" the
154 * particular draw that caused lockup.
155 */
156 emit_marker6(ring, 7);
157
158 if (info->indirect) {
159 draw_emit_indirect(ctx->batch, ring, primtype,
160 emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
161 info, index_offset);
162 } else {
163 draw_emit(ctx->batch, ring, primtype,
164 emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
165 info, index_offset);
166 }
167
168 emit_marker6(ring, 7);
169 fd_reset_wfi(ctx->batch);
170 }
171
172 /* fixup dirty shader state in case some "unrelated" (from the state-
173 * tracker's perspective) state change causes us to switch to a
174 * different variant.
175 */
176 static void
177 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
178 {
179 struct fd6_context *fd6_ctx = fd6_context(ctx);
180 struct ir3_shader_key *last_key = &fd6_ctx->last_key;
181
182 if (!ir3_shader_key_equal(last_key, key)) {
183 if (ir3_shader_key_changes_fs(last_key, key)) {
184 ctx->dirty_shader[PIPE_SHADER_FRAGMENT] |= FD_DIRTY_SHADER_PROG;
185 ctx->dirty |= FD_DIRTY_PROG;
186 }
187
188 if (ir3_shader_key_changes_vs(last_key, key)) {
189 ctx->dirty_shader[PIPE_SHADER_VERTEX] |= FD_DIRTY_SHADER_PROG;
190 ctx->dirty |= FD_DIRTY_PROG;
191 }
192
193 fd6_ctx->last_key = *key;
194 }
195 }
196
197 static bool
198 fd6_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
199 unsigned index_offset)
200 {
201 struct fd6_context *fd6_ctx = fd6_context(ctx);
202 struct fd6_emit emit = {
203 .debug = &ctx->debug,
204 .vtx = &ctx->vtx,
205 .prog = &ctx->prog,
206 .info = info,
207 .key = {
208 .color_two_side = ctx->rasterizer->light_twoside,
209 .vclamp_color = ctx->rasterizer->clamp_vertex_color,
210 .fclamp_color = ctx->rasterizer->clamp_fragment_color,
211 .rasterflat = ctx->rasterizer->flatshade,
212 .half_precision = ctx->in_blit &&
213 fd_half_precision(&ctx->batch->framebuffer),
214 .ucp_enables = ctx->rasterizer->clip_plane_enable,
215 .has_per_samp = (fd6_ctx->fsaturate || fd6_ctx->vsaturate ||
216 fd6_ctx->fastc_srgb || fd6_ctx->vastc_srgb),
217 .vsaturate_s = fd6_ctx->vsaturate_s,
218 .vsaturate_t = fd6_ctx->vsaturate_t,
219 .vsaturate_r = fd6_ctx->vsaturate_r,
220 .fsaturate_s = fd6_ctx->fsaturate_s,
221 .fsaturate_t = fd6_ctx->fsaturate_t,
222 .fsaturate_r = fd6_ctx->fsaturate_r,
223 .vastc_srgb = fd6_ctx->vastc_srgb,
224 .fastc_srgb = fd6_ctx->fastc_srgb,
225 .vsamples = ctx->tex[PIPE_SHADER_VERTEX].samples,
226 .fsamples = ctx->tex[PIPE_SHADER_FRAGMENT].samples,
227 },
228 .rasterflat = ctx->rasterizer->flatshade,
229 .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
230 .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
231 };
232
233 fixup_shader_state(ctx, &emit.key);
234
235 unsigned dirty = ctx->dirty;
236 const struct ir3_shader_variant *vp = fd6_emit_get_vp(&emit);
237 const struct ir3_shader_variant *fp = fd6_emit_get_fp(&emit);
238
239 /* do regular pass first, since that is more likely to fail compiling: */
240
241 if (!vp || !fp)
242 return false;
243
244 ctx->stats.vs_regs += ir3_shader_halfregs(vp);
245 ctx->stats.fs_regs += ir3_shader_halfregs(fp);
246
247 /* figure out whether we need to disable LRZ write for binning
248 * pass using draw pass's fp:
249 */
250 emit.no_lrz_write = fp->writes_pos || fp->has_kill;
251
252 emit.key.binning_pass = false;
253 emit.dirty = dirty;
254
255 draw_impl(ctx, ctx->batch->draw, &emit, index_offset);
256
257 /* and now binning pass: */
258 emit.key.binning_pass = true;
259 emit.dirty = dirty & ~(FD_DIRTY_BLEND);
260 emit.vp = NULL; /* we changed key so need to refetch vp */
261 emit.fp = NULL;
262 draw_impl(ctx, ctx->batch->binning, &emit, index_offset);
263
264 if (emit.streamout_mask) {
265 struct fd_ringbuffer *ring = ctx->batch->draw;
266
267 for (unsigned i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
268 if (emit.streamout_mask & (1 << i)) {
269 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
270 OUT_RING(ring, FLUSH_SO_0 + i);
271 }
272 }
273 }
274
275 fd_context_all_clean(ctx);
276
277 return true;
278 }
279
280 static bool is_z32(enum pipe_format format)
281 {
282 switch (format) {
283 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
284 case PIPE_FORMAT_Z32_UNORM:
285 case PIPE_FORMAT_Z32_FLOAT:
286 return true;
287 default:
288 return false;
289 }
290 }
291
292 #if 0
293 static void
294 fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
295 {
296 struct fd_ringbuffer *ring;
297 uint32_t clear = util_pack_z(PIPE_FORMAT_Z16_UNORM, depth);
298
299 // TODO mid-frame clears (ie. app doing crazy stuff)?? Maybe worth
300 // splitting both clear and lrz clear out into their own rb's. And
301 // just throw away any draws prior to clear. (Anything not fullscreen
302 // clear, just fallback to generic path that treats it as a normal
303 // draw
304
305 if (!batch->lrz_clear) {
306 batch->lrz_clear = fd_ringbuffer_new(batch->ctx->pipe, 0x1000);
307 fd_ringbuffer_set_parent(batch->lrz_clear, batch->gmem);
308 }
309
310 ring = batch->lrz_clear;
311
312 OUT_WFI5(ring);
313
314 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
315 OUT_RING(ring, 0x10000000);
316
317 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
318 OUT_RING(ring, 0x20fffff);
319
320 OUT_PKT4(ring, REG_A6XX_GRAS_SU_CNTL, 1);
321 OUT_RING(ring, A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(0.0));
322
323 OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
324 OUT_RING(ring, 0x00000000);
325
326 OUT_PKT4(ring, REG_A6XX_GRAS_CL_CNTL, 1);
327 OUT_RING(ring, 0x00000181);
328
329 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
330 OUT_RING(ring, 0x00000000);
331
332 OUT_PKT4(ring, REG_A6XX_RB_MRT_BUF_INFO(0), 5);
333 OUT_RING(ring, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(RB5_R16_UNORM) |
334 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(TILE6_LINEAR) |
335 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(WZYX));
336 OUT_RING(ring, A6XX_RB_MRT_PITCH(zsbuf->lrz_pitch * 2));
337 OUT_RING(ring, A6XX_RB_MRT_ARRAY_PITCH(fd_bo_size(zsbuf->lrz)));
338 OUT_RELOCW(ring, zsbuf->lrz, 0x1000, 0, 0);
339
340 OUT_PKT4(ring, REG_A6XX_RB_RENDER_CNTL, 1);
341 OUT_RING(ring, 0x00000000);
342
343 OUT_PKT4(ring, REG_A6XX_RB_DEST_MSAA_CNTL, 1);
344 OUT_RING(ring, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE));
345
346 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CNTL, 1);
347 OUT_RING(ring, A6XX_RB_BLIT_CNTL_BUF(BLIT_MRT0));
348
349 OUT_PKT4(ring, REG_A6XX_RB_CLEAR_CNTL, 1);
350 OUT_RING(ring, A6XX_RB_CLEAR_CNTL_FAST_CLEAR |
351 A6XX_RB_CLEAR_CNTL_MASK(0xf));
352
353 OUT_PKT4(ring, REG_A6XX_RB_CLEAR_COLOR_DW0, 1);
354 OUT_RING(ring, clear); /* RB_CLEAR_COLOR_DW0 */
355
356 OUT_PKT4(ring, REG_A6XX_VSC_RESOLVE_CNTL, 2);
357 OUT_RING(ring, A6XX_VSC_RESOLVE_CNTL_X(zsbuf->lrz_width) |
358 A6XX_VSC_RESOLVE_CNTL_Y(zsbuf->lrz_height));
359 OUT_RING(ring, 0x00000000); // XXX UNKNOWN_0CDE
360
361 OUT_PKT4(ring, REG_A6XX_RB_CNTL, 1);
362 OUT_RING(ring, A6XX_RB_CNTL_BYPASS);
363
364 OUT_PKT4(ring, REG_A6XX_RB_RESOLVE_CNTL_1, 2);
365 OUT_RING(ring, A6XX_RB_RESOLVE_CNTL_1_X(0) |
366 A6XX_RB_RESOLVE_CNTL_1_Y(0));
367 OUT_RING(ring, A6XX_RB_RESOLVE_CNTL_2_X(zsbuf->lrz_width - 1) |
368 A6XX_RB_RESOLVE_CNTL_2_Y(zsbuf->lrz_height - 1));
369
370 fd6_emit_blit(batch->ctx, ring);
371 }
372 #endif
373
374 #if 0
375 clear_with_cp_blit()
376 {
377 /* Clear with CP_BLIT */
378 WRITE(REG_A6XX_GRAS_2D_BLIT_CNTL, 0x10f43180);
379
380 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 7);
381 OUT_RING(ring, 0);
382 OUT_RING(ring, 0);
383 OUT_RING(ring, 0);
384 OUT_RING(ring, 0);
385 OUT_RING(ring, 0);
386 OUT_RING(ring, 0);
387 OUT_RING(ring, 0);
388
389 WRITE(0xacc0, 0xf181);
390 WRITE(0xacc0, 0xf181);
391
392 WRITE(REG_A6XX_GRAS_2D_BLIT_CNTL, 0x10f43180);
393 WRITE(REG_A6XX_RB_2D_BLIT_CNTL, 0x10f43180);
394
395 OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
396 OUT_RING(ring, 0);
397 OUT_RING(ring, 0);
398 OUT_RING(ring, 0xff);
399 OUT_RING(ring, 0);
400
401 DBG("%x %x %x %x\n", color->ui[0], color->ui[1], color->ui[2], color->ui[3]);
402
403 struct pipe_surface *psurf = pfb->cbufs[0];
404 struct fd_resource *rsc = fd_resource(psurf->texture);
405 struct fd_resource_slice *slice = fd_resource_slice(rsc, psurf->u.tex.level);
406
407 uint32_t offset = fd_resource_offset(rsc, psurf->u.tex.level,
408 psurf->u.tex.first_layer);
409 uint32_t stride = slice->pitch * rsc->cpp;
410
411 enum a6xx_color_fmt format = fd6_pipe2color(pfmt);
412 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
413 OUT_RING(ring,
414 A6XX_RB_2D_DST_INFO_COLOR_FORMAT(format) |
415 A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
416 A6XX_RB_2D_DST_INFO_COLOR_SWAP(WXYZ));
417 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* RB_2D_DST_LO/HI */
418 OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(stride));
419 OUT_RING(ring, 0);
420 OUT_RING(ring, 0);
421 OUT_RING(ring, 0);
422 OUT_RING(ring, 0);
423 OUT_RING(ring, 0);
424
425 OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
426 OUT_RING(ring, 0);
427 OUT_RING(ring, 0);
428 OUT_RING(ring, 0);
429 OUT_RING(ring, 0);
430
431 OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
432 OUT_RING(ring,
433 A6XX_GRAS_2D_DST_TL_X(ctx->batch->max_scissor.minx) |
434 A6XX_GRAS_2D_DST_TL_Y(ctx->batch->max_scissor.miny));
435 OUT_RING(ring,
436 A6XX_GRAS_2D_DST_BR_X(ctx->batch->max_scissor.maxx) |
437 A6XX_GRAS_2D_DST_BR_Y(ctx->batch->max_scissor.maxy));
438
439 OUT_PKT7(ring, CP_BLIT, 1);
440 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
441 }
442 #endif
443
444 static bool
445 fd6_clear(struct fd_context *ctx, unsigned buffers,
446 const union pipe_color_union *color, double depth, unsigned stencil)
447 {
448 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
449 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
450 struct fd_ringbuffer *ring = ctx->batch->draw;
451
452 if ((buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) &&
453 is_z32(pfb->zsbuf->format))
454 return false;
455
456 fd6_emit_render_cntl(ctx, true, false);
457
458 OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
459 OUT_RING(ring, A6XX_RB_BLIT_SCISSOR_TL_X(scissor->minx) |
460 A6XX_RB_BLIT_SCISSOR_TL_Y(scissor->miny));
461 OUT_RING(ring, A6XX_RB_BLIT_SCISSOR_BR_X(scissor->maxx - 1) |
462 A6XX_RB_BLIT_SCISSOR_BR_Y(scissor->maxy - 1));
463
464 if (buffers & PIPE_CLEAR_COLOR) {
465 for (int i = 0; i < pfb->nr_cbufs; i++) {
466 union util_color uc = {0};
467
468 if (!pfb->cbufs[i])
469 continue;
470
471 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
472 continue;
473
474 enum pipe_format pfmt = pfb->cbufs[i]->format;
475
476 // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
477 union pipe_color_union swapped;
478 switch (fd6_pipe2swap(pfmt)) {
479 case WZYX:
480 swapped.ui[0] = color->ui[0];
481 swapped.ui[1] = color->ui[1];
482 swapped.ui[2] = color->ui[2];
483 swapped.ui[3] = color->ui[3];
484 break;
485 case WXYZ:
486 swapped.ui[2] = color->ui[0];
487 swapped.ui[1] = color->ui[1];
488 swapped.ui[0] = color->ui[2];
489 swapped.ui[3] = color->ui[3];
490 break;
491 case ZYXW:
492 swapped.ui[3] = color->ui[0];
493 swapped.ui[0] = color->ui[1];
494 swapped.ui[1] = color->ui[2];
495 swapped.ui[2] = color->ui[3];
496 break;
497 case XYZW:
498 swapped.ui[3] = color->ui[0];
499 swapped.ui[2] = color->ui[1];
500 swapped.ui[1] = color->ui[2];
501 swapped.ui[0] = color->ui[3];
502 break;
503 }
504
505 if (util_format_is_pure_uint(pfmt)) {
506 util_format_write_4ui(pfmt, swapped.ui, 0, &uc, 0, 0, 0, 1, 1);
507 } else if (util_format_is_pure_sint(pfmt)) {
508 util_format_write_4i(pfmt, swapped.i, 0, &uc, 0, 0, 0, 1, 1);
509 } else {
510 util_pack_color(swapped.f, pfmt, &uc);
511 }
512
513 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
514 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
515 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
516
517 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
518 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
519 A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
520
521 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
522 OUT_RINGP(ring, i, &ctx->batch->gmem_patches);
523
524 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
525 OUT_RING(ring, 0);
526
527 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
528 OUT_RING(ring, uc.ui[0]);
529 OUT_RING(ring, uc.ui[1]);
530 OUT_RING(ring, uc.ui[2]);
531 OUT_RING(ring, uc.ui[3]);
532
533 fd6_emit_blit(ctx, ring);
534 }
535 }
536
537 if (pfb->zsbuf && (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL))) {
538 enum pipe_format pfmt = pfb->zsbuf->format;
539 uint32_t clear = util_pack_z_stencil(pfmt, depth, stencil);
540 uint32_t mask = 0;
541
542 if (buffers & PIPE_CLEAR_DEPTH)
543 mask |= 0x1;
544
545 if (buffers & PIPE_CLEAR_STENCIL)
546 mask |= 0x2;
547
548 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
549 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
550 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
551
552 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
553 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
554 // XXX UNK0 for separate stencil ??
555 A6XX_RB_BLIT_INFO_DEPTH |
556 A6XX_RB_BLIT_INFO_CLEAR_MASK(mask));
557
558 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
559 OUT_RINGP(ring, MAX_RENDER_TARGETS, &ctx->batch->gmem_patches);
560
561 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
562 OUT_RING(ring, 0);
563
564 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
565 OUT_RING(ring, clear);
566
567 fd6_emit_blit(ctx, ring);
568
569 #if 0
570 if (pfb->zsbuf && (buffers & PIPE_CLEAR_DEPTH)) {
571 struct fd_resource *zsbuf = fd_resource(pfb->zsbuf->texture);
572 if (zsbuf->lrz) {
573 zsbuf->lrz_valid = true;
574 fd6_clear_lrz(ctx->batch, zsbuf, depth);
575 }
576 }
577 #endif
578 }
579
580 return true;
581 }
582
583 void
584 fd6_draw_init(struct pipe_context *pctx)
585 {
586 struct fd_context *ctx = fd_context(pctx);
587 ctx->draw_vbo = fd6_draw_vbo;
588 ctx->clear = fd6_clear;
589 }