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freedreno/layout: layout simplifications and pitch from level 0 pitch
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_gmem.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include <stdio.h>
29
30 #include "pipe/p_state.h"
31 #include "util/u_string.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/format/u_format.h"
35
36 #include "freedreno_draw.h"
37 #include "freedreno_log.h"
38 #include "freedreno_state.h"
39 #include "freedreno_resource.h"
40
41 #include "fd6_blitter.h"
42 #include "fd6_gmem.h"
43 #include "fd6_context.h"
44 #include "fd6_draw.h"
45 #include "fd6_emit.h"
46 #include "fd6_program.h"
47 #include "fd6_format.h"
48 #include "fd6_resource.h"
49 #include "fd6_zsa.h"
50 #include "fd6_pack.h"
51
52 /**
53 * Emits the flags registers, suitable for RB_MRT_FLAG_BUFFER,
54 * RB_DEPTH_FLAG_BUFFER, SP_PS_2D_SRC_FLAGS, and RB_BLIT_FLAG_DST.
55 */
56 void
57 fd6_emit_flag_reference(struct fd_ringbuffer *ring, struct fd_resource *rsc,
58 int level, int layer)
59 {
60 if (fd_resource_ubwc_enabled(rsc, level)) {
61 OUT_RELOC(ring, rsc->bo, fd_resource_ubwc_offset(rsc, level, layer), 0, 0);
62 OUT_RING(ring,
63 A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(fdl_ubwc_pitch(&rsc->layout, level)) |
64 A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->layout.ubwc_layer_size >> 2));
65 } else {
66 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
67 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
68 OUT_RING(ring, 0x00000000);
69 }
70 }
71
72 static void
73 emit_mrt(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb,
74 const struct fd_gmem_stateobj *gmem)
75 {
76 unsigned char mrt_comp[A6XX_MAX_RENDER_TARGETS] = {0};
77 unsigned srgb_cntl = 0;
78 unsigned i;
79
80 unsigned max_layer_index = 0;
81
82 for (i = 0; i < pfb->nr_cbufs; i++) {
83 enum a6xx_format format = 0;
84 enum a3xx_color_swap swap = WZYX;
85 bool sint = false, uint = false;
86 struct fd_resource *rsc = NULL;
87 struct fdl_slice *slice = NULL;
88 uint32_t stride = 0;
89 uint32_t offset;
90 uint32_t tile_mode;
91
92 if (!pfb->cbufs[i])
93 continue;
94
95 mrt_comp[i] = 0xf;
96
97 struct pipe_surface *psurf = pfb->cbufs[i];
98 enum pipe_format pformat = psurf->format;
99 rsc = fd_resource(psurf->texture);
100 if (!rsc->bo)
101 continue;
102
103 uint32_t base = gmem ? gmem->cbuf_base[i] : 0;
104 slice = fd_resource_slice(rsc, psurf->u.tex.level);
105 format = fd6_pipe2color(pformat);
106 sint = util_format_is_pure_sint(pformat);
107 uint = util_format_is_pure_uint(pformat);
108
109 if (util_format_is_srgb(pformat))
110 srgb_cntl |= (1 << i);
111
112 offset = fd_resource_offset(rsc, psurf->u.tex.level,
113 psurf->u.tex.first_layer);
114
115 stride = fd_resource_pitch(rsc, psurf->u.tex.level);
116 swap = fd6_resource_swap(rsc, pformat);
117
118 tile_mode = fd_resource_tile_mode(psurf->texture, psurf->u.tex.level);
119 max_layer_index = psurf->u.tex.last_layer - psurf->u.tex.first_layer;
120
121 debug_assert((offset + slice->size0) <= fd_bo_size(rsc->bo));
122
123 OUT_REG(ring,
124 A6XX_RB_MRT_BUF_INFO(i,
125 .color_format = format,
126 .color_tile_mode = tile_mode,
127 .color_swap = swap),
128 A6XX_RB_MRT_PITCH(i, .a6xx_rb_mrt_pitch = stride),
129 A6XX_RB_MRT_ARRAY_PITCH(i, .a6xx_rb_mrt_array_pitch = slice->size0),
130 A6XX_RB_MRT_BASE(i, .bo = rsc->bo, .bo_offset = offset),
131 A6XX_RB_MRT_BASE_GMEM(i, .unknown = base));
132
133 OUT_REG(ring,
134 A6XX_SP_FS_MRT_REG(i, .color_format = format,
135 .color_sint = sint, .color_uint = uint));
136
137 OUT_PKT4(ring, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 3);
138 fd6_emit_flag_reference(ring, rsc,
139 psurf->u.tex.level, psurf->u.tex.first_layer);
140 }
141
142 OUT_REG(ring, A6XX_RB_SRGB_CNTL(.dword = srgb_cntl));
143 OUT_REG(ring, A6XX_SP_SRGB_CNTL(.dword = srgb_cntl));
144
145 OUT_REG(ring, A6XX_RB_RENDER_COMPONENTS(
146 .rt0 = mrt_comp[0],
147 .rt1 = mrt_comp[1],
148 .rt2 = mrt_comp[2],
149 .rt3 = mrt_comp[3],
150 .rt4 = mrt_comp[4],
151 .rt5 = mrt_comp[5],
152 .rt6 = mrt_comp[6],
153 .rt7 = mrt_comp[7]));
154
155 OUT_REG(ring, A6XX_SP_FS_RENDER_COMPONENTS(
156 .rt0 = mrt_comp[0],
157 .rt1 = mrt_comp[1],
158 .rt2 = mrt_comp[2],
159 .rt3 = mrt_comp[3],
160 .rt4 = mrt_comp[4],
161 .rt5 = mrt_comp[5],
162 .rt6 = mrt_comp[6],
163 .rt7 = mrt_comp[7]));
164
165 OUT_REG(ring, A6XX_GRAS_MAX_LAYER_INDEX(max_layer_index));
166 }
167
168 static void
169 emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
170 const struct fd_gmem_stateobj *gmem)
171 {
172 if (zsbuf) {
173 struct fd_resource *rsc = fd_resource(zsbuf->texture);
174 enum a6xx_depth_format fmt = fd6_pipe2depth(zsbuf->format);
175 uint32_t stride = fd_resource_pitch(rsc, 0);
176 uint32_t size = fd_resource_slice(rsc, 0)->size0;
177 uint32_t base = gmem ? gmem->zsbuf_base[0] : 0;
178 uint32_t offset = fd_resource_offset(rsc, zsbuf->u.tex.level,
179 zsbuf->u.tex.first_layer);
180
181 OUT_REG(ring,
182 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = fmt),
183 A6XX_RB_DEPTH_BUFFER_PITCH(.a6xx_rb_depth_buffer_pitch = stride),
184 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(.a6xx_rb_depth_buffer_array_pitch = size),
185 A6XX_RB_DEPTH_BUFFER_BASE(.bo = rsc->bo, .bo_offset = offset),
186 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(.dword = base));
187
188 OUT_REG(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt));
189
190 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
191 fd6_emit_flag_reference(ring, rsc,
192 zsbuf->u.tex.level, zsbuf->u.tex.first_layer);
193
194 if (rsc->lrz) {
195 OUT_REG(ring,
196 A6XX_GRAS_LRZ_BUFFER_BASE(.bo = rsc->lrz),
197 A6XX_GRAS_LRZ_BUFFER_PITCH(.pitch = rsc->lrz_pitch),
198 // XXX a6xx seems to use a different buffer here.. not sure what for..
199 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO(0),
200 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI(0));
201 } else {
202 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
203 OUT_RING(ring, 0x00000000);
204 OUT_RING(ring, 0x00000000);
205 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
206 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
207 OUT_RING(ring, 0x00000000);
208 }
209
210 /* NOTE: blob emits GRAS_LRZ_CNTL plus GRAZ_LRZ_BUFFER_BASE
211 * plus this CP_EVENT_WRITE at the end in it's own IB..
212 */
213 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
214 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(UNK_25));
215
216 if (rsc->stencil) {
217 stride = fd_resource_pitch(rsc->stencil, 0);
218 size = fd_resource_slice(rsc->stencil, 0)->size0;
219 uint32_t base = gmem ? gmem->zsbuf_base[1] : 0;
220
221 OUT_REG(ring,
222 A6XX_RB_STENCIL_INFO(.separate_stencil = true),
223 A6XX_RB_STENCIL_BUFFER_PITCH(.a6xx_rb_stencil_buffer_pitch = stride),
224 A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(.a6xx_rb_stencil_buffer_array_pitch = size),
225 A6XX_RB_STENCIL_BUFFER_BASE(.bo = rsc->stencil->bo),
226 A6XX_RB_STENCIL_BUFFER_BASE_GMEM(.dword = base));
227 } else {
228 OUT_REG(ring, A6XX_RB_STENCIL_INFO(0));
229 }
230 } else {
231 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
232 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
233 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
234 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
235 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
236 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
237 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
238
239 OUT_REG(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE));
240
241 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
242 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
243 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
244 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
245 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
246 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
247
248 OUT_REG(ring, A6XX_RB_STENCIL_INFO(0));
249 }
250 }
251
252 static bool
253 use_hw_binning(struct fd_batch *batch)
254 {
255 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
256
257 // TODO figure out hw limits for binning
258
259 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) >= 2) &&
260 (batch->num_draws > 0);
261 }
262
263 static void
264 patch_fb_read(struct fd_batch *batch)
265 {
266 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
267
268 for (unsigned i = 0; i < fd_patch_num_elements(&batch->fb_read_patches); i++) {
269 struct fd_cs_patch *patch = fd_patch_element(&batch->fb_read_patches, i);
270 *patch->cs = patch->val | A6XX_TEX_CONST_2_PITCH(gmem->bin_w * gmem->cbuf_cpp[0]);
271 }
272 util_dynarray_clear(&batch->fb_read_patches);
273 }
274
275 static void
276 update_render_cntl(struct fd_batch *batch, struct pipe_framebuffer_state *pfb, bool binning)
277 {
278 struct fd_ringbuffer *ring = batch->gmem;
279 uint32_t cntl = 0;
280 bool depth_ubwc_enable = false;
281 uint32_t mrts_ubwc_enable = 0;
282 int i;
283
284 if (pfb->zsbuf) {
285 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
286 depth_ubwc_enable = fd_resource_ubwc_enabled(rsc, pfb->zsbuf->u.tex.level);
287 }
288
289 for (i = 0; i < pfb->nr_cbufs; i++) {
290 if (!pfb->cbufs[i])
291 continue;
292
293 struct pipe_surface *psurf = pfb->cbufs[i];
294 struct fd_resource *rsc = fd_resource(psurf->texture);
295 if (!rsc->bo)
296 continue;
297
298 if (fd_resource_ubwc_enabled(rsc, psurf->u.tex.level))
299 mrts_ubwc_enable |= 1 << i;
300 }
301
302 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
303 if (binning)
304 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
305
306 OUT_PKT7(ring, CP_REG_WRITE, 3);
307 OUT_RING(ring, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL));
308 OUT_RING(ring, REG_A6XX_RB_RENDER_CNTL);
309 OUT_RING(ring, cntl |
310 COND(depth_ubwc_enable, A6XX_RB_RENDER_CNTL_FLAG_DEPTH) |
311 A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable));
312 }
313
314 /* extra size to store VSC_DRAW_STRM_SIZE: */
315 #define VSC_DRAW_STRM_SIZE(pitch) ((pitch) * 32 + 0x100)
316 #define VSC_PRIM_STRM_SIZE(pitch) ((pitch) * 32)
317
318 static void
319 update_vsc_pipe(struct fd_batch *batch)
320 {
321 struct fd_context *ctx = batch->ctx;
322 struct fd6_context *fd6_ctx = fd6_context(ctx);
323 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
324 struct fd_ringbuffer *ring = batch->gmem;
325 int i;
326
327 if (batch->draw_strm_bits/8 > fd6_ctx->vsc_draw_strm_pitch) {
328 if (fd6_ctx->vsc_draw_strm)
329 fd_bo_del(fd6_ctx->vsc_draw_strm);
330 fd6_ctx->vsc_draw_strm = NULL;
331 /* Note: probably only need to align to 0x40, but aligning stronger
332 * reduces the odds that we will have to realloc again on the next
333 * frame:
334 */
335 fd6_ctx->vsc_draw_strm_pitch = align(batch->draw_strm_bits/8, 0x4000);
336 debug_printf("pre-resize VSC_DRAW_STRM_PITCH to: 0x%x\n",
337 fd6_ctx->vsc_draw_strm_pitch);
338 }
339
340 if (batch->prim_strm_bits/8 > fd6_ctx->vsc_prim_strm_pitch) {
341 if (fd6_ctx->vsc_prim_strm)
342 fd_bo_del(fd6_ctx->vsc_prim_strm);
343 fd6_ctx->vsc_prim_strm = NULL;
344 fd6_ctx->vsc_prim_strm_pitch = align(batch->prim_strm_bits/8, 0x4000);
345 debug_printf("pre-resize VSC_PRIM_STRM_PITCH to: 0x%x\n",
346 fd6_ctx->vsc_prim_strm_pitch);
347 }
348
349 if (!fd6_ctx->vsc_draw_strm) {
350 fd6_ctx->vsc_draw_strm = fd_bo_new(ctx->screen->dev,
351 VSC_DRAW_STRM_SIZE(fd6_ctx->vsc_draw_strm_pitch),
352 DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_draw_strm");
353 }
354
355 if (!fd6_ctx->vsc_prim_strm) {
356 fd6_ctx->vsc_prim_strm = fd_bo_new(ctx->screen->dev,
357 VSC_PRIM_STRM_SIZE(fd6_ctx->vsc_prim_strm_pitch),
358 DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_prim_strm");
359 }
360
361 OUT_REG(ring,
362 A6XX_VSC_BIN_SIZE(.width = gmem->bin_w, .height = gmem->bin_h),
363 A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(
364 .bo = fd6_ctx->vsc_draw_strm,
365 .bo_offset = 32 * fd6_ctx->vsc_draw_strm_pitch));
366
367 OUT_REG(ring, A6XX_VSC_BIN_COUNT(.nx = gmem->nbins_x,
368 .ny = gmem->nbins_y));
369
370 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
371 for (i = 0; i < 32; i++) {
372 const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[i];
373 OUT_RING(ring, A6XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
374 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
375 A6XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
376 A6XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
377 }
378
379 OUT_REG(ring,
380 A6XX_VSC_PRIM_STRM_ADDRESS(.bo = fd6_ctx->vsc_prim_strm),
381 A6XX_VSC_PRIM_STRM_PITCH(.dword = fd6_ctx->vsc_prim_strm_pitch),
382 A6XX_VSC_PRIM_STRM_LIMIT(.dword = fd6_ctx->vsc_prim_strm_pitch - 64));
383
384 OUT_REG(ring,
385 A6XX_VSC_DRAW_STRM_ADDRESS(.bo = fd6_ctx->vsc_draw_strm),
386 A6XX_VSC_DRAW_STRM_PITCH(.dword = fd6_ctx->vsc_draw_strm_pitch),
387 A6XX_VSC_DRAW_STRM_LIMIT(.dword = fd6_ctx->vsc_draw_strm_pitch - 64));
388 }
389
390 /*
391 * If overflow is detected, either 0x1 (VSC_DRAW_STRM overflow) or 0x3
392 * (VSC_PRIM_STRM overflow) plus the size of the overflowed buffer is
393 * written to control->vsc_overflow. This allows the CPU to
394 * detect which buffer overflowed (and, since the current size is
395 * encoded as well, this protects against already-submitted but
396 * not executed batches from fooling the CPU into increasing the
397 * size again unnecessarily).
398 */
399 static void
400 emit_vsc_overflow_test(struct fd_batch *batch)
401 {
402 struct fd_ringbuffer *ring = batch->gmem;
403 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
404 struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
405
406 debug_assert((fd6_ctx->vsc_draw_strm_pitch & 0x3) == 0);
407 debug_assert((fd6_ctx->vsc_prim_strm_pitch & 0x3) == 0);
408
409 /* Check for overflow, write vsc_scratch if detected: */
410 for (int i = 0; i < gmem->num_vsc_pipes; i++) {
411 OUT_PKT7(ring, CP_COND_WRITE5, 8);
412 OUT_RING(ring, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
413 CP_COND_WRITE5_0_WRITE_MEMORY);
414 OUT_RING(ring, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i)));
415 OUT_RING(ring, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
416 OUT_RING(ring, CP_COND_WRITE5_3_REF(fd6_ctx->vsc_draw_strm_pitch - 64));
417 OUT_RING(ring, CP_COND_WRITE5_4_MASK(~0));
418 OUT_RELOC(ring, control_ptr(fd6_ctx, vsc_overflow)); /* WRITE_ADDR_LO/HI */
419 OUT_RING(ring, CP_COND_WRITE5_7_WRITE_DATA(1 + fd6_ctx->vsc_draw_strm_pitch));
420
421 OUT_PKT7(ring, CP_COND_WRITE5, 8);
422 OUT_RING(ring, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
423 CP_COND_WRITE5_0_WRITE_MEMORY);
424 OUT_RING(ring, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i)));
425 OUT_RING(ring, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
426 OUT_RING(ring, CP_COND_WRITE5_3_REF(fd6_ctx->vsc_prim_strm_pitch - 64));
427 OUT_RING(ring, CP_COND_WRITE5_4_MASK(~0));
428 OUT_RELOC(ring, control_ptr(fd6_ctx, vsc_overflow)); /* WRITE_ADDR_LO/HI */
429 OUT_RING(ring, CP_COND_WRITE5_7_WRITE_DATA(3 + fd6_ctx->vsc_prim_strm_pitch));
430 }
431
432 OUT_PKT7(ring, CP_WAIT_MEM_WRITES, 0);
433 }
434
435 static void
436 check_vsc_overflow(struct fd_context *ctx)
437 {
438 struct fd6_context *fd6_ctx = fd6_context(ctx);
439 struct fd6_control *control = fd_bo_map(fd6_ctx->control_mem);
440 uint32_t vsc_overflow = control->vsc_overflow;
441
442 if (!vsc_overflow)
443 return;
444
445 /* clear overflow flag: */
446 control->vsc_overflow = 0;
447
448 unsigned buffer = vsc_overflow & 0x3;
449 unsigned size = vsc_overflow & ~0x3;
450
451 if (buffer == 0x1) {
452 /* VSC_DRAW_STRM overflow: */
453
454 if (size < fd6_ctx->vsc_draw_strm_pitch) {
455 /* we've already increased the size, this overflow is
456 * from a batch submitted before resize, but executed
457 * after
458 */
459 return;
460 }
461
462 fd_bo_del(fd6_ctx->vsc_draw_strm);
463 fd6_ctx->vsc_draw_strm = NULL;
464 fd6_ctx->vsc_draw_strm_pitch *= 2;
465
466 debug_printf("resized VSC_DRAW_STRM_PITCH to: 0x%x\n",
467 fd6_ctx->vsc_draw_strm_pitch);
468
469 } else if (buffer == 0x3) {
470 /* VSC_PRIM_STRM overflow: */
471
472 if (size < fd6_ctx->vsc_prim_strm_pitch) {
473 /* we've already increased the size */
474 return;
475 }
476
477 fd_bo_del(fd6_ctx->vsc_prim_strm);
478 fd6_ctx->vsc_prim_strm = NULL;
479 fd6_ctx->vsc_prim_strm_pitch *= 2;
480
481 debug_printf("resized VSC_PRIM_STRM_PITCH to: 0x%x\n",
482 fd6_ctx->vsc_prim_strm_pitch);
483
484 } else {
485 /* NOTE: it's possible, for example, for overflow to corrupt the
486 * control page. I mostly just see this hit if I set initial VSC
487 * buffer size extremely small. Things still seem to recover,
488 * but maybe we should pre-emptively realloc vsc_data/vsc_data2
489 * and hope for different memory placement?
490 */
491 DBG("invalid vsc_overflow value: 0x%08x", vsc_overflow);
492 }
493 }
494
495 /*
496 * Emit conditional CP_INDIRECT_BRANCH based on VSC_STATE[p], ie. the IB
497 * is skipped for tiles that have no visible geometry.
498 */
499 static void
500 emit_conditional_ib(struct fd_batch *batch, const struct fd_tile *tile,
501 struct fd_ringbuffer *target)
502 {
503 struct fd_ringbuffer *ring = batch->gmem;
504
505 if (target->cur == target->start)
506 return;
507
508 emit_marker6(ring, 6);
509
510 unsigned count = fd_ringbuffer_cmd_count(target);
511
512 BEGIN_RING(ring, 5 + 4 * count); /* ensure conditional doesn't get split */
513
514 OUT_PKT7(ring, CP_REG_TEST, 1);
515 OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(REG_A6XX_VSC_STATE_REG(tile->p)) |
516 A6XX_CP_REG_TEST_0_BIT(tile->n) |
517 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
518
519 OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
520 OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
521 OUT_RING(ring, CP_COND_REG_EXEC_1_DWORDS(4 * count));
522
523 for (unsigned i = 0; i < count; i++) {
524 uint32_t dwords;
525 OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3);
526 dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
527 assert(dwords > 0);
528 OUT_RING(ring, dwords);
529 }
530
531 emit_marker6(ring, 6);
532 }
533
534 static void
535 set_scissor(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2)
536 {
537 OUT_REG(ring,
538 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x = x1, .y = y1),
539 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x = x2, .y = y2));
540
541 OUT_REG(ring,
542 A6XX_GRAS_RESOLVE_CNTL_1(.x = x1, .y = y1),
543 A6XX_GRAS_RESOLVE_CNTL_2(.x = x2, .y = y2));
544 }
545
546 static void
547 set_bin_size(struct fd_ringbuffer *ring, uint32_t w, uint32_t h, uint32_t flag)
548 {
549 OUT_REG(ring, A6XX_GRAS_BIN_CONTROL(.binw = w, .binh = h, .dword = flag));
550 OUT_REG(ring, A6XX_RB_BIN_CONTROL(.binw = w, .binh = h, .dword = flag));
551 /* no flag for RB_BIN_CONTROL2... */
552 OUT_REG(ring, A6XX_RB_BIN_CONTROL2(.binw = w, .binh = h));
553 }
554
555 static void
556 emit_binning_pass(struct fd_batch *batch)
557 {
558 struct fd_ringbuffer *ring = batch->gmem;
559 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
560 struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
561
562 debug_assert(!batch->tessellation);
563
564 set_scissor(ring, 0, 0, gmem->width - 1, gmem->height - 1);
565
566 emit_marker6(ring, 7);
567 OUT_PKT7(ring, CP_SET_MARKER, 1);
568 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
569 emit_marker6(ring, 7);
570
571 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
572 OUT_RING(ring, 0x1);
573
574 OUT_PKT7(ring, CP_SET_MODE, 1);
575 OUT_RING(ring, 0x1);
576
577 OUT_WFI5(ring);
578
579 OUT_REG(ring, A6XX_VFD_MODE_CNTL(.binning_pass = true));
580
581 update_vsc_pipe(batch);
582
583 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
584 OUT_RING(ring, fd6_ctx->magic.PC_UNKNOWN_9805);
585
586 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
587 OUT_RING(ring, fd6_ctx->magic.SP_UNKNOWN_A0F8);
588
589 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
590 OUT_RING(ring, UNK_2C);
591
592 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
593 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(0) |
594 A6XX_RB_WINDOW_OFFSET_Y(0));
595
596 OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
597 OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(0) |
598 A6XX_SP_TP_WINDOW_OFFSET_Y(0));
599
600 /* emit IB to binning drawcmds: */
601 fd_log(batch, "GMEM: START BINNING IB");
602 fd6_emit_ib(ring, batch->draw);
603 fd_log(batch, "GMEM: END BINNING IB");
604
605 fd_reset_wfi(batch);
606
607 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
608 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
609 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
610 CP_SET_DRAW_STATE__0_GROUP_ID(0));
611 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
612 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
613
614 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
615 OUT_RING(ring, UNK_2D);
616
617 fd6_cache_inv(batch, ring);
618 fd6_cache_flush(batch, ring);
619 fd_wfi(batch, ring);
620
621 OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
622
623 fd_log(batch, "START VSC OVERFLOW TEST");
624 emit_vsc_overflow_test(batch);
625 fd_log(batch, "END VSC OVERFLOW TEST");
626
627 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
628 OUT_RING(ring, 0x0);
629
630 OUT_PKT7(ring, CP_SET_MODE, 1);
631 OUT_RING(ring, 0x0);
632
633 OUT_WFI5(ring);
634
635 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
636 OUT_RING(ring, fd6_ctx->magic.RB_CCU_CNTL_gmem);
637 }
638
639 static void
640 emit_msaa(struct fd_ringbuffer *ring, unsigned nr)
641 {
642 enum a3xx_msaa_samples samples = fd_msaa_samples(nr);
643
644 OUT_PKT4(ring, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
645 OUT_RING(ring, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples));
646 OUT_RING(ring, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
647 COND(samples == MSAA_ONE, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
648
649 OUT_PKT4(ring, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
650 OUT_RING(ring, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples));
651 OUT_RING(ring, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples) |
652 COND(samples == MSAA_ONE, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE));
653
654 OUT_PKT4(ring, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
655 OUT_RING(ring, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
656 OUT_RING(ring, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
657 COND(samples == MSAA_ONE, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
658
659 OUT_PKT4(ring, REG_A6XX_RB_MSAA_CNTL, 1);
660 OUT_RING(ring, A6XX_RB_MSAA_CNTL_SAMPLES(samples));
661 }
662
663 static void prepare_tile_setup_ib(struct fd_batch *batch);
664 static void prepare_tile_fini_ib(struct fd_batch *batch);
665
666 /* before first tile */
667 static void
668 fd6_emit_tile_init(struct fd_batch *batch)
669 {
670 struct fd_context *ctx = batch->ctx;
671 struct fd_ringbuffer *ring = batch->gmem;
672 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
673 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
674
675 fd6_emit_restore(batch, ring);
676
677 fd6_emit_lrz_flush(ring);
678
679 if (batch->lrz_clear) {
680 fd_log(batch, "START LRZ CLEAR");
681 fd6_emit_ib(ring, batch->lrz_clear);
682 fd_log(batch, "END LRZ CLEAR");
683 }
684
685 fd6_cache_inv(batch, ring);
686
687 prepare_tile_setup_ib(batch);
688 prepare_tile_fini_ib(batch);
689
690 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
691 OUT_RING(ring, 0x0);
692
693 /* blob controls "local" in IB2, but I think that is not required */
694 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_LOCAL, 1);
695 OUT_RING(ring, 0x1);
696
697 fd_wfi(batch, ring);
698 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
699 OUT_RING(ring, fd6_context(ctx)->magic.RB_CCU_CNTL_gmem);
700
701 emit_zs(ring, pfb->zsbuf, batch->gmem_state);
702 emit_mrt(ring, pfb, batch->gmem_state);
703 emit_msaa(ring, pfb->samples);
704 patch_fb_read(batch);
705
706 if (use_hw_binning(batch)) {
707 /* enable stream-out during binning pass: */
708 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
709 OUT_RING(ring, 0);
710
711 set_bin_size(ring, gmem->bin_w, gmem->bin_h,
712 A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
713 update_render_cntl(batch, pfb, true);
714 emit_binning_pass(batch);
715
716 /* and disable stream-out for draw pass: */
717 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
718 OUT_RING(ring, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
719
720 /*
721 * NOTE: even if we detect VSC overflow and disable use of
722 * visibility stream in draw pass, it is still safe to execute
723 * the reset of these cmds:
724 */
725
726 // NOTE a618 not setting .USE_VIZ .. from a quick check on a630, it
727 // does not appear that this bit changes much (ie. it isn't actually
728 // .USE_VIZ like previous gens)
729 set_bin_size(ring, gmem->bin_w, gmem->bin_h,
730 A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
731
732 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
733 OUT_RING(ring, 0x0);
734
735 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
736 OUT_RING(ring, fd6_context(ctx)->magic.PC_UNKNOWN_9805);
737
738 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
739 OUT_RING(ring, fd6_context(ctx)->magic.SP_UNKNOWN_A0F8);
740
741 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
742 OUT_RING(ring, 0x1);
743 } else {
744 /* no binning pass, so enable stream-out for draw pass:: */
745 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
746 OUT_RING(ring, 0);
747
748 set_bin_size(ring, gmem->bin_w, gmem->bin_h, 0x6000000);
749 }
750
751 update_render_cntl(batch, pfb, false);
752 }
753
754 static void
755 set_window_offset(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1)
756 {
757 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
758 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(x1) |
759 A6XX_RB_WINDOW_OFFSET_Y(y1));
760
761 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET2, 1);
762 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET2_X(x1) |
763 A6XX_RB_WINDOW_OFFSET2_Y(y1));
764
765 OUT_PKT4(ring, REG_A6XX_SP_WINDOW_OFFSET, 1);
766 OUT_RING(ring, A6XX_SP_WINDOW_OFFSET_X(x1) |
767 A6XX_SP_WINDOW_OFFSET_Y(y1));
768
769 OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
770 OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(x1) |
771 A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
772 }
773
774 /* before mem2gmem */
775 static void
776 fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
777 {
778 struct fd_context *ctx = batch->ctx;
779 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
780 struct fd6_context *fd6_ctx = fd6_context(ctx);
781 struct fd_ringbuffer *ring = batch->gmem;
782
783 emit_marker6(ring, 7);
784 OUT_PKT7(ring, CP_SET_MARKER, 1);
785 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM));
786 emit_marker6(ring, 7);
787
788 uint32_t x1 = tile->xoff;
789 uint32_t y1 = tile->yoff;
790 uint32_t x2 = tile->xoff + tile->bin_w - 1;
791 uint32_t y2 = tile->yoff + tile->bin_h - 1;
792
793 set_scissor(ring, x1, y1, x2, y2);
794
795 if (use_hw_binning(batch)) {
796 const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[tile->p];
797
798 OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
799
800 OUT_PKT7(ring, CP_SET_MODE, 1);
801 OUT_RING(ring, 0x0);
802
803 OUT_PKT7(ring, CP_SET_BIN_DATA5, 7);
804 OUT_RING(ring, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe->w * pipe->h) |
805 CP_SET_BIN_DATA5_0_VSC_N(tile->n));
806 OUT_RELOC(ring, fd6_ctx->vsc_draw_strm, /* per-pipe draw-stream address */
807 (tile->p * fd6_ctx->vsc_draw_strm_pitch), 0, 0);
808 OUT_RELOC(ring, fd6_ctx->vsc_draw_strm, /* VSC_DRAW_STRM_ADDRESS + (p * 4) */
809 (tile->p * 4) + (32 * fd6_ctx->vsc_draw_strm_pitch), 0, 0);
810 OUT_RELOC(ring, fd6_ctx->vsc_prim_strm,
811 (tile->p * fd6_ctx->vsc_prim_strm_pitch), 0, 0);
812
813 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
814 OUT_RING(ring, 0x0);
815
816 set_window_offset(ring, x1, y1);
817
818 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
819 set_bin_size(ring, gmem->bin_w, gmem->bin_h, 0x6000000);
820
821 OUT_PKT7(ring, CP_SET_MODE, 1);
822 OUT_RING(ring, 0x0);
823 } else {
824 set_window_offset(ring, x1, y1);
825
826 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
827 OUT_RING(ring, 0x1);
828
829 OUT_PKT7(ring, CP_SET_MODE, 1);
830 OUT_RING(ring, 0x0);
831 }
832 }
833
834 static void
835 set_blit_scissor(struct fd_batch *batch, struct fd_ringbuffer *ring)
836 {
837 struct pipe_scissor_state blit_scissor = batch->max_scissor;
838
839 blit_scissor.minx = ROUND_DOWN_TO(blit_scissor.minx, 16);
840 blit_scissor.miny = ROUND_DOWN_TO(blit_scissor.miny, 4);
841 blit_scissor.maxx = ALIGN(blit_scissor.maxx, 16);
842 blit_scissor.maxy = ALIGN(blit_scissor.maxy, 4);
843
844 OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
845 OUT_RING(ring,
846 A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor.minx) |
847 A6XX_RB_BLIT_SCISSOR_TL_Y(blit_scissor.miny));
848 OUT_RING(ring,
849 A6XX_RB_BLIT_SCISSOR_BR_X(blit_scissor.maxx - 1) |
850 A6XX_RB_BLIT_SCISSOR_BR_Y(blit_scissor.maxy - 1));
851 }
852
853 static void
854 emit_blit(struct fd_batch *batch,
855 struct fd_ringbuffer *ring,
856 uint32_t base,
857 struct pipe_surface *psurf,
858 bool stencil)
859 {
860 struct fd_resource *rsc = fd_resource(psurf->texture);
861 enum pipe_format pfmt = psurf->format;
862 uint32_t offset;
863 bool ubwc_enabled;
864
865 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
866
867 /* separate stencil case: */
868 if (stencil) {
869 rsc = rsc->stencil;
870 pfmt = rsc->base.format;
871 }
872
873 offset = fd_resource_offset(rsc, psurf->u.tex.level,
874 psurf->u.tex.first_layer);
875 ubwc_enabled = fd_resource_ubwc_enabled(rsc, psurf->u.tex.level);
876
877 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
878
879 enum a6xx_format format = fd6_pipe2color(pfmt);
880 uint32_t stride = fd_resource_pitch(rsc, psurf->u.tex.level);
881 uint32_t size = fd_resource_slice(rsc, psurf->u.tex.level)->size0;
882 enum a3xx_color_swap swap = fd6_resource_swap(rsc, pfmt);
883 enum a3xx_msaa_samples samples =
884 fd_msaa_samples(rsc->base.nr_samples);
885 uint32_t tile_mode = fd_resource_tile_mode(&rsc->base, psurf->u.tex.level);
886
887 OUT_REG(ring,
888 A6XX_RB_BLIT_DST_INFO(.tile_mode = tile_mode, .samples = samples,
889 .color_format = format, .color_swap = swap, .flags = ubwc_enabled),
890 A6XX_RB_BLIT_DST(.bo = rsc->bo, .bo_offset = offset),
891 A6XX_RB_BLIT_DST_PITCH(.a6xx_rb_blit_dst_pitch = stride),
892 A6XX_RB_BLIT_DST_ARRAY_PITCH(.a6xx_rb_blit_dst_array_pitch = size));
893
894 OUT_REG(ring, A6XX_RB_BLIT_BASE_GMEM(.dword = base));
895
896 if (ubwc_enabled) {
897 OUT_PKT4(ring, REG_A6XX_RB_BLIT_FLAG_DST_LO, 3);
898 fd6_emit_flag_reference(ring, rsc,
899 psurf->u.tex.level, psurf->u.tex.first_layer);
900 }
901
902 fd6_emit_blit(batch, ring);
903 }
904
905 static void
906 emit_restore_blit(struct fd_batch *batch,
907 struct fd_ringbuffer *ring,
908 uint32_t base,
909 struct pipe_surface *psurf,
910 unsigned buffer)
911 {
912 bool stencil = (buffer == FD_BUFFER_STENCIL);
913
914 OUT_REG(ring, A6XX_RB_BLIT_INFO(
915 .gmem = true, .unk0 = true,
916 .depth = (buffer == FD_BUFFER_DEPTH),
917 .integer = util_format_is_pure_integer(psurf->format)));
918
919 emit_blit(batch, ring, base, psurf, stencil);
920 }
921
922 static void
923 emit_clears(struct fd_batch *batch, struct fd_ringbuffer *ring)
924 {
925 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
926 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
927 enum a3xx_msaa_samples samples = fd_msaa_samples(pfb->samples);
928
929 uint32_t buffers = batch->fast_cleared;
930
931 if (buffers & PIPE_CLEAR_COLOR) {
932
933 for (int i = 0; i < pfb->nr_cbufs; i++) {
934 union pipe_color_union *color = &batch->clear_color[i];
935 union util_color uc = {0};
936
937 if (!pfb->cbufs[i])
938 continue;
939
940 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
941 continue;
942
943 enum pipe_format pfmt = pfb->cbufs[i]->format;
944
945 // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
946 union pipe_color_union swapped;
947 switch (fd6_pipe2swap(pfmt)) {
948 case WZYX:
949 swapped.ui[0] = color->ui[0];
950 swapped.ui[1] = color->ui[1];
951 swapped.ui[2] = color->ui[2];
952 swapped.ui[3] = color->ui[3];
953 break;
954 case WXYZ:
955 swapped.ui[2] = color->ui[0];
956 swapped.ui[1] = color->ui[1];
957 swapped.ui[0] = color->ui[2];
958 swapped.ui[3] = color->ui[3];
959 break;
960 case ZYXW:
961 swapped.ui[3] = color->ui[0];
962 swapped.ui[0] = color->ui[1];
963 swapped.ui[1] = color->ui[2];
964 swapped.ui[2] = color->ui[3];
965 break;
966 case XYZW:
967 swapped.ui[3] = color->ui[0];
968 swapped.ui[2] = color->ui[1];
969 swapped.ui[1] = color->ui[2];
970 swapped.ui[0] = color->ui[3];
971 break;
972 }
973
974 util_pack_color_union(pfmt, &uc, &swapped);
975
976 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
977 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
978 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
979 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
980
981 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
982 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
983 A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
984
985 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
986 OUT_RING(ring, gmem->cbuf_base[i]);
987
988 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
989 OUT_RING(ring, 0);
990
991 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
992 OUT_RING(ring, uc.ui[0]);
993 OUT_RING(ring, uc.ui[1]);
994 OUT_RING(ring, uc.ui[2]);
995 OUT_RING(ring, uc.ui[3]);
996
997 fd6_emit_blit(batch, ring);
998 }
999 }
1000
1001 const bool has_depth = pfb->zsbuf;
1002 const bool has_separate_stencil =
1003 has_depth && fd_resource(pfb->zsbuf->texture)->stencil;
1004
1005 /* First clear depth or combined depth/stencil. */
1006 if ((has_depth && (buffers & PIPE_CLEAR_DEPTH)) ||
1007 (!has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL))) {
1008 enum pipe_format pfmt = pfb->zsbuf->format;
1009 uint32_t clear_value;
1010 uint32_t mask = 0;
1011
1012 if (has_separate_stencil) {
1013 pfmt = util_format_get_depth_only(pfb->zsbuf->format);
1014 clear_value = util_pack_z(pfmt, batch->clear_depth);
1015 } else {
1016 pfmt = pfb->zsbuf->format;
1017 clear_value = util_pack_z_stencil(pfmt, batch->clear_depth,
1018 batch->clear_stencil);
1019 }
1020
1021 if (buffers & PIPE_CLEAR_DEPTH)
1022 mask |= 0x1;
1023
1024 if (!has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL))
1025 mask |= 0x2;
1026
1027 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
1028 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
1029 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
1030 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
1031
1032 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
1033 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
1034 // XXX UNK0 for separate stencil ??
1035 A6XX_RB_BLIT_INFO_DEPTH |
1036 A6XX_RB_BLIT_INFO_CLEAR_MASK(mask));
1037
1038 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
1039 OUT_RING(ring, gmem->zsbuf_base[0]);
1040
1041 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
1042 OUT_RING(ring, 0);
1043
1044 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
1045 OUT_RING(ring, clear_value);
1046
1047 fd6_emit_blit(batch, ring);
1048 }
1049
1050 /* Then clear the separate stencil buffer in case of 32 bit depth
1051 * formats with separate stencil. */
1052 if (has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL)) {
1053 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
1054 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
1055 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
1056 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(FMT6_8_UINT));
1057
1058 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
1059 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
1060 //A6XX_RB_BLIT_INFO_UNK0 |
1061 A6XX_RB_BLIT_INFO_DEPTH |
1062 A6XX_RB_BLIT_INFO_CLEAR_MASK(0x1));
1063
1064 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
1065 OUT_RING(ring, gmem->zsbuf_base[1]);
1066
1067 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
1068 OUT_RING(ring, 0);
1069
1070 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
1071 OUT_RING(ring, batch->clear_stencil & 0xff);
1072
1073 fd6_emit_blit(batch, ring);
1074 }
1075 }
1076
1077 /*
1078 * transfer from system memory to gmem
1079 */
1080 static void
1081 emit_restore_blits(struct fd_batch *batch, struct fd_ringbuffer *ring)
1082 {
1083 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
1084 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1085
1086 if (batch->restore & FD_BUFFER_COLOR) {
1087 unsigned i;
1088 for (i = 0; i < pfb->nr_cbufs; i++) {
1089 if (!pfb->cbufs[i])
1090 continue;
1091 if (!(batch->restore & (PIPE_CLEAR_COLOR0 << i)))
1092 continue;
1093 emit_restore_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
1094 FD_BUFFER_COLOR);
1095 }
1096 }
1097
1098 if (batch->restore & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
1099 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
1100
1101 if (!rsc->stencil || (batch->restore & FD_BUFFER_DEPTH)) {
1102 emit_restore_blit(batch, ring, gmem->zsbuf_base[0], pfb->zsbuf,
1103 FD_BUFFER_DEPTH);
1104 }
1105 if (rsc->stencil && (batch->restore & FD_BUFFER_STENCIL)) {
1106 emit_restore_blit(batch, ring, gmem->zsbuf_base[1], pfb->zsbuf,
1107 FD_BUFFER_STENCIL);
1108 }
1109 }
1110 }
1111
1112 static void
1113 prepare_tile_setup_ib(struct fd_batch *batch)
1114 {
1115 batch->tile_setup = fd_submit_new_ringbuffer(batch->submit, 0x1000,
1116 FD_RINGBUFFER_STREAMING);
1117
1118 set_blit_scissor(batch, batch->tile_setup);
1119
1120 emit_restore_blits(batch, batch->tile_setup);
1121 emit_clears(batch, batch->tile_setup);
1122 }
1123
1124 /*
1125 * transfer from system memory to gmem
1126 */
1127 static void
1128 fd6_emit_tile_mem2gmem(struct fd_batch *batch, const struct fd_tile *tile)
1129 {
1130 }
1131
1132 /* before IB to rendering cmds: */
1133 static void
1134 fd6_emit_tile_renderprep(struct fd_batch *batch, const struct fd_tile *tile)
1135 {
1136 fd_log(batch, "TILE: START CLEAR/RESTORE");
1137 if (batch->fast_cleared || !use_hw_binning(batch)) {
1138 fd6_emit_ib(batch->gmem, batch->tile_setup);
1139 } else {
1140 emit_conditional_ib(batch, tile, batch->tile_setup);
1141 }
1142 fd_log(batch, "TILE: END CLEAR/RESTORE");
1143 }
1144
1145 static void
1146 emit_resolve_blit(struct fd_batch *batch,
1147 struct fd_ringbuffer *ring,
1148 uint32_t base,
1149 struct pipe_surface *psurf,
1150 unsigned buffer)
1151 {
1152 uint32_t info = 0;
1153 bool stencil = false;
1154
1155 if (!fd_resource(psurf->texture)->valid)
1156 return;
1157
1158 switch (buffer) {
1159 case FD_BUFFER_COLOR:
1160 break;
1161 case FD_BUFFER_STENCIL:
1162 info |= A6XX_RB_BLIT_INFO_UNK0;
1163 stencil = true;
1164 break;
1165 case FD_BUFFER_DEPTH:
1166 info |= A6XX_RB_BLIT_INFO_DEPTH;
1167 break;
1168 }
1169
1170 if (util_format_is_pure_integer(psurf->format))
1171 info |= A6XX_RB_BLIT_INFO_INTEGER;
1172
1173 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
1174 OUT_RING(ring, info);
1175
1176 emit_blit(batch, ring, base, psurf, stencil);
1177 }
1178
1179 /*
1180 * transfer from gmem to system memory (ie. normal RAM)
1181 */
1182
1183 static void
1184 prepare_tile_fini_ib(struct fd_batch *batch)
1185 {
1186 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
1187 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1188 struct fd_ringbuffer *ring;
1189
1190 batch->tile_fini = fd_submit_new_ringbuffer(batch->submit, 0x1000,
1191 FD_RINGBUFFER_STREAMING);
1192 ring = batch->tile_fini;
1193
1194 set_blit_scissor(batch, ring);
1195
1196 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
1197 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
1198
1199 if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH)) {
1200 emit_resolve_blit(batch, ring,
1201 gmem->zsbuf_base[0], pfb->zsbuf,
1202 FD_BUFFER_DEPTH);
1203 }
1204 if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL)) {
1205 emit_resolve_blit(batch, ring,
1206 gmem->zsbuf_base[1], pfb->zsbuf,
1207 FD_BUFFER_STENCIL);
1208 }
1209 }
1210
1211 if (batch->resolve & FD_BUFFER_COLOR) {
1212 unsigned i;
1213 for (i = 0; i < pfb->nr_cbufs; i++) {
1214 if (!pfb->cbufs[i])
1215 continue;
1216 if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
1217 continue;
1218 emit_resolve_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
1219 FD_BUFFER_COLOR);
1220 }
1221 }
1222 }
1223
1224 static void
1225 fd6_emit_tile(struct fd_batch *batch, const struct fd_tile *tile)
1226 {
1227 if (!use_hw_binning(batch)) {
1228 fd6_emit_ib(batch->gmem, batch->draw);
1229 } else {
1230 emit_conditional_ib(batch, tile, batch->draw);
1231 }
1232 }
1233
1234 static void
1235 fd6_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
1236 {
1237 struct fd_ringbuffer *ring = batch->gmem;
1238
1239 if (use_hw_binning(batch)) {
1240 OUT_PKT7(ring, CP_SET_MARKER, 1);
1241 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS));
1242 }
1243
1244 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
1245 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1246 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1247 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1248 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1249 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1250
1251 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_LOCAL, 1);
1252 OUT_RING(ring, 0x0);
1253
1254 emit_marker6(ring, 7);
1255 OUT_PKT7(ring, CP_SET_MARKER, 1);
1256 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE));
1257 emit_marker6(ring, 7);
1258
1259 fd_log(batch, "TILE: START RESOLVE");
1260 if (batch->fast_cleared || !use_hw_binning(batch)) {
1261 fd6_emit_ib(batch->gmem, batch->tile_fini);
1262 } else {
1263 emit_conditional_ib(batch, tile, batch->tile_fini);
1264 }
1265 fd_log(batch, "TILE: END RESOLVE");
1266 }
1267
1268 static void
1269 fd6_emit_tile_fini(struct fd_batch *batch)
1270 {
1271 struct fd_ringbuffer *ring = batch->gmem;
1272
1273 if (batch->epilogue)
1274 fd6_emit_ib(batch->gmem, batch->epilogue);
1275
1276 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
1277 OUT_RING(ring, A6XX_GRAS_LRZ_CNTL_ENABLE);
1278
1279 fd6_emit_lrz_flush(ring);
1280
1281 fd6_event_write(batch, ring, PC_CCU_RESOLVE_TS, true);
1282
1283 if (use_hw_binning(batch)) {
1284 check_vsc_overflow(batch->ctx);
1285 }
1286 }
1287
1288 static void
1289 emit_sysmem_clears(struct fd_batch *batch, struct fd_ringbuffer *ring)
1290 {
1291 struct fd_context *ctx = batch->ctx;
1292 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1293
1294 uint32_t buffers = batch->fast_cleared;
1295
1296 if (buffers & PIPE_CLEAR_COLOR) {
1297 for (int i = 0; i < pfb->nr_cbufs; i++) {
1298 union pipe_color_union *color = &batch->clear_color[i];
1299
1300 if (!pfb->cbufs[i])
1301 continue;
1302
1303 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
1304 continue;
1305
1306 fd6_clear_surface(ctx, ring,
1307 pfb->cbufs[i], pfb->width, pfb->height, color);
1308 }
1309 }
1310 if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
1311 union pipe_color_union value = {};
1312
1313 const bool has_depth = pfb->zsbuf;
1314 struct pipe_resource *separate_stencil =
1315 has_depth && fd_resource(pfb->zsbuf->texture)->stencil ?
1316 &fd_resource(pfb->zsbuf->texture)->stencil->base : NULL;
1317
1318 if ((has_depth && (buffers & PIPE_CLEAR_DEPTH)) ||
1319 (!separate_stencil && (buffers & PIPE_CLEAR_STENCIL))) {
1320 value.f[0] = batch->clear_depth;
1321 value.ui[1] = batch->clear_stencil;
1322 fd6_clear_surface(ctx, ring,
1323 pfb->zsbuf, pfb->width, pfb->height, &value);
1324 }
1325
1326 if (separate_stencil && (buffers & PIPE_CLEAR_STENCIL)) {
1327 value.ui[0] = batch->clear_stencil;
1328
1329 struct pipe_surface stencil_surf = *pfb->zsbuf;
1330 stencil_surf.texture = separate_stencil;
1331
1332 fd6_clear_surface(ctx, ring,
1333 &stencil_surf, pfb->width, pfb->height, &value);
1334 }
1335 }
1336
1337 fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
1338 }
1339
1340 static void
1341 setup_tess_buffers(struct fd_batch *batch, struct fd_ringbuffer *ring)
1342 {
1343 struct fd_context *ctx = batch->ctx;
1344
1345 batch->tessfactor_bo = fd_bo_new(ctx->screen->dev,
1346 batch->tessfactor_size,
1347 DRM_FREEDRENO_GEM_TYPE_KMEM, "tessfactor");
1348
1349 batch->tessparam_bo = fd_bo_new(ctx->screen->dev,
1350 batch->tessparam_size,
1351 DRM_FREEDRENO_GEM_TYPE_KMEM, "tessparam");
1352
1353 OUT_PKT4(ring, REG_A6XX_PC_TESSFACTOR_ADDR_LO, 2);
1354 OUT_RELOC(ring, batch->tessfactor_bo, 0, 0, 0);
1355
1356 batch->tess_addrs_constobj->cur = batch->tess_addrs_constobj->start;
1357 OUT_RELOC(batch->tess_addrs_constobj, batch->tessparam_bo, 0, 0, 0);
1358 OUT_RELOC(batch->tess_addrs_constobj, batch->tessfactor_bo, 0, 0, 0);
1359 }
1360
1361 static void
1362 fd6_emit_sysmem_prep(struct fd_batch *batch)
1363 {
1364 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1365 struct fd_ringbuffer *ring = batch->gmem;
1366
1367 fd6_emit_restore(batch, ring);
1368
1369 if (pfb->width > 0 && pfb->height > 0)
1370 set_scissor(ring, 0, 0, pfb->width - 1, pfb->height - 1);
1371 else
1372 set_scissor(ring, 0, 0, 0, 0);
1373
1374 set_window_offset(ring, 0, 0);
1375
1376 set_bin_size(ring, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1377
1378 emit_sysmem_clears(batch, ring);
1379
1380 fd6_emit_lrz_flush(ring);
1381
1382 if (batch->lrz_clear)
1383 fd6_emit_ib(ring, batch->lrz_clear);
1384
1385 emit_marker6(ring, 7);
1386 OUT_PKT7(ring, CP_SET_MARKER, 1);
1387 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
1388 emit_marker6(ring, 7);
1389
1390 if (batch->tessellation)
1391 setup_tess_buffers(batch, ring);
1392
1393 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1394 OUT_RING(ring, 0x0);
1395
1396 /* blob controls "local" in IB2, but I think that is not required */
1397 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_LOCAL, 1);
1398 OUT_RING(ring, 0x1);
1399
1400 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
1401 fd6_cache_inv(batch, ring);
1402
1403 fd_wfi(batch, ring);
1404 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
1405 OUT_RING(ring, fd6_context(batch->ctx)->magic.RB_CCU_CNTL_bypass);
1406
1407 /* enable stream-out, with sysmem there is only one pass: */
1408 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
1409 OUT_RING(ring, 0);
1410
1411 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
1412 OUT_RING(ring, 0x1);
1413
1414 emit_zs(ring, pfb->zsbuf, NULL);
1415 emit_mrt(ring, pfb, NULL);
1416 emit_msaa(ring, pfb->samples);
1417
1418 update_render_cntl(batch, pfb, false);
1419 }
1420
1421 static void
1422 fd6_emit_sysmem_fini(struct fd_batch *batch)
1423 {
1424 struct fd_ringbuffer *ring = batch->gmem;
1425
1426 if (batch->epilogue)
1427 fd6_emit_ib(batch->gmem, batch->epilogue);
1428
1429 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1430 OUT_RING(ring, 0x0);
1431
1432 fd6_emit_lrz_flush(ring);
1433
1434 fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
1435 }
1436
1437 void
1438 fd6_gmem_init(struct pipe_context *pctx)
1439 {
1440 struct fd_context *ctx = fd_context(pctx);
1441
1442 ctx->emit_tile_init = fd6_emit_tile_init;
1443 ctx->emit_tile_prep = fd6_emit_tile_prep;
1444 ctx->emit_tile_mem2gmem = fd6_emit_tile_mem2gmem;
1445 ctx->emit_tile_renderprep = fd6_emit_tile_renderprep;
1446 ctx->emit_tile = fd6_emit_tile;
1447 ctx->emit_tile_gmem2mem = fd6_emit_tile_gmem2mem;
1448 ctx->emit_tile_fini = fd6_emit_tile_fini;
1449 ctx->emit_sysmem_prep = fd6_emit_sysmem_prep;
1450 ctx->emit_sysmem_fini = fd6_emit_sysmem_fini;
1451 }