projects / mesa.git / blob
? search:


5ffcab6dbe7e51e2e5eb9a317257fb92cfda6771
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_gmem.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include <stdio.h>
29
30 #include "pipe/p_state.h"
31 #include "util/u_string.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/format/u_format.h"
35
36 #include "freedreno_draw.h"
37 #include "freedreno_state.h"
38 #include "freedreno_resource.h"
39
40 #include "fd6_blitter.h"
41 #include "fd6_gmem.h"
42 #include "fd6_context.h"
43 #include "fd6_draw.h"
44 #include "fd6_emit.h"
45 #include "fd6_program.h"
46 #include "fd6_format.h"
47 #include "fd6_resource.h"
48 #include "fd6_zsa.h"
49 #include "fd6_pack.h"
50
51 /**
52 * Emits the flags registers, suitable for RB_MRT_FLAG_BUFFER,
53 * RB_DEPTH_FLAG_BUFFER, SP_PS_2D_SRC_FLAGS, and RB_BLIT_FLAG_DST.
54 */
55 void
56 fd6_emit_flag_reference(struct fd_ringbuffer *ring, struct fd_resource *rsc,
57 int level, int layer)
58 {
59 if (fd_resource_ubwc_enabled(rsc, level)) {
60 OUT_RELOCW(ring, rsc->bo, fd_resource_ubwc_offset(rsc, level, layer), 0, 0);
61 OUT_RING(ring,
62 A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc->layout.ubwc_slices[level].pitch) |
63 A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->layout.ubwc_layer_size >> 2));
64 } else {
65 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
66 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
67 OUT_RING(ring, 0x00000000);
68 }
69 }
70
71 static void
72 emit_mrt(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb,
73 const struct fd_gmem_stateobj *gmem)
74 {
75 unsigned char mrt_comp[A6XX_MAX_RENDER_TARGETS] = {0};
76 unsigned srgb_cntl = 0;
77 unsigned i;
78
79 bool layered = false;
80 unsigned type = 0;
81
82 for (i = 0; i < pfb->nr_cbufs; i++) {
83 enum a6xx_format format = 0;
84 enum a3xx_color_swap swap = WZYX;
85 bool sint = false, uint = false;
86 struct fd_resource *rsc = NULL;
87 struct fdl_slice *slice = NULL;
88 uint32_t stride = 0;
89 uint32_t offset;
90 uint32_t tile_mode;
91
92 if (!pfb->cbufs[i])
93 continue;
94
95 mrt_comp[i] = 0xf;
96
97 struct pipe_surface *psurf = pfb->cbufs[i];
98 enum pipe_format pformat = psurf->format;
99 rsc = fd_resource(psurf->texture);
100 if (!rsc->bo)
101 continue;
102
103 uint32_t base = gmem ? gmem->cbuf_base[i] : 0;
104 slice = fd_resource_slice(rsc, psurf->u.tex.level);
105 format = fd6_pipe2color(pformat);
106 sint = util_format_is_pure_sint(pformat);
107 uint = util_format_is_pure_uint(pformat);
108
109 if (util_format_is_srgb(pformat))
110 srgb_cntl |= (1 << i);
111
112 offset = fd_resource_offset(rsc, psurf->u.tex.level,
113 psurf->u.tex.first_layer);
114
115 stride = slice->pitch * rsc->layout.cpp;
116 swap = fd6_resource_swap(rsc, pformat);
117
118 tile_mode = fd_resource_tile_mode(psurf->texture, psurf->u.tex.level);
119
120 if (psurf->u.tex.first_layer < psurf->u.tex.last_layer) {
121 layered = true;
122 if (psurf->texture->target == PIPE_TEXTURE_2D_ARRAY && psurf->texture->nr_samples > 0)
123 type = LAYER_MULTISAMPLE_ARRAY;
124 else if (psurf->texture->target == PIPE_TEXTURE_2D_ARRAY)
125 type = LAYER_2D_ARRAY;
126 else if (psurf->texture->target == PIPE_TEXTURE_CUBE)
127 type = LAYER_CUBEMAP;
128 else if (psurf->texture->target == PIPE_TEXTURE_3D)
129 type = LAYER_3D;
130 }
131
132 debug_assert((offset + slice->size0) <= fd_bo_size(rsc->bo));
133
134 OUT_REG(ring,
135 A6XX_RB_MRT_BUF_INFO(i,
136 .color_format = format,
137 .color_tile_mode = tile_mode,
138 .color_swap = swap),
139 A6XX_RB_MRT_PITCH(i, .a6xx_rb_mrt_pitch = stride),
140 A6XX_RB_MRT_ARRAY_PITCH(i, .a6xx_rb_mrt_array_pitch = slice->size0),
141 A6XX_RB_MRT_BASE(i, .bo = rsc->bo, .bo_offset = offset),
142 A6XX_RB_MRT_BASE_GMEM(i, .unknown = base));
143
144 OUT_REG(ring,
145 A6XX_SP_FS_MRT_REG(i, .color_format = format,
146 .color_sint = sint, .color_uint = uint));
147
148 OUT_PKT4(ring, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 3);
149 fd6_emit_flag_reference(ring, rsc,
150 psurf->u.tex.level, psurf->u.tex.first_layer);
151 }
152
153 OUT_REG(ring, A6XX_RB_SRGB_CNTL(.dword = srgb_cntl));
154 OUT_REG(ring, A6XX_SP_SRGB_CNTL(.dword = srgb_cntl));
155
156 OUT_REG(ring, A6XX_RB_RENDER_COMPONENTS(
157 .rt0 = mrt_comp[0],
158 .rt1 = mrt_comp[1],
159 .rt2 = mrt_comp[2],
160 .rt3 = mrt_comp[3],
161 .rt4 = mrt_comp[4],
162 .rt5 = mrt_comp[5],
163 .rt6 = mrt_comp[6],
164 .rt7 = mrt_comp[7]));
165
166 OUT_REG(ring, A6XX_SP_FS_RENDER_COMPONENTS(
167 .rt0 = mrt_comp[0],
168 .rt1 = mrt_comp[1],
169 .rt2 = mrt_comp[2],
170 .rt3 = mrt_comp[3],
171 .rt4 = mrt_comp[4],
172 .rt5 = mrt_comp[5],
173 .rt6 = mrt_comp[6],
174 .rt7 = mrt_comp[7]));
175
176 OUT_REG(ring, A6XX_GRAS_LAYER_CNTL(.layered = layered, .type = type));
177 }
178
179 static void
180 emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
181 const struct fd_gmem_stateobj *gmem)
182 {
183 if (zsbuf) {
184 struct fd_resource *rsc = fd_resource(zsbuf->texture);
185 enum a6xx_depth_format fmt = fd6_pipe2depth(zsbuf->format);
186 struct fdl_slice *slice = fd_resource_slice(rsc, 0);
187 uint32_t stride = slice->pitch * rsc->layout.cpp;
188 uint32_t size = slice->size0;
189 uint32_t base = gmem ? gmem->zsbuf_base[0] : 0;
190 uint32_t offset = fd_resource_offset(rsc, zsbuf->u.tex.level,
191 zsbuf->u.tex.first_layer);
192
193 OUT_REG(ring,
194 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = fmt),
195 A6XX_RB_DEPTH_BUFFER_PITCH(.a6xx_rb_depth_buffer_pitch = stride),
196 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(.a6xx_rb_depth_buffer_array_pitch = size),
197 A6XX_RB_DEPTH_BUFFER_BASE(.bo = rsc->bo, .bo_offset = offset),
198 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(.dword = base));
199
200 OUT_REG(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt));
201
202 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
203 fd6_emit_flag_reference(ring, rsc,
204 zsbuf->u.tex.level, zsbuf->u.tex.first_layer);
205
206 if (rsc->lrz) {
207 OUT_REG(ring,
208 A6XX_GRAS_LRZ_BUFFER_BASE(.bo = rsc->lrz),
209 A6XX_GRAS_LRZ_BUFFER_PITCH(.pitch = rsc->lrz_pitch),
210 // XXX a6xx seems to use a different buffer here.. not sure what for..
211 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO(0),
212 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI(0));
213 } else {
214 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
215 OUT_RING(ring, 0x00000000);
216 OUT_RING(ring, 0x00000000);
217 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
218 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
219 OUT_RING(ring, 0x00000000);
220 }
221
222 /* NOTE: blob emits GRAS_LRZ_CNTL plus GRAZ_LRZ_BUFFER_BASE
223 * plus this CP_EVENT_WRITE at the end in it's own IB..
224 */
225 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
226 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(UNK_25));
227
228 if (rsc->stencil) {
229 struct fdl_slice *slice = fd_resource_slice(rsc->stencil, 0);
230 stride = slice->pitch * rsc->stencil->layout.cpp;
231 size = slice->size0;
232 uint32_t base = gmem ? gmem->zsbuf_base[1] : 0;
233
234 OUT_REG(ring,
235 A6XX_RB_STENCIL_INFO(.separate_stencil = true),
236 A6XX_RB_STENCIL_BUFFER_PITCH(.a6xx_rb_stencil_buffer_pitch = stride),
237 A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(.a6xx_rb_stencil_buffer_array_pitch = size),
238 A6XX_RB_STENCIL_BUFFER_BASE(.bo = rsc->stencil->bo),
239 A6XX_RB_STENCIL_BUFFER_BASE_GMEM(.dword = base));
240 } else {
241 OUT_REG(ring, A6XX_RB_STENCIL_INFO(0));
242 }
243 } else {
244 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
245 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
246 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
247 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
248 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
249 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
250 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
251
252 OUT_REG(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE));
253
254 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
255 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
256 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
257 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
258 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
259 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
260
261 OUT_REG(ring, A6XX_RB_STENCIL_INFO(0));
262 }
263 }
264
265 static bool
266 use_hw_binning(struct fd_batch *batch)
267 {
268 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
269
270 // TODO figure out hw limits for binning
271
272 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) >= 2) &&
273 (batch->num_draws > 0);
274 }
275
276 static void
277 patch_fb_read(struct fd_batch *batch)
278 {
279 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
280
281 for (unsigned i = 0; i < fd_patch_num_elements(&batch->fb_read_patches); i++) {
282 struct fd_cs_patch *patch = fd_patch_element(&batch->fb_read_patches, i);
283 *patch->cs = patch->val | A6XX_TEX_CONST_2_PITCH(gmem->bin_w * gmem->cbuf_cpp[0]);
284 }
285 util_dynarray_clear(&batch->fb_read_patches);
286 }
287
288 static void
289 update_render_cntl(struct fd_batch *batch, struct pipe_framebuffer_state *pfb, bool binning)
290 {
291 struct fd_ringbuffer *ring = batch->gmem;
292 uint32_t cntl = 0;
293 bool depth_ubwc_enable = false;
294 uint32_t mrts_ubwc_enable = 0;
295 int i;
296
297 if (pfb->zsbuf) {
298 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
299 depth_ubwc_enable = fd_resource_ubwc_enabled(rsc, pfb->zsbuf->u.tex.level);
300 }
301
302 for (i = 0; i < pfb->nr_cbufs; i++) {
303 if (!pfb->cbufs[i])
304 continue;
305
306 struct pipe_surface *psurf = pfb->cbufs[i];
307 struct fd_resource *rsc = fd_resource(psurf->texture);
308 if (!rsc->bo)
309 continue;
310
311 if (fd_resource_ubwc_enabled(rsc, psurf->u.tex.level))
312 mrts_ubwc_enable |= 1 << i;
313 }
314
315 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
316 if (binning)
317 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
318
319 OUT_PKT7(ring, CP_REG_WRITE, 3);
320 OUT_RING(ring, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL));
321 OUT_RING(ring, REG_A6XX_RB_RENDER_CNTL);
322 OUT_RING(ring, cntl |
323 COND(depth_ubwc_enable, A6XX_RB_RENDER_CNTL_FLAG_DEPTH) |
324 A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable));
325 }
326
327 #define VSC_DATA_SIZE(pitch) ((pitch) * 32 + 0x100) /* extra size to store VSC_SIZE */
328 #define VSC_DATA2_SIZE(pitch) ((pitch) * 32)
329
330 static void
331 update_vsc_pipe(struct fd_batch *batch)
332 {
333 struct fd_context *ctx = batch->ctx;
334 struct fd6_context *fd6_ctx = fd6_context(ctx);
335 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
336 struct fd_ringbuffer *ring = batch->gmem;
337 int i;
338
339
340 if (!fd6_ctx->vsc_data) {
341 fd6_ctx->vsc_data = fd_bo_new(ctx->screen->dev,
342 VSC_DATA_SIZE(fd6_ctx->vsc_data_pitch),
343 DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_data");
344 }
345
346 if (!fd6_ctx->vsc_data2) {
347 fd6_ctx->vsc_data2 = fd_bo_new(ctx->screen->dev,
348 VSC_DATA2_SIZE(fd6_ctx->vsc_data2_pitch),
349 DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_data2");
350 }
351
352 OUT_REG(ring,
353 A6XX_VSC_BIN_SIZE(.width = gmem->bin_w, .height = gmem->bin_h),
354 A6XX_VSC_SIZE_ADDRESS(.bo = fd6_ctx->vsc_data, .bo_offset = 32 * fd6_ctx->vsc_data_pitch));
355
356 OUT_REG(ring, A6XX_VSC_BIN_COUNT(.nx = gmem->nbins_x,
357 .ny = gmem->nbins_y));
358
359 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
360 for (i = 0; i < 32; i++) {
361 const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[i];
362 OUT_RING(ring, A6XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
363 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
364 A6XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
365 A6XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
366 }
367
368 OUT_REG(ring,
369 A6XX_VSC_PIPE_DATA2_ADDRESS(.bo = fd6_ctx->vsc_data2),
370 A6XX_VSC_PIPE_DATA2_PITCH(.dword = fd6_ctx->vsc_data2_pitch),
371 A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(.dword = fd_bo_size(fd6_ctx->vsc_data2)));
372
373 OUT_REG(ring,
374 A6XX_VSC_PIPE_DATA_ADDRESS(.bo = fd6_ctx->vsc_data),
375 A6XX_VSC_PIPE_DATA_PITCH(.dword = fd6_ctx->vsc_data_pitch),
376 A6XX_VSC_PIPE_DATA_ARRAY_PITCH(.dword = fd_bo_size(fd6_ctx->vsc_data)));
377 }
378
379 /* TODO we probably have more than 8 scratch regs.. although the first
380 * 8 is what kernel dumps, and it is kinda useful to be able to see
381 * the value in kernel traces
382 */
383 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
384
385 /*
386 * If overflow is detected, either 0x1 (VSC_DATA overflow) or 0x3
387 * (VSC_DATA2 overflow) plus the size of the overflowed buffer is
388 * written to control->vsc_overflow. This allows the CPU to
389 * detect which buffer overflowed (and, since the current size is
390 * encoded as well, this protects against already-submitted but
391 * not executed batches from fooling the CPU into increasing the
392 * size again unnecessarily).
393 *
394 * To conditionally use VSC data in draw pass only if there is no
395 * overflow, we use a scratch reg (OVERFLOW_FLAG_REG) to hold 1
396 * if no overflow, or 0 in case of overflow. The value is inverted
397 * to make the CP_COND_REG_EXEC stuff easier.
398 */
399 static void
400 emit_vsc_overflow_test(struct fd_batch *batch)
401 {
402 struct fd_ringbuffer *ring = batch->gmem;
403 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
404 struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
405
406 debug_assert((fd6_ctx->vsc_data_pitch & 0x3) == 0);
407 debug_assert((fd6_ctx->vsc_data2_pitch & 0x3) == 0);
408
409 /* Clear vsc_scratch: */
410 OUT_PKT7(ring, CP_MEM_WRITE, 3);
411 OUT_RELOCW(ring, control_ptr(fd6_ctx, vsc_scratch));
412 OUT_RING(ring, 0x0);
413
414 /* Check for overflow, write vsc_scratch if detected: */
415 for (int i = 0; i < gmem->num_vsc_pipes; i++) {
416 OUT_PKT7(ring, CP_COND_WRITE5, 8);
417 OUT_RING(ring, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
418 CP_COND_WRITE5_0_WRITE_MEMORY);
419 OUT_RING(ring, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE_REG(i)));
420 OUT_RING(ring, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
421 OUT_RING(ring, CP_COND_WRITE5_3_REF(fd6_ctx->vsc_data_pitch));
422 OUT_RING(ring, CP_COND_WRITE5_4_MASK(~0));
423 OUT_RELOCW(ring, control_ptr(fd6_ctx, vsc_scratch)); /* WRITE_ADDR_LO/HI */
424 OUT_RING(ring, CP_COND_WRITE5_7_WRITE_DATA(1 + fd6_ctx->vsc_data_pitch));
425
426 OUT_PKT7(ring, CP_COND_WRITE5, 8);
427 OUT_RING(ring, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
428 CP_COND_WRITE5_0_WRITE_MEMORY);
429 OUT_RING(ring, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE2_REG(i)));
430 OUT_RING(ring, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
431 OUT_RING(ring, CP_COND_WRITE5_3_REF(fd6_ctx->vsc_data2_pitch));
432 OUT_RING(ring, CP_COND_WRITE5_4_MASK(~0));
433 OUT_RELOCW(ring, control_ptr(fd6_ctx, vsc_scratch)); /* WRITE_ADDR_LO/HI */
434 OUT_RING(ring, CP_COND_WRITE5_7_WRITE_DATA(3 + fd6_ctx->vsc_data2_pitch));
435 }
436
437 OUT_PKT7(ring, CP_WAIT_MEM_WRITES, 0);
438
439 OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
440
441 OUT_PKT7(ring, CP_MEM_TO_REG, 3);
442 OUT_RING(ring, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG) |
443 CP_MEM_TO_REG_0_CNT(0));
444 OUT_RELOC(ring, control_ptr(fd6_ctx, vsc_scratch)); /* SRC_LO/HI */
445
446 /*
447 * This is a bit awkward, we really want a way to invert the
448 * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
449 * execute cmds to use hwbinning when a bit is *not* set. This
450 * dance is to invert OVERFLOW_FLAG_REG
451 *
452 * A CP_NOP packet is used to skip executing the 'else' clause
453 * if (b0 set)..
454 */
455
456 BEGIN_RING(ring, 10); /* ensure if/else doesn't get split */
457
458 /* b0 will be set if VSC_DATA or VSC_DATA2 overflow: */
459 OUT_PKT7(ring, CP_REG_TEST, 1);
460 OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
461 A6XX_CP_REG_TEST_0_BIT(0) |
462 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
463
464 OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
465 OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
466 OUT_RING(ring, CP_COND_REG_EXEC_1_DWORDS(7));
467
468 /* if (b0 set) */ {
469 /*
470 * On overflow, mirror the value to control->vsc_overflow
471 * which CPU is checking to detect overflow (see
472 * check_vsc_overflow())
473 */
474 OUT_PKT7(ring, CP_REG_TO_MEM, 3);
475 OUT_RING(ring, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG) |
476 CP_REG_TO_MEM_0_CNT(1 - 1));
477 OUT_RELOCW(ring, control_ptr(fd6_ctx, vsc_overflow));
478
479 OUT_PKT4(ring, OVERFLOW_FLAG_REG, 1);
480 OUT_RING(ring, 0x0);
481
482 OUT_PKT7(ring, CP_NOP, 2); /* skip 'else' when 'if' is taken */
483 } /* else */ {
484 OUT_PKT4(ring, OVERFLOW_FLAG_REG, 1);
485 OUT_RING(ring, 0x1);
486 }
487 }
488
489 static void
490 check_vsc_overflow(struct fd_context *ctx)
491 {
492 struct fd6_context *fd6_ctx = fd6_context(ctx);
493 struct fd6_control *control = fd_bo_map(fd6_ctx->control_mem);
494 uint32_t vsc_overflow = control->vsc_overflow;
495
496 if (!vsc_overflow)
497 return;
498
499 /* clear overflow flag: */
500 control->vsc_overflow = 0;
501
502 unsigned buffer = vsc_overflow & 0x3;
503 unsigned size = vsc_overflow & ~0x3;
504
505 if (buffer == 0x1) {
506 /* VSC_PIPE_DATA overflow: */
507
508 if (size < fd6_ctx->vsc_data_pitch) {
509 /* we've already increased the size, this overflow is
510 * from a batch submitted before resize, but executed
511 * after
512 */
513 return;
514 }
515
516 fd_bo_del(fd6_ctx->vsc_data);
517 fd6_ctx->vsc_data = NULL;
518 fd6_ctx->vsc_data_pitch *= 2;
519
520 debug_printf("resized VSC_DATA_PITCH to: 0x%x\n", fd6_ctx->vsc_data_pitch);
521
522 } else if (buffer == 0x3) {
523 /* VSC_PIPE_DATA2 overflow: */
524
525 if (size < fd6_ctx->vsc_data2_pitch) {
526 /* we've already increased the size */
527 return;
528 }
529
530 fd_bo_del(fd6_ctx->vsc_data2);
531 fd6_ctx->vsc_data2 = NULL;
532 fd6_ctx->vsc_data2_pitch *= 2;
533
534 debug_printf("resized VSC_DATA2_PITCH to: 0x%x\n", fd6_ctx->vsc_data2_pitch);
535
536 } else {
537 /* NOTE: it's possible, for example, for overflow to corrupt the
538 * control page. I mostly just see this hit if I set initial VSC
539 * buffer size extremely small. Things still seem to recover,
540 * but maybe we should pre-emptively realloc vsc_data/vsc_data2
541 * and hope for different memory placement?
542 */
543 DBG("invalid vsc_overflow value: 0x%08x", vsc_overflow);
544 }
545 }
546
547 /*
548 * Emit conditional CP_INDIRECT_BRANCH based on VSC_STATE[p], ie. the IB
549 * is skipped for tiles that have no visible geometry.
550 */
551 static void
552 emit_conditional_ib(struct fd_batch *batch, const struct fd_tile *tile,
553 struct fd_ringbuffer *target)
554 {
555 struct fd_ringbuffer *ring = batch->gmem;
556
557 if (target->cur == target->start)
558 return;
559
560 emit_marker6(ring, 6);
561
562 unsigned count = fd_ringbuffer_cmd_count(target);
563
564 BEGIN_RING(ring, 5 + 4 * count); /* ensure conditional doesn't get split */
565
566 OUT_PKT7(ring, CP_REG_TEST, 1);
567 OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(REG_A6XX_VSC_STATE_REG(tile->p)) |
568 A6XX_CP_REG_TEST_0_BIT(tile->n) |
569 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
570
571 OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
572 OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
573 OUT_RING(ring, CP_COND_REG_EXEC_1_DWORDS(4 * count));
574
575 for (unsigned i = 0; i < count; i++) {
576 uint32_t dwords;
577 OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3);
578 dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
579 assert(dwords > 0);
580 OUT_RING(ring, dwords);
581 }
582
583 emit_marker6(ring, 6);
584 }
585
586 static void
587 set_scissor(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2)
588 {
589 OUT_REG(ring,
590 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x = x1, .y = y1),
591 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x = x2, .y = y2));
592
593 OUT_REG(ring,
594 A6XX_GRAS_RESOLVE_CNTL_1(.x = x1, .y = y1),
595 A6XX_GRAS_RESOLVE_CNTL_2(.x = x2, .y = y2));
596 }
597
598 static void
599 set_bin_size(struct fd_ringbuffer *ring, uint32_t w, uint32_t h, uint32_t flag)
600 {
601 OUT_REG(ring, A6XX_GRAS_BIN_CONTROL(.binw = w, .binh = h, .dword = flag));
602 OUT_REG(ring, A6XX_RB_BIN_CONTROL(.binw = w, .binh = h, .dword = flag));
603 /* no flag for RB_BIN_CONTROL2... */
604 OUT_REG(ring, A6XX_RB_BIN_CONTROL2(.binw = w, .binh = h));
605 }
606
607 static void
608 emit_binning_pass(struct fd_batch *batch)
609 {
610 struct fd_ringbuffer *ring = batch->gmem;
611 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
612 struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
613
614 uint32_t x1 = gmem->minx;
615 uint32_t y1 = gmem->miny;
616 uint32_t x2 = gmem->minx + gmem->width - 1;
617 uint32_t y2 = gmem->miny + gmem->height - 1;
618
619 debug_assert(!batch->tessellation);
620
621 set_scissor(ring, x1, y1, x2, y2);
622
623 emit_marker6(ring, 7);
624 OUT_PKT7(ring, CP_SET_MARKER, 1);
625 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
626 emit_marker6(ring, 7);
627
628 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
629 OUT_RING(ring, 0x1);
630
631 OUT_PKT7(ring, CP_SET_MODE, 1);
632 OUT_RING(ring, 0x1);
633
634 OUT_WFI5(ring);
635
636 OUT_REG(ring, A6XX_VFD_MODE_CNTL(.binning_pass = true));
637
638 update_vsc_pipe(batch);
639
640 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
641 OUT_RING(ring, fd6_ctx->magic.PC_UNKNOWN_9805);
642
643 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
644 OUT_RING(ring, fd6_ctx->magic.SP_UNKNOWN_A0F8);
645
646 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
647 OUT_RING(ring, UNK_2C);
648
649 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
650 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(0) |
651 A6XX_RB_WINDOW_OFFSET_Y(0));
652
653 OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
654 OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(0) |
655 A6XX_SP_TP_WINDOW_OFFSET_Y(0));
656
657 /* emit IB to binning drawcmds: */
658 fd6_emit_ib(ring, batch->draw);
659
660 fd_reset_wfi(batch);
661
662 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
663 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
664 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
665 CP_SET_DRAW_STATE__0_GROUP_ID(0));
666 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
667 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
668
669 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
670 OUT_RING(ring, UNK_2D);
671
672 fd6_cache_inv(batch, ring);
673 fd6_cache_flush(batch, ring);
674 fd_wfi(batch, ring);
675
676 OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
677
678 emit_vsc_overflow_test(batch);
679
680 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
681 OUT_RING(ring, 0x0);
682
683 OUT_PKT7(ring, CP_SET_MODE, 1);
684 OUT_RING(ring, 0x0);
685
686 OUT_WFI5(ring);
687
688 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
689 OUT_RING(ring, fd6_ctx->magic.RB_CCU_CNTL_gmem);
690 }
691
692 static void
693 emit_msaa(struct fd_ringbuffer *ring, unsigned nr)
694 {
695 enum a3xx_msaa_samples samples = fd_msaa_samples(nr);
696
697 OUT_PKT4(ring, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
698 OUT_RING(ring, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples));
699 OUT_RING(ring, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
700 COND(samples == MSAA_ONE, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
701
702 OUT_PKT4(ring, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
703 OUT_RING(ring, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples));
704 OUT_RING(ring, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples) |
705 COND(samples == MSAA_ONE, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE));
706
707 OUT_PKT4(ring, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
708 OUT_RING(ring, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
709 OUT_RING(ring, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
710 COND(samples == MSAA_ONE, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
711
712 OUT_PKT4(ring, REG_A6XX_RB_MSAA_CNTL, 1);
713 OUT_RING(ring, A6XX_RB_MSAA_CNTL_SAMPLES(samples));
714 }
715
716 static void prepare_tile_setup_ib(struct fd_batch *batch);
717 static void prepare_tile_fini_ib(struct fd_batch *batch);
718
719 /* before first tile */
720 static void
721 fd6_emit_tile_init(struct fd_batch *batch)
722 {
723 struct fd_context *ctx = batch->ctx;
724 struct fd_ringbuffer *ring = batch->gmem;
725 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
726 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
727
728 fd6_emit_restore(batch, ring);
729
730 fd6_emit_lrz_flush(ring);
731
732 if (batch->lrz_clear)
733 fd6_emit_ib(ring, batch->lrz_clear);
734
735 fd6_cache_inv(batch, ring);
736
737 prepare_tile_setup_ib(batch);
738 prepare_tile_fini_ib(batch);
739
740 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
741 OUT_RING(ring, 0x0);
742
743 fd_wfi(batch, ring);
744 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
745 OUT_RING(ring, fd6_context(ctx)->magic.RB_CCU_CNTL_gmem);
746
747 emit_zs(ring, pfb->zsbuf, batch->gmem_state);
748 emit_mrt(ring, pfb, batch->gmem_state);
749 emit_msaa(ring, pfb->samples);
750 patch_fb_read(batch);
751
752 if (use_hw_binning(batch)) {
753 /* enable stream-out during binning pass: */
754 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
755 OUT_RING(ring, 0);
756
757 set_bin_size(ring, gmem->bin_w, gmem->bin_h,
758 A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
759 update_render_cntl(batch, pfb, true);
760 emit_binning_pass(batch);
761
762 /* and disable stream-out for draw pass: */
763 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
764 OUT_RING(ring, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
765
766 /*
767 * NOTE: even if we detect VSC overflow and disable use of
768 * visibility stream in draw pass, it is still safe to execute
769 * the reset of these cmds:
770 */
771
772 // NOTE a618 not setting .USE_VIZ .. from a quick check on a630, it
773 // does not appear that this bit changes much (ie. it isn't actually
774 // .USE_VIZ like previous gens)
775 set_bin_size(ring, gmem->bin_w, gmem->bin_h,
776 A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
777
778 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
779 OUT_RING(ring, 0x0);
780
781 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
782 OUT_RING(ring, fd6_context(ctx)->magic.PC_UNKNOWN_9805);
783
784 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
785 OUT_RING(ring, fd6_context(ctx)->magic.SP_UNKNOWN_A0F8);
786
787 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
788 OUT_RING(ring, 0x1);
789 } else {
790 /* no binning pass, so enable stream-out for draw pass:: */
791 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
792 OUT_RING(ring, 0);
793
794 set_bin_size(ring, gmem->bin_w, gmem->bin_h, 0x6000000);
795 }
796
797 update_render_cntl(batch, pfb, false);
798 }
799
800 static void
801 set_window_offset(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1)
802 {
803 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
804 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(x1) |
805 A6XX_RB_WINDOW_OFFSET_Y(y1));
806
807 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET2, 1);
808 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET2_X(x1) |
809 A6XX_RB_WINDOW_OFFSET2_Y(y1));
810
811 OUT_PKT4(ring, REG_A6XX_SP_WINDOW_OFFSET, 1);
812 OUT_RING(ring, A6XX_SP_WINDOW_OFFSET_X(x1) |
813 A6XX_SP_WINDOW_OFFSET_Y(y1));
814
815 OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
816 OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(x1) |
817 A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
818 }
819
820 /* before mem2gmem */
821 static void
822 fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
823 {
824 struct fd_context *ctx = batch->ctx;
825 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
826 struct fd6_context *fd6_ctx = fd6_context(ctx);
827 struct fd_ringbuffer *ring = batch->gmem;
828
829 emit_marker6(ring, 7);
830 OUT_PKT7(ring, CP_SET_MARKER, 1);
831 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM));
832 emit_marker6(ring, 7);
833
834 uint32_t x1 = tile->xoff;
835 uint32_t y1 = tile->yoff;
836 uint32_t x2 = tile->xoff + tile->bin_w - 1;
837 uint32_t y2 = tile->yoff + tile->bin_h - 1;
838
839 set_scissor(ring, x1, y1, x2, y2);
840
841 if (use_hw_binning(batch)) {
842 const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[tile->p];
843
844 OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
845
846 OUT_PKT7(ring, CP_SET_MODE, 1);
847 OUT_RING(ring, 0x0);
848
849 /*
850 * Conditionally execute if no VSC overflow:
851 */
852
853 BEGIN_RING(ring, 18); /* ensure if/else doesn't get split */
854
855 OUT_PKT7(ring, CP_REG_TEST, 1);
856 OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
857 A6XX_CP_REG_TEST_0_BIT(0) |
858 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
859
860 OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
861 OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
862 OUT_RING(ring, CP_COND_REG_EXEC_1_DWORDS(11));
863
864 /* if (no overflow) */ {
865 OUT_PKT7(ring, CP_SET_BIN_DATA5, 7);
866 OUT_RING(ring, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe->w * pipe->h) |
867 CP_SET_BIN_DATA5_0_VSC_N(tile->n));
868 OUT_RELOC(ring, fd6_ctx->vsc_data, /* VSC_PIPE[p].DATA_ADDRESS */
869 (tile->p * fd6_ctx->vsc_data_pitch), 0, 0);
870 OUT_RELOC(ring, fd6_ctx->vsc_data, /* VSC_SIZE_ADDRESS + (p * 4) */
871 (tile->p * 4) + (32 * fd6_ctx->vsc_data_pitch), 0, 0);
872 OUT_RELOC(ring, fd6_ctx->vsc_data2,
873 (tile->p * fd6_ctx->vsc_data2_pitch), 0, 0);
874
875 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
876 OUT_RING(ring, 0x0);
877
878 /* use a NOP packet to skip over the 'else' side: */
879 OUT_PKT7(ring, CP_NOP, 2);
880 } /* else */ {
881 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
882 OUT_RING(ring, 0x1);
883 }
884
885 set_window_offset(ring, x1, y1);
886
887 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
888 set_bin_size(ring, gmem->bin_w, gmem->bin_h, 0x6000000);
889
890 OUT_PKT7(ring, CP_SET_MODE, 1);
891 OUT_RING(ring, 0x0);
892
893 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8804, 1);
894 OUT_RING(ring, 0x0);
895
896 OUT_PKT4(ring, REG_A6XX_SP_TP_UNKNOWN_B304, 1);
897 OUT_RING(ring, 0x0);
898
899 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_80A4, 1);
900 OUT_RING(ring, 0x0);
901 } else {
902 set_window_offset(ring, x1, y1);
903
904 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
905 OUT_RING(ring, 0x1);
906
907 OUT_PKT7(ring, CP_SET_MODE, 1);
908 OUT_RING(ring, 0x0);
909 }
910 }
911
912 static void
913 set_blit_scissor(struct fd_batch *batch, struct fd_ringbuffer *ring)
914 {
915 struct pipe_scissor_state blit_scissor;
916 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
917
918 blit_scissor.minx = 0;
919 blit_scissor.miny = 0;
920 blit_scissor.maxx = align(pfb->width, batch->ctx->screen->gmem_alignw);
921 blit_scissor.maxy = align(pfb->height, batch->ctx->screen->gmem_alignh);
922
923 OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
924 OUT_RING(ring,
925 A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor.minx) |
926 A6XX_RB_BLIT_SCISSOR_TL_Y(blit_scissor.miny));
927 OUT_RING(ring,
928 A6XX_RB_BLIT_SCISSOR_BR_X(blit_scissor.maxx - 1) |
929 A6XX_RB_BLIT_SCISSOR_BR_Y(blit_scissor.maxy - 1));
930 }
931
932 static void
933 emit_blit(struct fd_batch *batch,
934 struct fd_ringbuffer *ring,
935 uint32_t base,
936 struct pipe_surface *psurf,
937 bool stencil)
938 {
939 struct fdl_slice *slice;
940 struct fd_resource *rsc = fd_resource(psurf->texture);
941 enum pipe_format pfmt = psurf->format;
942 uint32_t offset;
943 bool ubwc_enabled;
944
945 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
946
947 /* separate stencil case: */
948 if (stencil) {
949 rsc = rsc->stencil;
950 pfmt = rsc->base.format;
951 }
952
953 slice = fd_resource_slice(rsc, psurf->u.tex.level);
954 offset = fd_resource_offset(rsc, psurf->u.tex.level,
955 psurf->u.tex.first_layer);
956 ubwc_enabled = fd_resource_ubwc_enabled(rsc, psurf->u.tex.level);
957
958 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
959
960 enum a6xx_format format = fd6_pipe2color(pfmt);
961 uint32_t stride = slice->pitch * rsc->layout.cpp;
962 uint32_t size = slice->size0;
963 enum a3xx_color_swap swap = fd6_resource_swap(rsc, pfmt);
964 enum a3xx_msaa_samples samples =
965 fd_msaa_samples(rsc->base.nr_samples);
966 uint32_t tile_mode = fd_resource_tile_mode(&rsc->base, psurf->u.tex.level);
967
968 OUT_REG(ring,
969 A6XX_RB_BLIT_DST_INFO(.tile_mode = tile_mode, .samples = samples,
970 .color_format = format, .color_swap = swap, .flags = ubwc_enabled),
971 A6XX_RB_BLIT_DST(.bo = rsc->bo, .bo_offset = offset),
972 A6XX_RB_BLIT_DST_PITCH(.a6xx_rb_blit_dst_pitch = stride),
973 A6XX_RB_BLIT_DST_ARRAY_PITCH(.a6xx_rb_blit_dst_array_pitch = size));
974
975 OUT_REG(ring, A6XX_RB_BLIT_BASE_GMEM(.dword = base));
976
977 if (ubwc_enabled) {
978 OUT_PKT4(ring, REG_A6XX_RB_BLIT_FLAG_DST_LO, 3);
979 fd6_emit_flag_reference(ring, rsc,
980 psurf->u.tex.level, psurf->u.tex.first_layer);
981 }
982
983 fd6_emit_blit(batch, ring);
984 }
985
986 static void
987 emit_restore_blit(struct fd_batch *batch,
988 struct fd_ringbuffer *ring,
989 uint32_t base,
990 struct pipe_surface *psurf,
991 unsigned buffer)
992 {
993 bool stencil = (buffer == FD_BUFFER_STENCIL);
994
995 OUT_REG(ring, A6XX_RB_BLIT_INFO(
996 .gmem = true, .unk0 = true,
997 .depth = (buffer == FD_BUFFER_DEPTH),
998 .integer = util_format_is_pure_integer(psurf->format)));
999
1000 emit_blit(batch, ring, base, psurf, stencil);
1001 }
1002
1003 static void
1004 emit_clears(struct fd_batch *batch, struct fd_ringbuffer *ring)
1005 {
1006 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1007 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
1008 enum a3xx_msaa_samples samples = fd_msaa_samples(pfb->samples);
1009
1010 uint32_t buffers = batch->fast_cleared;
1011
1012 if (buffers & PIPE_CLEAR_COLOR) {
1013
1014 for (int i = 0; i < pfb->nr_cbufs; i++) {
1015 union pipe_color_union *color = &batch->clear_color[i];
1016 union util_color uc = {0};
1017
1018 if (!pfb->cbufs[i])
1019 continue;
1020
1021 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
1022 continue;
1023
1024 enum pipe_format pfmt = pfb->cbufs[i]->format;
1025
1026 // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
1027 union pipe_color_union swapped;
1028 switch (fd6_pipe2swap(pfmt)) {
1029 case WZYX:
1030 swapped.ui[0] = color->ui[0];
1031 swapped.ui[1] = color->ui[1];
1032 swapped.ui[2] = color->ui[2];
1033 swapped.ui[3] = color->ui[3];
1034 break;
1035 case WXYZ:
1036 swapped.ui[2] = color->ui[0];
1037 swapped.ui[1] = color->ui[1];
1038 swapped.ui[0] = color->ui[2];
1039 swapped.ui[3] = color->ui[3];
1040 break;
1041 case ZYXW:
1042 swapped.ui[3] = color->ui[0];
1043 swapped.ui[0] = color->ui[1];
1044 swapped.ui[1] = color->ui[2];
1045 swapped.ui[2] = color->ui[3];
1046 break;
1047 case XYZW:
1048 swapped.ui[3] = color->ui[0];
1049 swapped.ui[2] = color->ui[1];
1050 swapped.ui[1] = color->ui[2];
1051 swapped.ui[0] = color->ui[3];
1052 break;
1053 }
1054
1055 util_pack_color_union(pfmt, &uc, &swapped);
1056
1057 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
1058 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
1059 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
1060 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
1061
1062 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
1063 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
1064 A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
1065
1066 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
1067 OUT_RING(ring, gmem->cbuf_base[i]);
1068
1069 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
1070 OUT_RING(ring, 0);
1071
1072 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
1073 OUT_RING(ring, uc.ui[0]);
1074 OUT_RING(ring, uc.ui[1]);
1075 OUT_RING(ring, uc.ui[2]);
1076 OUT_RING(ring, uc.ui[3]);
1077
1078 fd6_emit_blit(batch, ring);
1079 }
1080 }
1081
1082 const bool has_depth = pfb->zsbuf;
1083 const bool has_separate_stencil =
1084 has_depth && fd_resource(pfb->zsbuf->texture)->stencil;
1085
1086 /* First clear depth or combined depth/stencil. */
1087 if ((has_depth && (buffers & PIPE_CLEAR_DEPTH)) ||
1088 (!has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL))) {
1089 enum pipe_format pfmt = pfb->zsbuf->format;
1090 uint32_t clear_value;
1091 uint32_t mask = 0;
1092
1093 if (has_separate_stencil) {
1094 pfmt = util_format_get_depth_only(pfb->zsbuf->format);
1095 clear_value = util_pack_z(pfmt, batch->clear_depth);
1096 } else {
1097 pfmt = pfb->zsbuf->format;
1098 clear_value = util_pack_z_stencil(pfmt, batch->clear_depth,
1099 batch->clear_stencil);
1100 }
1101
1102 if (buffers & PIPE_CLEAR_DEPTH)
1103 mask |= 0x1;
1104
1105 if (!has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL))
1106 mask |= 0x2;
1107
1108 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
1109 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
1110 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
1111 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
1112
1113 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
1114 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
1115 // XXX UNK0 for separate stencil ??
1116 A6XX_RB_BLIT_INFO_DEPTH |
1117 A6XX_RB_BLIT_INFO_CLEAR_MASK(mask));
1118
1119 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
1120 OUT_RING(ring, gmem->zsbuf_base[0]);
1121
1122 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
1123 OUT_RING(ring, 0);
1124
1125 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
1126 OUT_RING(ring, clear_value);
1127
1128 fd6_emit_blit(batch, ring);
1129 }
1130
1131 /* Then clear the separate stencil buffer in case of 32 bit depth
1132 * formats with separate stencil. */
1133 if (has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL)) {
1134 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
1135 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
1136 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
1137 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(FMT6_8_UINT));
1138
1139 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
1140 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
1141 //A6XX_RB_BLIT_INFO_UNK0 |
1142 A6XX_RB_BLIT_INFO_DEPTH |
1143 A6XX_RB_BLIT_INFO_CLEAR_MASK(0x1));
1144
1145 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
1146 OUT_RING(ring, gmem->zsbuf_base[1]);
1147
1148 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
1149 OUT_RING(ring, 0);
1150
1151 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
1152 OUT_RING(ring, batch->clear_stencil & 0xff);
1153
1154 fd6_emit_blit(batch, ring);
1155 }
1156 }
1157
1158 /*
1159 * transfer from system memory to gmem
1160 */
1161 static void
1162 emit_restore_blits(struct fd_batch *batch, struct fd_ringbuffer *ring)
1163 {
1164 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
1165 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1166
1167 if (batch->restore & FD_BUFFER_COLOR) {
1168 unsigned i;
1169 for (i = 0; i < pfb->nr_cbufs; i++) {
1170 if (!pfb->cbufs[i])
1171 continue;
1172 if (!(batch->restore & (PIPE_CLEAR_COLOR0 << i)))
1173 continue;
1174 emit_restore_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
1175 FD_BUFFER_COLOR);
1176 }
1177 }
1178
1179 if (batch->restore & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
1180 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
1181
1182 if (!rsc->stencil || (batch->restore & FD_BUFFER_DEPTH)) {
1183 emit_restore_blit(batch, ring, gmem->zsbuf_base[0], pfb->zsbuf,
1184 FD_BUFFER_DEPTH);
1185 }
1186 if (rsc->stencil && (batch->restore & FD_BUFFER_STENCIL)) {
1187 emit_restore_blit(batch, ring, gmem->zsbuf_base[1], pfb->zsbuf,
1188 FD_BUFFER_STENCIL);
1189 }
1190 }
1191 }
1192
1193 static void
1194 prepare_tile_setup_ib(struct fd_batch *batch)
1195 {
1196 batch->tile_setup = fd_submit_new_ringbuffer(batch->submit, 0x1000,
1197 FD_RINGBUFFER_STREAMING);
1198
1199 set_blit_scissor(batch, batch->tile_setup);
1200
1201 emit_restore_blits(batch, batch->tile_setup);
1202 emit_clears(batch, batch->tile_setup);
1203 }
1204
1205 /*
1206 * transfer from system memory to gmem
1207 */
1208 static void
1209 fd6_emit_tile_mem2gmem(struct fd_batch *batch, const struct fd_tile *tile)
1210 {
1211 }
1212
1213 /* before IB to rendering cmds: */
1214 static void
1215 fd6_emit_tile_renderprep(struct fd_batch *batch, const struct fd_tile *tile)
1216 {
1217 if (batch->fast_cleared || !use_hw_binning(batch)) {
1218 fd6_emit_ib(batch->gmem, batch->tile_setup);
1219 } else {
1220 emit_conditional_ib(batch, tile, batch->tile_setup);
1221 }
1222 }
1223
1224 static void
1225 emit_resolve_blit(struct fd_batch *batch,
1226 struct fd_ringbuffer *ring,
1227 uint32_t base,
1228 struct pipe_surface *psurf,
1229 unsigned buffer)
1230 {
1231 uint32_t info = 0;
1232 bool stencil = false;
1233
1234 if (!fd_resource(psurf->texture)->valid)
1235 return;
1236
1237 switch (buffer) {
1238 case FD_BUFFER_COLOR:
1239 break;
1240 case FD_BUFFER_STENCIL:
1241 info |= A6XX_RB_BLIT_INFO_UNK0;
1242 stencil = true;
1243 break;
1244 case FD_BUFFER_DEPTH:
1245 info |= A6XX_RB_BLIT_INFO_DEPTH;
1246 break;
1247 }
1248
1249 if (util_format_is_pure_integer(psurf->format))
1250 info |= A6XX_RB_BLIT_INFO_INTEGER;
1251
1252 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
1253 OUT_RING(ring, info);
1254
1255 emit_blit(batch, ring, base, psurf, stencil);
1256 }
1257
1258 /*
1259 * transfer from gmem to system memory (ie. normal RAM)
1260 */
1261
1262 static void
1263 prepare_tile_fini_ib(struct fd_batch *batch)
1264 {
1265 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
1266 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1267 struct fd_ringbuffer *ring;
1268
1269 batch->tile_fini = fd_submit_new_ringbuffer(batch->submit, 0x1000,
1270 FD_RINGBUFFER_STREAMING);
1271 ring = batch->tile_fini;
1272
1273 set_blit_scissor(batch, ring);
1274
1275 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
1276 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
1277
1278 if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH)) {
1279 emit_resolve_blit(batch, ring,
1280 gmem->zsbuf_base[0], pfb->zsbuf,
1281 FD_BUFFER_DEPTH);
1282 }
1283 if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL)) {
1284 emit_resolve_blit(batch, ring,
1285 gmem->zsbuf_base[1], pfb->zsbuf,
1286 FD_BUFFER_STENCIL);
1287 }
1288 }
1289
1290 if (batch->resolve & FD_BUFFER_COLOR) {
1291 unsigned i;
1292 for (i = 0; i < pfb->nr_cbufs; i++) {
1293 if (!pfb->cbufs[i])
1294 continue;
1295 if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
1296 continue;
1297 emit_resolve_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
1298 FD_BUFFER_COLOR);
1299 }
1300 }
1301 }
1302
1303 static void
1304 fd6_emit_tile(struct fd_batch *batch, const struct fd_tile *tile)
1305 {
1306 if (!use_hw_binning(batch)) {
1307 fd6_emit_ib(batch->gmem, batch->draw);
1308 } else {
1309 emit_conditional_ib(batch, tile, batch->draw);
1310 }
1311 }
1312
1313 static void
1314 fd6_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
1315 {
1316 struct fd_ringbuffer *ring = batch->gmem;
1317
1318 if (use_hw_binning(batch)) {
1319 /* Conditionally execute if no VSC overflow: */
1320
1321 BEGIN_RING(ring, 7); /* ensure if/else doesn't get split */
1322
1323 OUT_PKT7(ring, CP_REG_TEST, 1);
1324 OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1325 A6XX_CP_REG_TEST_0_BIT(0) |
1326 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1327
1328 OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
1329 OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
1330 OUT_RING(ring, CP_COND_REG_EXEC_1_DWORDS(2));
1331
1332 /* if (no overflow) */ {
1333 OUT_PKT7(ring, CP_SET_MARKER, 1);
1334 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS));
1335 }
1336 }
1337
1338 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
1339 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1340 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1341 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1342 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1343 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1344
1345 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_LOCAL, 1);
1346 OUT_RING(ring, 0x0);
1347
1348 emit_marker6(ring, 7);
1349 OUT_PKT7(ring, CP_SET_MARKER, 1);
1350 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE));
1351 emit_marker6(ring, 7);
1352
1353 if (batch->fast_cleared || !use_hw_binning(batch)) {
1354 fd6_emit_ib(batch->gmem, batch->tile_fini);
1355 } else {
1356 emit_conditional_ib(batch, tile, batch->tile_fini);
1357 }
1358
1359 OUT_PKT7(ring, CP_SET_MARKER, 1);
1360 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD));
1361 }
1362
1363 static void
1364 fd6_emit_tile_fini(struct fd_batch *batch)
1365 {
1366 struct fd_ringbuffer *ring = batch->gmem;
1367
1368 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
1369 OUT_RING(ring, A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_UNK3);
1370
1371 fd6_emit_lrz_flush(ring);
1372
1373 fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
1374
1375 if (use_hw_binning(batch)) {
1376 check_vsc_overflow(batch->ctx);
1377 }
1378 }
1379
1380 static void
1381 emit_sysmem_clears(struct fd_batch *batch, struct fd_ringbuffer *ring)
1382 {
1383 struct fd_context *ctx = batch->ctx;
1384 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1385
1386 uint32_t buffers = batch->fast_cleared;
1387
1388 if (buffers & PIPE_CLEAR_COLOR) {
1389 for (int i = 0; i < pfb->nr_cbufs; i++) {
1390 union pipe_color_union *color = &batch->clear_color[i];
1391
1392 if (!pfb->cbufs[i])
1393 continue;
1394
1395 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
1396 continue;
1397
1398 fd6_clear_surface(ctx, ring,
1399 pfb->cbufs[i], pfb->width, pfb->height, color);
1400 }
1401 }
1402 if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
1403 union pipe_color_union value = {};
1404
1405 const bool has_depth = pfb->zsbuf;
1406 struct pipe_resource *separate_stencil =
1407 has_depth && fd_resource(pfb->zsbuf->texture)->stencil ?
1408 &fd_resource(pfb->zsbuf->texture)->stencil->base : NULL;
1409
1410 if ((has_depth && (buffers & PIPE_CLEAR_DEPTH)) ||
1411 (!separate_stencil && (buffers & PIPE_CLEAR_STENCIL))) {
1412 value.f[0] = batch->clear_depth;
1413 value.ui[1] = batch->clear_stencil;
1414 fd6_clear_surface(ctx, ring,
1415 pfb->zsbuf, pfb->width, pfb->height, &value);
1416 }
1417
1418 if (separate_stencil && (buffers & PIPE_CLEAR_STENCIL)) {
1419 value.ui[0] = batch->clear_stencil;
1420
1421 struct pipe_surface stencil_surf = *pfb->zsbuf;
1422 stencil_surf.texture = separate_stencil;
1423
1424 fd6_clear_surface(ctx, ring,
1425 &stencil_surf, pfb->width, pfb->height, &value);
1426 }
1427 }
1428
1429 fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
1430 }
1431
1432 static void
1433 setup_tess_buffers(struct fd_batch *batch, struct fd_ringbuffer *ring)
1434 {
1435 struct fd_context *ctx = batch->ctx;
1436
1437 batch->tessfactor_bo = fd_bo_new(ctx->screen->dev,
1438 batch->tessfactor_size,
1439 DRM_FREEDRENO_GEM_TYPE_KMEM, "tessfactor");
1440
1441 batch->tessparam_bo = fd_bo_new(ctx->screen->dev,
1442 batch->tessparam_size,
1443 DRM_FREEDRENO_GEM_TYPE_KMEM, "tessparam");
1444
1445 OUT_PKT4(ring, REG_A6XX_PC_TESSFACTOR_ADDR_LO, 2);
1446 OUT_RELOCW(ring, batch->tessfactor_bo, 0, 0, 0);
1447
1448 batch->tess_addrs_constobj->cur = batch->tess_addrs_constobj->start;
1449 OUT_RELOCW(batch->tess_addrs_constobj, batch->tessparam_bo, 0, 0, 0);
1450 OUT_RELOCW(batch->tess_addrs_constobj, batch->tessfactor_bo, 0, 0, 0);
1451 }
1452
1453 static void
1454 fd6_emit_sysmem_prep(struct fd_batch *batch)
1455 {
1456 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1457 struct fd_ringbuffer *ring = batch->gmem;
1458
1459 fd6_emit_restore(batch, ring);
1460
1461 if (pfb->width > 0 && pfb->height > 0)
1462 set_scissor(ring, 0, 0, pfb->width - 1, pfb->height - 1);
1463 else
1464 set_scissor(ring, 0, 0, 0, 0);
1465
1466 set_window_offset(ring, 0, 0);
1467
1468 set_bin_size(ring, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1469
1470 emit_sysmem_clears(batch, ring);
1471
1472 fd6_emit_lrz_flush(ring);
1473
1474 if (batch->lrz_clear)
1475 fd6_emit_ib(ring, batch->lrz_clear);
1476
1477 emit_marker6(ring, 7);
1478 OUT_PKT7(ring, CP_SET_MARKER, 1);
1479 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
1480 emit_marker6(ring, 7);
1481
1482 if (batch->tessellation)
1483 setup_tess_buffers(batch, ring);
1484
1485 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1486 OUT_RING(ring, 0x0);
1487
1488 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
1489 fd6_cache_inv(batch, ring);
1490
1491 fd_wfi(batch, ring);
1492 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
1493 OUT_RING(ring, fd6_context(batch->ctx)->magic.RB_CCU_CNTL_bypass);
1494
1495 /* enable stream-out, with sysmem there is only one pass: */
1496 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
1497 OUT_RING(ring, 0);
1498
1499 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
1500 OUT_RING(ring, 0x1);
1501
1502 emit_zs(ring, pfb->zsbuf, NULL);
1503 emit_mrt(ring, pfb, NULL);
1504 emit_msaa(ring, pfb->samples);
1505
1506 update_render_cntl(batch, pfb, false);
1507 }
1508
1509 static void
1510 fd6_emit_sysmem_fini(struct fd_batch *batch)
1511 {
1512 struct fd_ringbuffer *ring = batch->gmem;
1513
1514 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1515 OUT_RING(ring, 0x0);
1516
1517 fd6_emit_lrz_flush(ring);
1518
1519 fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
1520 }
1521
1522 void
1523 fd6_gmem_init(struct pipe_context *pctx)
1524 {
1525 struct fd_context *ctx = fd_context(pctx);
1526
1527 ctx->emit_tile_init = fd6_emit_tile_init;
1528 ctx->emit_tile_prep = fd6_emit_tile_prep;
1529 ctx->emit_tile_mem2gmem = fd6_emit_tile_mem2gmem;
1530 ctx->emit_tile_renderprep = fd6_emit_tile_renderprep;
1531 ctx->emit_tile = fd6_emit_tile;
1532 ctx->emit_tile_gmem2mem = fd6_emit_tile_gmem2mem;
1533 ctx->emit_tile_fini = fd6_emit_tile_fini;
1534 ctx->emit_sysmem_prep = fd6_emit_sysmem_prep;
1535 ctx->emit_sysmem_fini = fd6_emit_sysmem_fini;
1536 }