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26be370833d7d89d5eaab4ce64a564a333be42db
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_program.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/u_format.h"
33 #include "util/bitset.h"
34
35 #include "freedreno_program.h"
36
37 #include "fd6_program.h"
38 #include "fd6_emit.h"
39 #include "fd6_texture.h"
40 #include "fd6_format.h"
41
42 void
43 fd6_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
44 {
45 enum a6xx_state_block sb = fd6_stage2shadersb(so->type);
46
47 OUT_PKT7(ring, fd6_stage2opcode(so->type), 3);
48 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
49 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
50 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
51 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
52 CP_LOAD_STATE6_0_NUM_UNIT(so->instrlen));
53 OUT_RELOCD(ring, so->bo, 0, 0, 0);
54 }
55
56 /* Add any missing varyings needed for stream-out. Otherwise varyings not
57 * used by fragment shader will be stripped out.
58 */
59 static void
60 link_stream_out(struct ir3_shader_linkage *l, const struct ir3_shader_variant *v)
61 {
62 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
63
64 /*
65 * First, any stream-out varyings not already in linkage map (ie. also
66 * consumed by frag shader) need to be added:
67 */
68 for (unsigned i = 0; i < strmout->num_outputs; i++) {
69 const struct ir3_stream_output *out = &strmout->output[i];
70 unsigned k = out->register_index;
71 unsigned compmask =
72 (1 << (out->num_components + out->start_component)) - 1;
73 unsigned idx, nextloc = 0;
74
75 /* psize/pos need to be the last entries in linkage map, and will
76 * get added link_stream_out, so skip over them:
77 */
78 if ((v->outputs[k].slot == VARYING_SLOT_PSIZ) ||
79 (v->outputs[k].slot == VARYING_SLOT_POS))
80 continue;
81
82 for (idx = 0; idx < l->cnt; idx++) {
83 if (l->var[idx].regid == v->outputs[k].regid)
84 break;
85 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
86 }
87
88 /* add if not already in linkage map: */
89 if (idx == l->cnt)
90 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
91
92 /* expand component-mask if needed, ie streaming out all components
93 * but frag shader doesn't consume all components:
94 */
95 if (compmask & ~l->var[idx].compmask) {
96 l->var[idx].compmask |= compmask;
97 l->max_loc = MAX2(l->max_loc,
98 l->var[idx].loc + util_last_bit(l->var[idx].compmask));
99 }
100 }
101 }
102
103 static void
104 setup_stream_out(struct fd6_program_state *state, const struct ir3_shader_variant *v,
105 struct ir3_shader_linkage *l)
106 {
107 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
108 struct fd6_streamout_state *tf = &state->tf;
109
110 memset(tf, 0, sizeof(*tf));
111
112 tf->prog_count = align(l->max_loc, 2) / 2;
113
114 debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
115
116 for (unsigned i = 0; i < strmout->num_outputs; i++) {
117 const struct ir3_stream_output *out = &strmout->output[i];
118 unsigned k = out->register_index;
119 unsigned idx;
120
121 tf->ncomp[out->output_buffer] += out->num_components;
122
123 /* linkage map sorted by order frag shader wants things, so
124 * a bit less ideal here..
125 */
126 for (idx = 0; idx < l->cnt; idx++)
127 if (l->var[idx].regid == v->outputs[k].regid)
128 break;
129
130 debug_assert(idx < l->cnt);
131
132 for (unsigned j = 0; j < out->num_components; j++) {
133 unsigned c = j + out->start_component;
134 unsigned loc = l->var[idx].loc + c;
135 unsigned off = j + out->dst_offset; /* in dwords */
136
137 if (loc & 1) {
138 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
139 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
140 A6XX_VPC_SO_PROG_B_OFF(off * 4);
141 } else {
142 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
143 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
144 A6XX_VPC_SO_PROG_A_OFF(off * 4);
145 }
146 }
147 }
148
149 tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
150 COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
151 COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
152 COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
153 COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
154 }
155
156 static void
157 setup_config_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *state)
158 {
159 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
160 OUT_RING(ring, 0xff); /* XXX */
161
162 debug_assert(state->vs->constlen >= state->bs->constlen);
163
164 OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
165 OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(state->vs->constlen, 4)) |
166 A6XX_HLSQ_VS_CNTL_ENABLED);
167 OUT_RING(ring, A6XX_HLSQ_HS_CNTL_CONSTLEN(0));
168 OUT_RING(ring, A6XX_HLSQ_DS_CNTL_CONSTLEN(0));
169 OUT_RING(ring, A6XX_HLSQ_GS_CNTL_CONSTLEN(0));
170
171 OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL, 1);
172 OUT_RING(ring, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(state->fs->constlen, 4)) |
173 A6XX_HLSQ_FS_CNTL_ENABLED);
174
175 OUT_PKT4(ring, REG_A6XX_SP_VS_CONFIG, 1);
176 OUT_RING(ring, COND(state->vs, A6XX_SP_VS_CONFIG_ENABLED) |
177 A6XX_SP_VS_CONFIG_NIBO(state->vs->image_mapping.num_ibo) |
178 A6XX_SP_VS_CONFIG_NTEX(state->vs->num_samp) |
179 A6XX_SP_VS_CONFIG_NSAMP(state->vs->num_samp));
180
181 OUT_PKT4(ring, REG_A6XX_SP_FS_CONFIG, 1);
182 OUT_RING(ring, COND(state->fs, A6XX_SP_FS_CONFIG_ENABLED) |
183 A6XX_SP_FS_CONFIG_NIBO(state->fs->image_mapping.num_ibo) |
184 A6XX_SP_FS_CONFIG_NTEX(state->fs->num_samp) |
185 A6XX_SP_FS_CONFIG_NSAMP(state->fs->num_samp));
186
187 OUT_PKT4(ring, REG_A6XX_SP_HS_CONFIG, 1);
188 OUT_RING(ring, COND(false, A6XX_SP_HS_CONFIG_ENABLED));
189
190 OUT_PKT4(ring, REG_A6XX_SP_DS_CONFIG, 1);
191 OUT_RING(ring, COND(false, A6XX_SP_DS_CONFIG_ENABLED));
192
193 OUT_PKT4(ring, REG_A6XX_SP_GS_CONFIG, 1);
194 OUT_RING(ring, COND(false, A6XX_SP_GS_CONFIG_ENABLED));
195
196 OUT_PKT4(ring, REG_A6XX_SP_IBO_COUNT, 1);
197 OUT_RING(ring, state->fs->image_mapping.num_ibo);
198 }
199
200 #define VALIDREG(r) ((r) != regid(63,0))
201 #define CONDREG(r, val) COND(VALIDREG(r), (val))
202
203 static inline uint32_t
204 next_regid(uint32_t reg, uint32_t increment)
205 {
206 if (VALIDREG(reg))
207 return reg + increment;
208 else
209 return regid(63,0);
210 }
211
212 static void
213 setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
214 struct fd6_program_state *state, const struct ir3_shader_key *key,
215 bool binning_pass)
216 {
217 uint32_t pos_regid, psize_regid, color_regid[8], posz_regid;
218 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
219 uint32_t smask_in_regid, smask_regid;
220 uint32_t vertex_regid, instance_regid;
221 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
222 enum a3xx_threadsize fssz;
223 uint8_t psize_loc = ~0, pos_loc = ~0;
224 int i, j;
225
226 static const struct ir3_shader_variant dummy_fs = {0};
227 const struct ir3_shader_variant *vs = binning_pass ? state->bs : state->vs;
228 const struct ir3_shader_variant *fs = binning_pass ? &dummy_fs : state->fs;
229
230 bool sample_shading = fs->per_samp | key->sample_shading;
231
232 fssz = FOUR_QUADS;
233
234 pos_regid = ir3_find_output_regid(vs, VARYING_SLOT_POS);
235 psize_regid = ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
236 vertex_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
237 instance_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
238
239 if (fs->color0_mrt) {
240 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
241 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
242 ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
243 } else {
244 color_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0);
245 color_regid[1] = ir3_find_output_regid(fs, FRAG_RESULT_DATA1);
246 color_regid[2] = ir3_find_output_regid(fs, FRAG_RESULT_DATA2);
247 color_regid[3] = ir3_find_output_regid(fs, FRAG_RESULT_DATA3);
248 color_regid[4] = ir3_find_output_regid(fs, FRAG_RESULT_DATA4);
249 color_regid[5] = ir3_find_output_regid(fs, FRAG_RESULT_DATA5);
250 color_regid[6] = ir3_find_output_regid(fs, FRAG_RESULT_DATA6);
251 color_regid[7] = ir3_find_output_regid(fs, FRAG_RESULT_DATA7);
252 }
253
254 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
255 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
256 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
257 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
258 zwcoord_regid = next_regid(coord_regid, 2);
259 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PIXEL);
260 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_SAMPLE);
261 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_CENTROID);
262 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_SIZE);
263 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
264 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
265
266 /* we can't write gl_SampleMask for !msaa.. if b0 is zero then we
267 * end up masking the single sample!!
268 */
269 if (!key->msaa)
270 smask_regid = regid(63, 0);
271
272 /* we could probably divide this up into things that need to be
273 * emitted if frag-prog is dirty vs if vert-prog is dirty..
274 */
275
276 OUT_PKT4(ring, REG_A6XX_SP_VS_INSTRLEN, 1);
277 OUT_RING(ring, vs->instrlen); /* SP_VS_INSTRLEN */
278
279 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
280 OUT_RING(ring, 0);
281
282 OUT_PKT4(ring, REG_A6XX_SP_HS_INSTRLEN, 1);
283 OUT_RING(ring, 0); /* SP_HS_INSTRLEN */
284
285 OUT_PKT4(ring, REG_A6XX_SP_DS_INSTRLEN, 1);
286 OUT_RING(ring, 0); /* SP_DS_INSTRLEN */
287
288 OUT_PKT4(ring, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
289 OUT_RING(ring, 0);
290
291 OUT_PKT4(ring, REG_A6XX_SP_GS_INSTRLEN, 1);
292 OUT_RING(ring, 0); /* SP_GS_INSTRLEN */
293
294 /* I believe this is related to pre-dispatch texture fetch.. we probably
295 * should't turn it on by accident:
296 */
297 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A99E, 1);
298 OUT_RING(ring, 0x0);
299
300 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A9A8, 1);
301 OUT_RING(ring, 0);
302
303 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_AB00, 1);
304 OUT_RING(ring, 0x5);
305
306 OUT_PKT4(ring, REG_A6XX_SP_FS_INSTRLEN, 1);
307 OUT_RING(ring, fs->instrlen); /* SP_FS_INSTRLEN */
308
309 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL0, 1);
310 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
311 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
312 0xfc000000);
313
314 OUT_PKT4(ring, REG_A6XX_SP_VS_CTRL_REG0, 1);
315 OUT_RING(ring, A6XX_SP_VS_CTRL_REG0_THREADSIZE(fssz) |
316 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
317 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
318 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack) |
319 COND(vs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE));
320
321 struct ir3_shader_linkage l = {0};
322 ir3_link_shaders(&l, vs, fs);
323
324 if ((vs->shader->stream_output.num_outputs > 0) && !binning_pass)
325 link_stream_out(&l, vs);
326
327 BITSET_DECLARE(varbs, 128) = {0};
328 uint32_t *varmask = (uint32_t *)varbs;
329
330 for (i = 0; i < l.cnt; i++)
331 for (j = 0; j < util_last_bit(l.var[i].compmask); j++)
332 BITSET_SET(varbs, l.var[i].loc + j);
333
334 OUT_PKT4(ring, REG_A6XX_VPC_VAR_DISABLE(0), 4);
335 OUT_RING(ring, ~varmask[0]); /* VPC_VAR[0].DISABLE */
336 OUT_RING(ring, ~varmask[1]); /* VPC_VAR[1].DISABLE */
337 OUT_RING(ring, ~varmask[2]); /* VPC_VAR[2].DISABLE */
338 OUT_RING(ring, ~varmask[3]); /* VPC_VAR[3].DISABLE */
339
340 /* a6xx appends pos/psize to end of the linkage map: */
341 if (VALIDREG(pos_regid)) {
342 pos_loc = l.max_loc;
343 ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
344 }
345
346 if (VALIDREG(psize_regid)) {
347 psize_loc = l.max_loc;
348 ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
349 }
350
351 if ((vs->shader->stream_output.num_outputs > 0) && !binning_pass) {
352 setup_stream_out(state, vs, &l);
353 }
354
355 for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
356 uint32_t reg = 0;
357
358 OUT_PKT4(ring, REG_A6XX_SP_VS_OUT_REG(i), 1);
359
360 reg |= A6XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
361 reg |= A6XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
362 j++;
363
364 reg |= A6XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
365 reg |= A6XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
366 j++;
367
368 OUT_RING(ring, reg);
369 }
370
371 for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
372 uint32_t reg = 0;
373
374 OUT_PKT4(ring, REG_A6XX_SP_VS_VPC_DST_REG(i), 1);
375
376 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
377 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
378 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
379 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
380
381 OUT_RING(ring, reg);
382 }
383
384 OUT_PKT4(ring, REG_A6XX_SP_VS_OBJ_START_LO, 2);
385 OUT_RELOC(ring, vs->bo, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
386
387 if (vs->instrlen)
388 fd6_emit_shader(ring, vs);
389
390
391 OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
392 OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
393
394 bool enable_varyings = fs->total_in > 0;
395
396 OUT_PKT4(ring, REG_A6XX_VPC_CNTL_0, 1);
397 OUT_RING(ring, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
398 COND(enable_varyings, A6XX_VPC_CNTL_0_VARYING) |
399 0xff00ff00);
400
401 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
402 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l.max_loc) |
403 CONDREG(psize_regid, 0x100));
404
405 if (binning_pass) {
406 OUT_PKT4(ring, REG_A6XX_SP_FS_OBJ_START_LO, 2);
407 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_LO */
408 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_HI */
409 } else {
410 OUT_PKT4(ring, REG_A6XX_SP_FS_OBJ_START_LO, 2);
411 OUT_RELOC(ring, fs->bo, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
412 }
413
414 OUT_PKT4(ring, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
415 OUT_RING(ring, 0x7); /* XXX */
416 OUT_RING(ring, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
417 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
418 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
419 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
420 OUT_RING(ring, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
421 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
422 0xfc00fc00); /* XXX */
423 OUT_RING(ring, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
424 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
425 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
426 0x0000fc00); /* XXX */
427 OUT_RING(ring, 0xfc); /* XXX */
428
429 OUT_PKT4(ring, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
430 OUT_RING(ring, enable_varyings ? 3 : 1);
431
432 OUT_PKT4(ring, REG_A6XX_SP_FS_CTRL_REG0, 1);
433 OUT_RING(ring, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
434 COND(enable_varyings, A6XX_SP_FS_CTRL_REG0_VARYING) |
435 COND(fs->frag_coord, A6XX_SP_FS_CTRL_REG0_VARYING) |
436 0x1000000 |
437 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
438 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
439 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack) |
440 COND(fs->need_pixlod, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE));
441
442 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A982, 1);
443 OUT_RING(ring, 0); /* XXX */
444
445 OUT_PKT4(ring, REG_A6XX_VPC_GS_SIV_CNTL, 1);
446 OUT_RING(ring, 0x0000ffff); /* XXX */
447
448 OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
449 OUT_RING(ring,
450 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
451 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
452 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
453 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
454 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
455 COND(fs->frag_coord,
456 A6XX_GRAS_CNTL_SIZE |
457 A6XX_GRAS_CNTL_XCOORD |
458 A6XX_GRAS_CNTL_YCOORD |
459 A6XX_GRAS_CNTL_ZCOORD |
460 A6XX_GRAS_CNTL_WCOORD) |
461 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
462
463 OUT_PKT4(ring, REG_A6XX_RB_RENDER_CONTROL0, 2);
464 OUT_RING(ring,
465 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
466 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
467 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
468 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
469 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
470 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
471 COND(fs->frag_coord,
472 A6XX_RB_RENDER_CONTROL0_SIZE |
473 A6XX_RB_RENDER_CONTROL0_XCOORD |
474 A6XX_RB_RENDER_CONTROL0_YCOORD |
475 A6XX_RB_RENDER_CONTROL0_ZCOORD |
476 A6XX_RB_RENDER_CONTROL0_WCOORD) |
477 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
478
479 OUT_RING(ring,
480 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
481 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
482 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
483 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
484
485 OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_CNTL, 1);
486 OUT_RING(ring, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
487
488 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8101, 1);
489 OUT_RING(ring, COND(sample_shading, 0x6)); // XXX
490
491 OUT_PKT4(ring, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
492 OUT_RING(ring, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
493
494 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
495 for (i = 0; i < 8; i++) {
496 OUT_RING(ring, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
497 COND(color_regid[i] & HALF_REG_ID, A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
498 }
499
500 OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
501 OUT_RING(ring, A6XX_VPC_PACK_POSITIONLOC(pos_loc) |
502 A6XX_VPC_PACK_PSIZELOC(psize_loc) |
503 A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
504
505 if (!binning_pass) {
506 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
507 for (j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
508 /* NOTE: varyings are packed, so if compmask is 0xb
509 * then first, third, and fourth component occupy
510 * three consecutive varying slots:
511 */
512 unsigned compmask = fs->inputs[j].compmask;
513
514 uint32_t inloc = fs->inputs[j].inloc;
515
516 if (fs->inputs[j].interpolate == INTERP_MODE_FLAT) {
517 uint32_t loc = inloc;
518
519 for (i = 0; i < 4; i++) {
520 if (compmask & (1 << i)) {
521 state->vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
522 loc++;
523 }
524 }
525 }
526 }
527 }
528
529 if (!binning_pass)
530 if (fs->instrlen)
531 fd6_emit_shader(ring, fs);
532
533 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_1, 6);
534 OUT_RING(ring, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
535 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
536 0xfcfc0000);
537 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_2 */
538 OUT_RING(ring, 0xfcfcfcfc); /* VFD_CONTROL_3 */
539 OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
540 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_5 */
541 OUT_RING(ring, 0x00000000); /* VFD_CONTROL_6 */
542
543 bool fragz = fs->no_earlyz | fs->writes_pos;
544
545 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
546 OUT_RING(ring, COND(fragz, A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));
547
548 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
549 OUT_RING(ring, COND(fragz, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));
550
551 ir3_emit_immediates(screen, vs, ring);
552 if (!binning_pass)
553 ir3_emit_immediates(screen, fs, ring);
554 }
555
556 /* emits the program state which is not part of the stateobj because of
557 * dependency on other gl state (rasterflat or sprite-coord-replacement)
558 */
559 void
560 fd6_program_emit(struct fd_ringbuffer *ring, struct fd6_emit *emit)
561 {
562 const struct fd6_program_state *state = fd6_emit_get_prog(emit);
563
564 if (!unlikely(emit->rasterflat || emit->sprite_coord_enable)) {
565 /* fastpath: */
566 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
567 for (int i = 0; i < 8; i++)
568 OUT_RING(ring, state->vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
569
570 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
571 for (int i = 0; i < 8; i++)
572 OUT_RING(ring, 0x00000000); /* VPC_VARYING_PS_REPL[i] */
573 } else {
574 /* slow-path: */
575 struct ir3_shader_variant *fs = state->fs;
576 uint32_t vinterp[8], vpsrepl[8];
577
578 memset(vinterp, 0, sizeof(vinterp));
579 memset(vpsrepl, 0, sizeof(vpsrepl));
580
581 for (int j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
582
583 /* NOTE: varyings are packed, so if compmask is 0xb
584 * then first, third, and fourth component occupy
585 * three consecutive varying slots:
586 */
587 unsigned compmask = fs->inputs[j].compmask;
588
589 uint32_t inloc = fs->inputs[j].inloc;
590
591 if ((fs->inputs[j].interpolate == INTERP_MODE_FLAT) ||
592 (fs->inputs[j].rasterflat && emit->rasterflat)) {
593 uint32_t loc = inloc;
594
595 for (int i = 0; i < 4; i++) {
596 if (compmask & (1 << i)) {
597 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
598 loc++;
599 }
600 }
601 }
602
603 gl_varying_slot slot = fs->inputs[j].slot;
604
605 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
606 if (slot >= VARYING_SLOT_VAR0) {
607 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
608 /* Replace the .xy coordinates with S/T from the point sprite. Set
609 * interpolation bits for .zw such that they become .01
610 */
611 if (emit->sprite_coord_enable & texmask) {
612 /* mask is two 2-bit fields, where:
613 * '01' -> S
614 * '10' -> T
615 * '11' -> 1 - T (flip mode)
616 */
617 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
618 uint32_t loc = inloc;
619 if (compmask & 0x1) {
620 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
621 loc++;
622 }
623 if (compmask & 0x2) {
624 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
625 loc++;
626 }
627 if (compmask & 0x4) {
628 /* .z <- 0.0f */
629 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
630 loc++;
631 }
632 if (compmask & 0x8) {
633 /* .w <- 1.0f */
634 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
635 loc++;
636 }
637 }
638 }
639 }
640
641 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
642 for (int i = 0; i < 8; i++)
643 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
644
645 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
646 for (int i = 0; i < 8; i++)
647 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
648 }
649 }
650
651 static struct ir3_program_state *
652 fd6_program_create(void *data, struct ir3_shader_variant *bs,
653 struct ir3_shader_variant *vs,
654 struct ir3_shader_variant *fs,
655 const struct ir3_shader_key *key)
656 {
657 struct fd_context *ctx = data;
658 struct fd6_program_state *state = CALLOC_STRUCT(fd6_program_state);
659
660 state->bs = bs;
661 state->vs = vs;
662 state->fs = fs;
663 state->config_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
664 state->binning_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
665 state->stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
666
667 #ifdef DEBUG
668 for (unsigned i = 0; i < bs->inputs_count; i++) {
669 if (vs->inputs[i].sysval)
670 continue;
671 debug_assert(bs->inputs[i].regid == vs->inputs[i].regid);
672 }
673 #endif
674
675 setup_config_stateobj(state->config_stateobj, state);
676 setup_stateobj(state->binning_stateobj, ctx->screen, state, key, true);
677 setup_stateobj(state->stateobj, ctx->screen, state, key, false);
678
679 return &state->base;
680 }
681
682 static void
683 fd6_program_destroy(void *data, struct ir3_program_state *state)
684 {
685 struct fd6_program_state *so = fd6_program_state(state);
686 fd_ringbuffer_del(so->stateobj);
687 fd_ringbuffer_del(so->binning_stateobj);
688 fd_ringbuffer_del(so->config_stateobj);
689 free(so);
690 }
691
692 static const struct ir3_cache_funcs cache_funcs = {
693 .create_state = fd6_program_create,
694 .destroy_state = fd6_program_destroy,
695 };
696
697 static void *
698 fd6_shader_state_create(struct pipe_context *pctx, const struct pipe_shader_state *cso)
699 {
700 struct fd_context *ctx = fd_context(pctx);
701 struct ir3_compiler *compiler = ctx->screen->compiler;
702 struct ir3_shader *shader =
703 ir3_shader_create(compiler, cso, &ctx->debug, pctx->screen);
704 unsigned packets, size;
705
706 /* pre-calculate size required for userconst stateobj: */
707 ir3_user_consts_size(&shader->ubo_state, &packets, &size);
708
709 /* also account for UBO addresses: */
710 packets += 1;
711 size += 2 * shader->const_state.num_ubos;
712
713 unsigned sizedwords = (4 * packets) + size;
714 shader->ubo_state.cmdstream_size = sizedwords * 4;
715
716 return shader;
717 }
718
719 static void
720 fd6_shader_state_delete(struct pipe_context *pctx, void *hwcso)
721 {
722 struct ir3_shader *so = hwcso;
723 struct fd_context *ctx = fd_context(pctx);
724 ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
725 ir3_shader_destroy(so);
726 }
727
728 void
729 fd6_prog_init(struct pipe_context *pctx)
730 {
731 struct fd_context *ctx = fd_context(pctx);
732
733 fd6_context(ctx)->shader_cache = ir3_cache_create(&cache_funcs, ctx);
734
735 pctx->create_vs_state = fd6_shader_state_create;
736 pctx->delete_vs_state = fd6_shader_state_delete;
737
738 pctx->create_fs_state = fd6_shader_state_create;
739 pctx->delete_fs_state = fd6_shader_state_delete;
740
741 fd_prog_init(pctx);
742 }