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72a47c1f5717b8d40e41ccc90ed2b3ff80cdd136
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_program.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/format/u_format.h"
33 #include "util/bitset.h"
34
35 #include "freedreno_program.h"
36
37 #include "fd6_program.h"
38 #include "fd6_const.h"
39 #include "fd6_emit.h"
40 #include "fd6_texture.h"
41 #include "fd6_format.h"
42
43 void
44 fd6_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
45 {
46 enum a6xx_state_block sb = fd6_stage2shadersb(so->type);
47
48 uint32_t obj_start;
49 uint32_t instrlen;
50
51 switch (so->type) {
52 case MESA_SHADER_VERTEX:
53 obj_start = REG_A6XX_SP_VS_OBJ_START_LO;
54 instrlen = REG_A6XX_SP_VS_INSTRLEN;
55 break;
56 case MESA_SHADER_TESS_CTRL:
57 obj_start = REG_A6XX_SP_HS_OBJ_START_LO;
58 instrlen = REG_A6XX_SP_HS_INSTRLEN;
59 break;
60 case MESA_SHADER_TESS_EVAL:
61 obj_start = REG_A6XX_SP_DS_OBJ_START_LO;
62 instrlen = REG_A6XX_SP_DS_INSTRLEN;
63 break;
64 case MESA_SHADER_GEOMETRY:
65 obj_start = REG_A6XX_SP_GS_OBJ_START_LO;
66 instrlen = REG_A6XX_SP_GS_INSTRLEN;
67 break;
68 case MESA_SHADER_FRAGMENT:
69 obj_start = REG_A6XX_SP_FS_OBJ_START_LO;
70 instrlen = REG_A6XX_SP_FS_INSTRLEN;
71 break;
72 case MESA_SHADER_COMPUTE:
73 case MESA_SHADER_KERNEL:
74 obj_start = REG_A6XX_SP_CS_OBJ_START_LO;
75 instrlen = REG_A6XX_SP_CS_INSTRLEN;
76 break;
77 case MESA_SHADER_NONE:
78 unreachable("");
79 }
80
81 #ifdef DEBUG
82 /* Name should generally match what you get with MESA_SHADER_CAPTURE_PATH: */
83 const char *name = so->shader->nir->info.name;
84 if (name)
85 fd_emit_string5(ring, name, strlen(name));
86 #endif
87
88 OUT_PKT4(ring, instrlen, 1);
89 OUT_RING(ring, so->instrlen);
90
91 OUT_PKT4(ring, obj_start, 2);
92 OUT_RELOC(ring, so->bo, 0, 0, 0);
93
94 OUT_PKT7(ring, fd6_stage2opcode(so->type), 3);
95 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
96 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
97 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
98 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
99 CP_LOAD_STATE6_0_NUM_UNIT(so->instrlen));
100 OUT_RELOC(ring, so->bo, 0, 0, 0);
101 }
102
103 /* Add any missing varyings needed for stream-out. Otherwise varyings not
104 * used by fragment shader will be stripped out.
105 */
106 static void
107 link_stream_out(struct ir3_shader_linkage *l, const struct ir3_shader_variant *v)
108 {
109 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
110
111 /*
112 * First, any stream-out varyings not already in linkage map (ie. also
113 * consumed by frag shader) need to be added:
114 */
115 for (unsigned i = 0; i < strmout->num_outputs; i++) {
116 const struct ir3_stream_output *out = &strmout->output[i];
117 unsigned k = out->register_index;
118 unsigned compmask =
119 (1 << (out->num_components + out->start_component)) - 1;
120 unsigned idx, nextloc = 0;
121
122 /* psize/pos need to be the last entries in linkage map, and will
123 * get added link_stream_out, so skip over them:
124 */
125 if ((v->outputs[k].slot == VARYING_SLOT_PSIZ) ||
126 (v->outputs[k].slot == VARYING_SLOT_POS))
127 continue;
128
129 for (idx = 0; idx < l->cnt; idx++) {
130 if (l->var[idx].regid == v->outputs[k].regid)
131 break;
132 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
133 }
134
135 /* add if not already in linkage map: */
136 if (idx == l->cnt)
137 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
138
139 /* expand component-mask if needed, ie streaming out all components
140 * but frag shader doesn't consume all components:
141 */
142 if (compmask & ~l->var[idx].compmask) {
143 l->var[idx].compmask |= compmask;
144 l->max_loc = MAX2(l->max_loc,
145 l->var[idx].loc + util_last_bit(l->var[idx].compmask));
146 }
147 }
148 }
149
150 static void
151 setup_stream_out(struct fd6_program_state *state, const struct ir3_shader_variant *v,
152 struct ir3_shader_linkage *l)
153 {
154 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
155
156 uint32_t ncomp[PIPE_MAX_SO_BUFFERS];
157 uint32_t prog[256/2];
158 uint32_t prog_count;
159
160 memset(ncomp, 0, sizeof(ncomp));
161 memset(prog, 0, sizeof(prog));
162
163 prog_count = align(l->max_loc, 2) / 2;
164
165 debug_assert(prog_count < ARRAY_SIZE(prog));
166
167 for (unsigned i = 0; i < strmout->num_outputs; i++) {
168 const struct ir3_stream_output *out = &strmout->output[i];
169 unsigned k = out->register_index;
170 unsigned idx;
171
172 ncomp[out->output_buffer] += out->num_components;
173
174 /* linkage map sorted by order frag shader wants things, so
175 * a bit less ideal here..
176 */
177 for (idx = 0; idx < l->cnt; idx++)
178 if (l->var[idx].regid == v->outputs[k].regid)
179 break;
180
181 debug_assert(idx < l->cnt);
182
183 for (unsigned j = 0; j < out->num_components; j++) {
184 unsigned c = j + out->start_component;
185 unsigned loc = l->var[idx].loc + c;
186 unsigned off = j + out->dst_offset; /* in dwords */
187
188 if (loc & 1) {
189 prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
190 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
191 A6XX_VPC_SO_PROG_B_OFF(off * 4);
192 } else {
193 prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
194 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
195 A6XX_VPC_SO_PROG_A_OFF(off * 4);
196 }
197 }
198 }
199
200 struct fd_ringbuffer *ring = state->streamout_stateobj;
201
202 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * prog_count));
203 OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
204 OUT_RING(ring, A6XX_VPC_SO_BUF_CNTL_ENABLE |
205 COND(ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
206 COND(ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
207 COND(ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
208 COND(ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3));
209 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(0));
210 OUT_RING(ring, ncomp[0]);
211 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(1));
212 OUT_RING(ring, ncomp[1]);
213 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(2));
214 OUT_RING(ring, ncomp[2]);
215 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(3));
216 OUT_RING(ring, ncomp[3]);
217 OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
218 OUT_RING(ring, A6XX_VPC_SO_CNTL_ENABLE);
219 for (unsigned i = 0; i < prog_count; i++) {
220 OUT_RING(ring, REG_A6XX_VPC_SO_PROG);
221 OUT_RING(ring, prog[i]);
222 }
223 }
224
225 static void
226 setup_config_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *state)
227 {
228 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
229 OUT_RING(ring, 0xff); /* XXX */
230
231 debug_assert(state->vs->constlen >= state->bs->constlen);
232
233 OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
234 OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(state->vs->constlen) |
235 A6XX_HLSQ_VS_CNTL_ENABLED);
236 OUT_RING(ring, COND(state->hs,
237 A6XX_HLSQ_HS_CNTL_ENABLED |
238 A6XX_HLSQ_HS_CNTL_CONSTLEN(state->hs->constlen)));
239 OUT_RING(ring, COND(state->ds,
240 A6XX_HLSQ_DS_CNTL_ENABLED |
241 A6XX_HLSQ_DS_CNTL_CONSTLEN(state->ds->constlen)));
242 OUT_RING(ring, COND(state->gs,
243 A6XX_HLSQ_GS_CNTL_ENABLED |
244 A6XX_HLSQ_GS_CNTL_CONSTLEN(state->gs->constlen)));
245 OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL, 1);
246 OUT_RING(ring, A6XX_HLSQ_FS_CNTL_CONSTLEN(state->fs->constlen) |
247 A6XX_HLSQ_FS_CNTL_ENABLED);
248
249 OUT_PKT4(ring, REG_A6XX_SP_VS_CONFIG, 1);
250 OUT_RING(ring, COND(state->vs, A6XX_SP_VS_CONFIG_ENABLED) |
251 A6XX_SP_VS_CONFIG_NIBO(ir3_shader_nibo(state->vs)) |
252 A6XX_SP_VS_CONFIG_NTEX(state->vs->num_samp) |
253 A6XX_SP_VS_CONFIG_NSAMP(state->vs->num_samp));
254
255 OUT_PKT4(ring, REG_A6XX_SP_HS_CONFIG, 1);
256 OUT_RING(ring, COND(state->hs,
257 A6XX_SP_HS_CONFIG_ENABLED |
258 A6XX_SP_HS_CONFIG_NIBO(ir3_shader_nibo(state->hs)) |
259 A6XX_SP_HS_CONFIG_NTEX(state->hs->num_samp) |
260 A6XX_SP_HS_CONFIG_NSAMP(state->hs->num_samp)));
261
262 OUT_PKT4(ring, REG_A6XX_SP_DS_CONFIG, 1);
263 OUT_RING(ring, COND(state->ds,
264 A6XX_SP_DS_CONFIG_ENABLED |
265 A6XX_SP_DS_CONFIG_NIBO(ir3_shader_nibo(state->ds)) |
266 A6XX_SP_DS_CONFIG_NTEX(state->ds->num_samp) |
267 A6XX_SP_DS_CONFIG_NSAMP(state->ds->num_samp)));
268
269 OUT_PKT4(ring, REG_A6XX_SP_GS_CONFIG, 1);
270 OUT_RING(ring, COND(state->gs,
271 A6XX_SP_GS_CONFIG_ENABLED |
272 A6XX_SP_GS_CONFIG_NIBO(ir3_shader_nibo(state->gs)) |
273 A6XX_SP_GS_CONFIG_NTEX(state->gs->num_samp) |
274 A6XX_SP_GS_CONFIG_NSAMP(state->gs->num_samp)));
275
276 OUT_PKT4(ring, REG_A6XX_SP_FS_CONFIG, 1);
277 OUT_RING(ring, COND(state->fs, A6XX_SP_FS_CONFIG_ENABLED) |
278 A6XX_SP_FS_CONFIG_NIBO(ir3_shader_nibo(state->fs)) |
279 A6XX_SP_FS_CONFIG_NTEX(state->fs->num_samp) |
280 A6XX_SP_FS_CONFIG_NSAMP(state->fs->num_samp));
281
282 OUT_PKT4(ring, REG_A6XX_SP_IBO_COUNT, 1);
283 OUT_RING(ring, ir3_shader_nibo(state->fs));
284 }
285
286 static inline uint32_t
287 next_regid(uint32_t reg, uint32_t increment)
288 {
289 if (VALIDREG(reg))
290 return reg + increment;
291 else
292 return regid(63,0);
293 }
294
295 static void
296 setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
297 struct fd6_program_state *state, const struct ir3_shader_key *key,
298 bool binning_pass)
299 {
300 uint32_t pos_regid, psize_regid, color_regid[8], posz_regid;
301 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
302 uint32_t smask_in_regid, smask_regid;
303 uint32_t vertex_regid, instance_regid, layer_regid, primitive_regid;
304 uint32_t hs_invocation_regid;
305 uint32_t tess_coord_x_regid, tess_coord_y_regid, hs_patch_regid, ds_patch_regid;
306 uint32_t ij_regid[IJ_COUNT];
307 uint32_t gs_header_regid;
308 enum a3xx_threadsize fssz;
309 uint8_t psize_loc = ~0, pos_loc = ~0, layer_loc = ~0;
310 int i, j;
311
312 static const struct ir3_shader_variant dummy_fs = {0};
313 const struct ir3_shader_variant *vs = binning_pass ? state->bs : state->vs;
314 const struct ir3_shader_variant *hs = state->hs;
315 const struct ir3_shader_variant *ds = state->ds;
316 const struct ir3_shader_variant *gs = state->gs;
317 const struct ir3_shader_variant *fs = binning_pass ? &dummy_fs : state->fs;
318
319 /* binning VS is wrong when GS is present, so use nonbinning VS
320 * TODO: compile both binning VS/GS variants correctly
321 */
322 if (binning_pass && state->gs)
323 vs = state->vs;
324
325 bool sample_shading = fs->per_samp | key->sample_shading;
326
327 fssz = FOUR_QUADS;
328
329 pos_regid = ir3_find_output_regid(vs, VARYING_SLOT_POS);
330 psize_regid = ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
331 vertex_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
332 instance_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
333
334 if (hs) {
335 tess_coord_x_regid = ir3_find_sysval_regid(ds, SYSTEM_VALUE_TESS_COORD);
336 tess_coord_y_regid = next_regid(tess_coord_x_regid, 1);
337 hs_patch_regid = ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID);
338 ds_patch_regid = ir3_find_sysval_regid(ds, SYSTEM_VALUE_PRIMITIVE_ID);
339 hs_invocation_regid = ir3_find_sysval_regid(hs, SYSTEM_VALUE_TCS_HEADER_IR3);
340
341 pos_regid = ir3_find_output_regid(ds, VARYING_SLOT_POS);
342 psize_regid = ir3_find_output_regid(ds, VARYING_SLOT_PSIZ);
343 } else {
344 tess_coord_x_regid = regid(63, 0);
345 tess_coord_y_regid = regid(63, 0);
346 hs_patch_regid = regid(63, 0);
347 ds_patch_regid = regid(63, 0);
348 hs_invocation_regid = regid(63, 0);
349 }
350
351 if (gs) {
352 gs_header_regid = ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3);
353 primitive_regid = ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
354 pos_regid = ir3_find_output_regid(gs, VARYING_SLOT_POS);
355 psize_regid = ir3_find_output_regid(gs, VARYING_SLOT_PSIZ);
356 layer_regid = ir3_find_output_regid(gs, VARYING_SLOT_LAYER);
357 } else {
358 gs_header_regid = regid(63, 0);
359 primitive_regid = regid(63, 0);
360 layer_regid = regid(63, 0);
361 }
362
363 if (fs->color0_mrt) {
364 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
365 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
366 ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
367 } else {
368 color_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0);
369 color_regid[1] = ir3_find_output_regid(fs, FRAG_RESULT_DATA1);
370 color_regid[2] = ir3_find_output_regid(fs, FRAG_RESULT_DATA2);
371 color_regid[3] = ir3_find_output_regid(fs, FRAG_RESULT_DATA3);
372 color_regid[4] = ir3_find_output_regid(fs, FRAG_RESULT_DATA4);
373 color_regid[5] = ir3_find_output_regid(fs, FRAG_RESULT_DATA5);
374 color_regid[6] = ir3_find_output_regid(fs, FRAG_RESULT_DATA6);
375 color_regid[7] = ir3_find_output_regid(fs, FRAG_RESULT_DATA7);
376 }
377
378 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
379 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
380 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
381 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
382 zwcoord_regid = next_regid(coord_regid, 2);
383 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
384 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
385 for (unsigned i = 0; i < ARRAY_SIZE(ij_regid); i++)
386 ij_regid[i] = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL + i);
387
388 /* If we have pre-dispatch texture fetches, then ij_pix should not
389 * be DCE'd, even if not actually used in the shader itself:
390 */
391 if (fs->num_sampler_prefetch > 0) {
392 assert(VALIDREG(ij_regid[IJ_PERSP_PIXEL]));
393 /* also, it seems like ij_pix is *required* to be r0.x */
394 assert(ij_regid[IJ_PERSP_PIXEL] == regid(0, 0));
395 }
396
397 /* we can't write gl_SampleMask for !msaa.. if b0 is zero then we
398 * end up masking the single sample!!
399 */
400 if (!key->msaa)
401 smask_regid = regid(63, 0);
402
403 /* we could probably divide this up into things that need to be
404 * emitted if frag-prog is dirty vs if vert-prog is dirty..
405 */
406
407 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A833, 1);
408 OUT_RING(ring, 0x0);
409
410 OUT_PKT4(ring, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
411 OUT_RING(ring, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
412 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
413 0x7000); // XXX
414 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
415 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
416 OUT_RING(ring, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
417 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
418 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
419 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
420 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
421 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
422 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
423 }
424
425 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A9A8, 1);
426 OUT_RING(ring, 0);
427
428 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_AB00, 1);
429 OUT_RING(ring, 0x5);
430
431 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL0, 1);
432 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
433 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
434 0xfc000000);
435
436 enum a3xx_threadsize vssz;
437 if (ds || hs) {
438 vssz = TWO_QUADS;
439 } else {
440 vssz = FOUR_QUADS;
441 }
442
443 OUT_PKT4(ring, REG_A6XX_SP_VS_CTRL_REG0, 1);
444 OUT_RING(ring, A6XX_SP_VS_CTRL_REG0_THREADSIZE(vssz) |
445 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
446 A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vs->info.max_half_reg + 1) |
447 COND(vs->mergedregs, A6XX_SP_VS_CTRL_REG0_MERGEDREGS) |
448 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack) |
449 COND(vs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE));
450
451 fd6_emit_shader(ring, vs);
452 fd6_emit_immediates(screen, vs, ring);
453
454 struct ir3_shader_linkage l = {0};
455 const struct ir3_shader_variant *last_shader = fd6_last_shader(state);
456 ir3_link_shaders(&l, last_shader, fs, true);
457
458 bool primid_passthru = l.primid_loc != 0xff;
459
460 OUT_PKT4(ring, REG_A6XX_VPC_VAR_DISABLE(0), 4);
461 OUT_RING(ring, ~l.varmask[0]); /* VPC_VAR[0].DISABLE */
462 OUT_RING(ring, ~l.varmask[1]); /* VPC_VAR[1].DISABLE */
463 OUT_RING(ring, ~l.varmask[2]); /* VPC_VAR[2].DISABLE */
464 OUT_RING(ring, ~l.varmask[3]); /* VPC_VAR[3].DISABLE */
465
466 /* Add stream out outputs after computing the VPC_VAR_DISABLE bitmask. */
467 if (last_shader->shader->stream_output.num_outputs > 0)
468 link_stream_out(&l, last_shader);
469
470 if (VALIDREG(layer_regid)) {
471 layer_loc = l.max_loc;
472 ir3_link_add(&l, layer_regid, 0x1, l.max_loc);
473 }
474
475 if (VALIDREG(pos_regid)) {
476 pos_loc = l.max_loc;
477 ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
478 }
479
480 if (VALIDREG(psize_regid)) {
481 psize_loc = l.max_loc;
482 ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
483 }
484
485 if (last_shader->shader->stream_output.num_outputs > 0) {
486 setup_stream_out(state, last_shader, &l);
487 }
488
489 debug_assert(l.cnt < 32);
490 if (gs)
491 OUT_PKT4(ring, REG_A6XX_SP_GS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
492 else if (ds)
493 OUT_PKT4(ring, REG_A6XX_SP_DS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
494 else
495 OUT_PKT4(ring, REG_A6XX_SP_VS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
496
497 for (j = 0; j < l.cnt; ) {
498 uint32_t reg = 0;
499
500 reg |= A6XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
501 reg |= A6XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
502 j++;
503
504 reg |= A6XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
505 reg |= A6XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
506 j++;
507
508 OUT_RING(ring, reg);
509 }
510
511 if (gs)
512 OUT_PKT4(ring, REG_A6XX_SP_GS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
513 else if (ds)
514 OUT_PKT4(ring, REG_A6XX_SP_DS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
515 else
516 OUT_PKT4(ring, REG_A6XX_SP_VS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
517
518 for (j = 0; j < l.cnt; ) {
519 uint32_t reg = 0;
520
521 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
522 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
523 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
524 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
525
526 OUT_RING(ring, reg);
527 }
528
529 if (hs) {
530 OUT_PKT4(ring, REG_A6XX_SP_HS_CTRL_REG0, 1);
531 OUT_RING(ring, A6XX_SP_HS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
532 A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(hs->info.max_reg + 1) |
533 A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(hs->info.max_half_reg + 1) |
534 COND(hs->mergedregs, A6XX_SP_HS_CTRL_REG0_MERGEDREGS) |
535 A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(hs->branchstack) |
536 COND(hs->need_pixlod, A6XX_SP_HS_CTRL_REG0_PIXLODENABLE));
537
538 fd6_emit_shader(ring, hs);
539 fd6_emit_immediates(screen, hs, ring);
540 fd6_emit_link_map(screen, vs, hs, ring);
541
542 OUT_PKT4(ring, REG_A6XX_SP_DS_CTRL_REG0, 1);
543 OUT_RING(ring, A6XX_SP_DS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
544 A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(ds->info.max_reg + 1) |
545 A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(ds->info.max_half_reg + 1) |
546 COND(ds->mergedregs, A6XX_SP_DS_CTRL_REG0_MERGEDREGS) |
547 A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(ds->branchstack) |
548 COND(ds->need_pixlod, A6XX_SP_DS_CTRL_REG0_PIXLODENABLE));
549
550 fd6_emit_shader(ring, ds);
551 fd6_emit_immediates(screen, ds, ring);
552 fd6_emit_link_map(screen, hs, ds, ring);
553
554 shader_info *hs_info = &hs->shader->nir->info;
555 OUT_PKT4(ring, REG_A6XX_PC_TESS_NUM_VERTEX, 1);
556 OUT_RING(ring, hs_info->tess.tcs_vertices_out);
557
558 /* Total attribute slots in HS incoming patch. */
559 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9801, 1);
560 OUT_RING(ring, hs_info->tess.tcs_vertices_out * vs->output_size / 4);
561
562 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
563 OUT_RING(ring, vs->output_size);
564
565 shader_info *ds_info = &ds->shader->nir->info;
566 OUT_PKT4(ring, REG_A6XX_PC_TESS_CNTL, 1);
567 uint32_t output;
568 if (ds_info->tess.point_mode)
569 output = TESS_POINTS;
570 else if (ds_info->tess.primitive_mode == GL_ISOLINES)
571 output = TESS_LINES;
572 else if (ds_info->tess.ccw)
573 output = TESS_CCW_TRIS;
574 else
575 output = TESS_CW_TRIS;
576
577 OUT_RING(ring, A6XX_PC_TESS_CNTL_SPACING(fd6_gl2spacing(ds_info->tess.spacing)) |
578 A6XX_PC_TESS_CNTL_OUTPUT(output));
579
580 OUT_PKT4(ring, REG_A6XX_VPC_DS_CLIP_CNTL, 1);
581 OUT_RING(ring, 0x00ffff00);
582
583 OUT_PKT4(ring, REG_A6XX_VPC_DS_LAYER_CNTL, 1);
584 OUT_RING(ring, 0x0000ffff);
585
586 OUT_PKT4(ring, REG_A6XX_GRAS_DS_LAYER_CNTL, 1);
587 OUT_RING(ring, 0x0);
588
589 OUT_PKT4(ring, REG_A6XX_GRAS_DS_CL_CNTL, 1);
590 OUT_RING(ring, 0x0);
591
592 OUT_PKT4(ring, REG_A6XX_VPC_VS_PACK, 1);
593 OUT_RING(ring, A6XX_VPC_VS_PACK_POSITIONLOC(pos_loc) |
594 A6XX_VPC_VS_PACK_PSIZELOC(255) |
595 A6XX_VPC_VS_PACK_STRIDE_IN_VPC(l.max_loc));
596
597 OUT_PKT4(ring, REG_A6XX_VPC_DS_PACK, 1);
598 OUT_RING(ring, A6XX_VPC_DS_PACK_POSITIONLOC(pos_loc) |
599 A6XX_VPC_DS_PACK_PSIZELOC(psize_loc) |
600 A6XX_VPC_DS_PACK_STRIDE_IN_VPC(l.max_loc));
601
602 OUT_PKT4(ring, REG_A6XX_SP_DS_PRIMITIVE_CNTL, 1);
603 OUT_RING(ring, A6XX_SP_DS_PRIMITIVE_CNTL_OUT(l.cnt));
604
605 OUT_PKT4(ring, REG_A6XX_PC_DS_OUT_CNTL, 1);
606 OUT_RING(ring, A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(l.max_loc) |
607 CONDREG(psize_regid, 0x100));
608
609 } else {
610 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
611 OUT_RING(ring, 0);
612 }
613
614 OUT_PKT4(ring, REG_A6XX_SP_VS_PRIMITIVE_CNTL, 1);
615 OUT_RING(ring, A6XX_SP_VS_PRIMITIVE_CNTL_OUT(l.cnt));
616
617 bool enable_varyings = fs->total_in > 0;
618
619 OUT_PKT4(ring, REG_A6XX_VPC_CNTL_0, 1);
620 OUT_RING(ring, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
621 COND(enable_varyings, A6XX_VPC_CNTL_0_VARYING) |
622 A6XX_VPC_CNTL_0_PRIMIDLOC(l.primid_loc) |
623 A6XX_VPC_CNTL_0_UNKLOC(0xff));
624
625 OUT_PKT4(ring, REG_A6XX_PC_VS_OUT_CNTL, 1);
626 OUT_RING(ring, A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(l.max_loc) |
627 CONDREG(psize_regid, A6XX_PC_VS_OUT_CNTL_PSIZE));
628
629 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
630 OUT_RING(ring, 0);
631
632 OUT_PKT4(ring, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
633 OUT_RING(ring, 0x7); /* XXX */
634 OUT_RING(ring, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
635 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
636 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
637 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_regid[IJ_PERSP_SIZE]));
638 OUT_RING(ring,
639 A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid[IJ_PERSP_PIXEL]) |
640 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(ij_regid[IJ_LINEAR_PIXEL]) |
641 A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(ij_regid[IJ_PERSP_CENTROID]) |
642 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(ij_regid[IJ_LINEAR_CENTROID]));
643 OUT_RING(ring, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
644 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
645 A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(ij_regid[IJ_PERSP_SAMPLE]) |
646 A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(ij_regid[IJ_LINEAR_SAMPLE]));
647 OUT_RING(ring, 0xfc); /* XXX */
648
649 OUT_PKT4(ring, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
650 OUT_RING(ring, enable_varyings ? 3 : 1);
651
652 OUT_PKT4(ring, REG_A6XX_SP_FS_CTRL_REG0, 1);
653 OUT_RING(ring, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
654 COND(enable_varyings, A6XX_SP_FS_CTRL_REG0_VARYING) |
655 0x1000000 |
656 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
657 A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fs->info.max_half_reg + 1) |
658 COND(fs->mergedregs, A6XX_SP_FS_CTRL_REG0_MERGEDREGS) |
659 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack) |
660 COND(fs->need_pixlod, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE));
661
662 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A982, 1);
663 OUT_RING(ring, 0); /* XXX */
664
665 OUT_PKT4(ring, REG_A6XX_VPC_VS_LAYER_CNTL, 1);
666 OUT_RING(ring, 0x0000ffff); /* XXX */
667
668 bool need_size = fs->frag_face || fs->fragcoord_compmask != 0;
669 bool need_size_persamp = false;
670 if (VALIDREG(ij_regid[IJ_PERSP_SIZE])) {
671 if (sample_shading)
672 need_size_persamp = true;
673 else
674 need_size = true;
675 }
676 if (VALIDREG(ij_regid[IJ_LINEAR_PIXEL]))
677 need_size = true;
678
679 /* XXX: enable bits for linear centroid and linear sample bary */
680
681 OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
682 OUT_RING(ring,
683 CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_GRAS_CNTL_IJ_PERSP_PIXEL) |
684 CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_GRAS_CNTL_IJ_PERSP_CENTROID) |
685 CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE) |
686 COND(need_size, A6XX_GRAS_CNTL_SIZE) |
687 COND(need_size_persamp, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
688 COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)));
689
690 OUT_PKT4(ring, REG_A6XX_RB_RENDER_CONTROL0, 2);
691 OUT_RING(ring,
692 CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL) |
693 CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID) |
694 CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE) |
695 COND(need_size, A6XX_RB_RENDER_CONTROL0_SIZE) |
696 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
697 COND(need_size_persamp, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
698 COND(fs->fragcoord_compmask != 0,
699 A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)));
700
701 OUT_RING(ring,
702 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
703 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
704 CONDREG(ij_regid[IJ_PERSP_SIZE], A6XX_RB_RENDER_CONTROL1_SIZE) |
705 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
706
707 OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_CNTL, 1);
708 OUT_RING(ring, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
709
710 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8101, 1);
711 OUT_RING(ring, COND(sample_shading, 0x6)); // XXX
712
713 OUT_PKT4(ring, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
714 OUT_RING(ring, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
715
716 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
717 for (i = 0; i < 8; i++) {
718 OUT_RING(ring, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
719 COND(color_regid[i] & HALF_REG_ID, A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
720 }
721
722 OUT_PKT4(ring, REG_A6XX_VPC_VS_PACK, 1);
723 OUT_RING(ring, A6XX_VPC_VS_PACK_POSITIONLOC(pos_loc) |
724 A6XX_VPC_VS_PACK_PSIZELOC(psize_loc) |
725 A6XX_VPC_VS_PACK_STRIDE_IN_VPC(l.max_loc));
726
727 if (gs) {
728 OUT_PKT4(ring, REG_A6XX_SP_GS_CTRL_REG0, 1);
729 OUT_RING(ring, A6XX_SP_GS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
730 A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs->info.max_reg + 1) |
731 A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(gs->info.max_half_reg + 1) |
732 COND(gs->mergedregs, A6XX_SP_GS_CTRL_REG0_MERGEDREGS) |
733 A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(gs->branchstack) |
734 COND(gs->need_pixlod, A6XX_SP_GS_CTRL_REG0_PIXLODENABLE));
735
736 fd6_emit_shader(ring, gs);
737 fd6_emit_immediates(screen, gs, ring);
738 if (ds)
739 fd6_emit_link_map(screen, ds, gs, ring);
740 else
741 fd6_emit_link_map(screen, vs, gs, ring);
742
743 OUT_PKT4(ring, REG_A6XX_VPC_GS_PACK, 1);
744 OUT_RING(ring, A6XX_VPC_GS_PACK_POSITIONLOC(pos_loc) |
745 A6XX_VPC_GS_PACK_PSIZELOC(psize_loc) |
746 A6XX_VPC_GS_PACK_STRIDE_IN_VPC(l.max_loc));
747
748 OUT_PKT4(ring, REG_A6XX_VPC_GS_LAYER_CNTL, 1);
749 OUT_RING(ring, A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(layer_loc) | 0xff00);
750
751 OUT_PKT4(ring, REG_A6XX_GRAS_GS_LAYER_CNTL, 1);
752 OUT_RING(ring, CONDREG(layer_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER));
753
754 uint32_t flags_regid = ir3_find_output_regid(gs, VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
755
756 OUT_PKT4(ring, REG_A6XX_SP_GS_PRIMITIVE_CNTL, 1);
757 OUT_RING(ring, A6XX_SP_GS_PRIMITIVE_CNTL_OUT(l.cnt) |
758 A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(flags_regid));
759
760 OUT_PKT4(ring, REG_A6XX_PC_GS_OUT_CNTL, 1);
761 OUT_RING(ring, A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(l.max_loc) |
762 CONDREG(psize_regid, A6XX_PC_GS_OUT_CNTL_PSIZE) |
763 CONDREG(layer_regid, A6XX_PC_GS_OUT_CNTL_LAYER) |
764 CONDREG(primitive_regid, A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID));
765
766 uint32_t output;
767 switch (gs->shader->nir->info.gs.output_primitive) {
768 case GL_POINTS:
769 output = TESS_POINTS;
770 break;
771 case GL_LINE_STRIP:
772 output = TESS_LINES;
773 break;
774 case GL_TRIANGLE_STRIP:
775 output = TESS_CW_TRIS;
776 break;
777 default:
778 unreachable("");
779 }
780 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
781 OUT_RING(ring,
782 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(gs->shader->nir->info.gs.vertices_out - 1) |
783 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
784 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(gs->shader->nir->info.gs.invocations - 1));
785
786 OUT_PKT4(ring, REG_A6XX_GRAS_GS_CL_CNTL, 1);
787 OUT_RING(ring, 0);
788
789 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9100, 1);
790 OUT_RING(ring, 0xff);
791
792 OUT_PKT4(ring, REG_A6XX_VPC_GS_CLIP_CNTL, 1);
793 OUT_RING(ring, 0xffff00);
794
795 const struct ir3_shader_variant *prev = state->ds ? state->ds : state->vs;
796
797 /* Size of per-primitive alloction in ldlw memory in vec4s. */
798 uint32_t vec4_size =
799 gs->shader->nir->info.gs.vertices_in *
800 DIV_ROUND_UP(prev->output_size, 4);
801 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
802 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
803
804 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9B07, 1);
805 OUT_RING(ring, 0);
806
807 OUT_PKT4(ring, REG_A6XX_SP_GS_PRIM_SIZE, 1);
808 OUT_RING(ring, prev->output_size);
809 } else {
810 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
811 OUT_RING(ring, 0);
812 OUT_PKT4(ring, REG_A6XX_SP_GS_PRIM_SIZE, 1);
813 OUT_RING(ring, 0);
814 }
815
816 OUT_PKT4(ring, REG_A6XX_VPC_VS_CLIP_CNTL, 1);
817 OUT_RING(ring, 0xffff00);
818
819 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9107, 1);
820 OUT_RING(ring, 0);
821
822 if (fs->instrlen)
823 fd6_emit_shader(ring, fs);
824
825 OUT_PKT4(ring, REG_A6XX_PC_PRIMID_CNTL, 1);
826 OUT_RING(ring, COND(primid_passthru, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU));
827
828 uint32_t non_sysval_input_count = 0;
829 for (uint32_t i = 0; i < vs->inputs_count; i++)
830 if (!vs->inputs[i].sysval)
831 non_sysval_input_count++;
832
833 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_0, 1);
834 OUT_RING(ring, A6XX_VFD_CONTROL_0_FETCH_CNT(non_sysval_input_count) |
835 A6XX_VFD_CONTROL_0_DECODE_CNT(non_sysval_input_count));
836
837 OUT_PKT4(ring, REG_A6XX_VFD_DEST_CNTL(0), non_sysval_input_count);
838 for (uint32_t i = 0; i < non_sysval_input_count; i++) {
839 assert(vs->inputs[i].compmask);
840 OUT_RING(ring, A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs->inputs[i].compmask) |
841 A6XX_VFD_DEST_CNTL_INSTR_REGID(vs->inputs[i].regid));
842 }
843
844 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_1, 6);
845 OUT_RING(ring, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
846 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
847 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitive_regid) |
848 0xfc000000);
849 OUT_RING(ring, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid) |
850 A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid));
851 OUT_RING(ring, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid) |
852 A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid) |
853 A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid) |
854 0xfc);
855 OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
856 OUT_RING(ring, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gs_header_regid) |
857 0xfc00); /* VFD_CONTROL_5 */
858 OUT_RING(ring,
859 COND(primid_passthru, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU)); /* VFD_CONTROL_6 */
860
861 if (!binning_pass)
862 fd6_emit_immediates(screen, fs, ring);
863 }
864
865 static void emit_interp_state(struct fd_ringbuffer *ring, struct ir3_shader_variant *fs,
866 bool rasterflat, bool sprite_coord_mode, uint32_t sprite_coord_enable);
867
868 static struct fd_ringbuffer *
869 create_interp_stateobj(struct fd_context *ctx, struct fd6_program_state *state)
870 {
871 struct fd_ringbuffer *ring = fd_ringbuffer_new_object(ctx->pipe, 18 * 4);
872
873 emit_interp_state(ring, state->fs, false, false, 0);
874
875 return ring;
876 }
877
878 /* build the program streaming state which is not part of the pre-
879 * baked stateobj because of dependency on other gl state (rasterflat
880 * or sprite-coord-replacement)
881 */
882 struct fd_ringbuffer *
883 fd6_program_interp_state(struct fd6_emit *emit)
884 {
885 const struct fd6_program_state *state = fd6_emit_get_prog(emit);
886
887 if (!unlikely(emit->rasterflat || emit->sprite_coord_enable)) {
888 /* fastpath: */
889 return fd_ringbuffer_ref(state->interp_stateobj);
890 } else {
891 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
892 emit->ctx->batch->submit, 18 * 4, FD_RINGBUFFER_STREAMING);
893
894 emit_interp_state(ring, state->fs, emit->rasterflat,
895 emit->sprite_coord_mode, emit->sprite_coord_enable);
896
897 return ring;
898 }
899 }
900
901 static void
902 emit_interp_state(struct fd_ringbuffer *ring, struct ir3_shader_variant *fs,
903 bool rasterflat, bool sprite_coord_mode, uint32_t sprite_coord_enable)
904 {
905 uint32_t vinterp[8], vpsrepl[8];
906
907 memset(vinterp, 0, sizeof(vinterp));
908 memset(vpsrepl, 0, sizeof(vpsrepl));
909
910 for (int j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
911
912 /* NOTE: varyings are packed, so if compmask is 0xb
913 * then first, third, and fourth component occupy
914 * three consecutive varying slots:
915 */
916 unsigned compmask = fs->inputs[j].compmask;
917
918 uint32_t inloc = fs->inputs[j].inloc;
919
920 if ((fs->inputs[j].interpolate == INTERP_MODE_FLAT) ||
921 (fs->inputs[j].rasterflat && rasterflat)) {
922 uint32_t loc = inloc;
923
924 for (int i = 0; i < 4; i++) {
925 if (compmask & (1 << i)) {
926 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
927 loc++;
928 }
929 }
930 }
931
932 bool coord_mode = sprite_coord_mode;
933 if (ir3_point_sprite(fs, j, sprite_coord_enable, &coord_mode)) {
934 /* mask is two 2-bit fields, where:
935 * '01' -> S
936 * '10' -> T
937 * '11' -> 1 - T (flip mode)
938 */
939 unsigned mask = coord_mode ? 0b1101 : 0b1001;
940 uint32_t loc = inloc;
941 if (compmask & 0x1) {
942 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
943 loc++;
944 }
945 if (compmask & 0x2) {
946 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
947 loc++;
948 }
949 if (compmask & 0x4) {
950 /* .z <- 0.0f */
951 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
952 loc++;
953 }
954 if (compmask & 0x8) {
955 /* .w <- 1.0f */
956 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
957 loc++;
958 }
959 }
960 }
961
962 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
963 for (int i = 0; i < 8; i++)
964 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
965
966 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
967 for (int i = 0; i < 8; i++)
968 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
969 }
970
971 static struct ir3_program_state *
972 fd6_program_create(void *data, struct ir3_shader_variant *bs,
973 struct ir3_shader_variant *vs,
974 struct ir3_shader_variant *hs,
975 struct ir3_shader_variant *ds,
976 struct ir3_shader_variant *gs,
977 struct ir3_shader_variant *fs,
978 const struct ir3_shader_key *key)
979 {
980 struct fd_context *ctx = data;
981 struct fd6_program_state *state = CALLOC_STRUCT(fd6_program_state);
982
983 /* if we have streamout, use full VS in binning pass, as the
984 * binning pass VS will have outputs on other than position/psize
985 * stripped out:
986 */
987 state->bs = vs->shader->stream_output.num_outputs ? vs : bs;
988 state->vs = vs;
989 state->hs = hs;
990 state->ds = ds;
991 state->gs = gs;
992 state->fs = fs;
993 state->config_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
994 state->binning_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
995 state->stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
996 state->streamout_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
997
998
999 #ifdef DEBUG
1000 if (!ds) {
1001 for (unsigned i = 0; i < bs->inputs_count; i++) {
1002 if (vs->inputs[i].sysval)
1003 continue;
1004 debug_assert(bs->inputs[i].regid == vs->inputs[i].regid);
1005 }
1006 }
1007 #endif
1008
1009 setup_config_stateobj(state->config_stateobj, state);
1010 setup_stateobj(state->binning_stateobj, ctx->screen, state, key, true);
1011 setup_stateobj(state->stateobj, ctx->screen, state, key, false);
1012 state->interp_stateobj = create_interp_stateobj(ctx, state);
1013
1014 return &state->base;
1015 }
1016
1017 static void
1018 fd6_program_destroy(void *data, struct ir3_program_state *state)
1019 {
1020 struct fd6_program_state *so = fd6_program_state(state);
1021 fd_ringbuffer_del(so->stateobj);
1022 fd_ringbuffer_del(so->binning_stateobj);
1023 fd_ringbuffer_del(so->config_stateobj);
1024 fd_ringbuffer_del(so->interp_stateobj);
1025 fd_ringbuffer_del(so->streamout_stateobj);
1026 free(so);
1027 }
1028
1029 static const struct ir3_cache_funcs cache_funcs = {
1030 .create_state = fd6_program_create,
1031 .destroy_state = fd6_program_destroy,
1032 };
1033
1034 static void *
1035 fd6_shader_state_create(struct pipe_context *pctx, const struct pipe_shader_state *cso)
1036 {
1037 return ir3_shader_state_create(pctx, cso);
1038 }
1039
1040 static void
1041 fd6_shader_state_delete(struct pipe_context *pctx, void *hwcso)
1042 {
1043 struct fd_context *ctx = fd_context(pctx);
1044 ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
1045 ir3_shader_state_delete(pctx, hwcso);
1046 }
1047
1048 void
1049 fd6_prog_init(struct pipe_context *pctx)
1050 {
1051 struct fd_context *ctx = fd_context(pctx);
1052
1053 fd6_context(ctx)->shader_cache = ir3_cache_create(&cache_funcs, ctx);
1054
1055 pctx->create_vs_state = fd6_shader_state_create;
1056 pctx->delete_vs_state = fd6_shader_state_delete;
1057
1058 pctx->create_tcs_state = fd6_shader_state_create;
1059 pctx->delete_tcs_state = fd6_shader_state_delete;
1060
1061 pctx->create_tes_state = fd6_shader_state_create;
1062 pctx->delete_tes_state = fd6_shader_state_delete;
1063
1064 pctx->create_gs_state = fd6_shader_state_create;
1065 pctx->delete_gs_state = fd6_shader_state_delete;
1066
1067 pctx->create_gs_state = fd6_shader_state_create;
1068 pctx->delete_gs_state = fd6_shader_state_delete;
1069
1070 pctx->create_fs_state = fd6_shader_state_create;
1071 pctx->delete_fs_state = fd6_shader_state_delete;
1072
1073 fd_prog_init(pctx);
1074 }