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freedreno/a6xx: Add generic program stateobj support for HS/DS/GS
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_program.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/u_format.h"
33 #include "util/bitset.h"
34
35 #include "freedreno_program.h"
36
37 #include "fd6_program.h"
38 #include "fd6_emit.h"
39 #include "fd6_texture.h"
40 #include "fd6_format.h"
41
42 void
43 fd6_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
44 {
45 enum a6xx_state_block sb = fd6_stage2shadersb(so->type);
46
47 OUT_PKT7(ring, fd6_stage2opcode(so->type), 3);
48 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
49 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
50 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
51 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
52 CP_LOAD_STATE6_0_NUM_UNIT(so->instrlen));
53 OUT_RELOCD(ring, so->bo, 0, 0, 0);
54 }
55
56 /* Add any missing varyings needed for stream-out. Otherwise varyings not
57 * used by fragment shader will be stripped out.
58 */
59 static void
60 link_stream_out(struct ir3_shader_linkage *l, const struct ir3_shader_variant *v)
61 {
62 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
63
64 /*
65 * First, any stream-out varyings not already in linkage map (ie. also
66 * consumed by frag shader) need to be added:
67 */
68 for (unsigned i = 0; i < strmout->num_outputs; i++) {
69 const struct ir3_stream_output *out = &strmout->output[i];
70 unsigned k = out->register_index;
71 unsigned compmask =
72 (1 << (out->num_components + out->start_component)) - 1;
73 unsigned idx, nextloc = 0;
74
75 /* psize/pos need to be the last entries in linkage map, and will
76 * get added link_stream_out, so skip over them:
77 */
78 if ((v->outputs[k].slot == VARYING_SLOT_PSIZ) ||
79 (v->outputs[k].slot == VARYING_SLOT_POS))
80 continue;
81
82 for (idx = 0; idx < l->cnt; idx++) {
83 if (l->var[idx].regid == v->outputs[k].regid)
84 break;
85 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
86 }
87
88 /* add if not already in linkage map: */
89 if (idx == l->cnt)
90 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
91
92 /* expand component-mask if needed, ie streaming out all components
93 * but frag shader doesn't consume all components:
94 */
95 if (compmask & ~l->var[idx].compmask) {
96 l->var[idx].compmask |= compmask;
97 l->max_loc = MAX2(l->max_loc,
98 l->var[idx].loc + util_last_bit(l->var[idx].compmask));
99 }
100 }
101 }
102
103 static void
104 setup_stream_out(struct fd6_program_state *state, const struct ir3_shader_variant *v,
105 struct ir3_shader_linkage *l)
106 {
107 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
108 struct fd6_streamout_state *tf = &state->tf;
109
110 memset(tf, 0, sizeof(*tf));
111
112 tf->prog_count = align(l->max_loc, 2) / 2;
113
114 debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
115
116 for (unsigned i = 0; i < strmout->num_outputs; i++) {
117 const struct ir3_stream_output *out = &strmout->output[i];
118 unsigned k = out->register_index;
119 unsigned idx;
120
121 tf->ncomp[out->output_buffer] += out->num_components;
122
123 /* linkage map sorted by order frag shader wants things, so
124 * a bit less ideal here..
125 */
126 for (idx = 0; idx < l->cnt; idx++)
127 if (l->var[idx].regid == v->outputs[k].regid)
128 break;
129
130 debug_assert(idx < l->cnt);
131
132 for (unsigned j = 0; j < out->num_components; j++) {
133 unsigned c = j + out->start_component;
134 unsigned loc = l->var[idx].loc + c;
135 unsigned off = j + out->dst_offset; /* in dwords */
136
137 if (loc & 1) {
138 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
139 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
140 A6XX_VPC_SO_PROG_B_OFF(off * 4);
141 } else {
142 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
143 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
144 A6XX_VPC_SO_PROG_A_OFF(off * 4);
145 }
146 }
147 }
148
149 tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
150 COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
151 COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
152 COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
153 COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
154 }
155
156 static void
157 setup_config_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *state)
158 {
159 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
160 OUT_RING(ring, 0xff); /* XXX */
161
162 if (state->ds)
163 debug_assert(state->ds->constlen >= state->bs->constlen);
164 else
165 debug_assert(state->vs->constlen >= state->bs->constlen);
166
167 OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
168 OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(state->vs->constlen, 4)) |
169 A6XX_HLSQ_VS_CNTL_ENABLED);
170 OUT_RING(ring, COND(state->hs,
171 A6XX_HLSQ_HS_CNTL_ENABLED |
172 A6XX_HLSQ_HS_CNTL_CONSTLEN(align(state->hs->constlen, 4))));
173 OUT_RING(ring, COND(state->ds,
174 A6XX_HLSQ_DS_CNTL_ENABLED |
175 A6XX_HLSQ_DS_CNTL_CONSTLEN(align(state->ds->constlen, 4))));
176 OUT_RING(ring, COND(state->gs,
177 A6XX_HLSQ_GS_CNTL_ENABLED |
178 A6XX_HLSQ_GS_CNTL_CONSTLEN(align(state->gs->constlen, 4))));
179 OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL, 1);
180 OUT_RING(ring, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(state->fs->constlen, 4)) |
181 A6XX_HLSQ_FS_CNTL_ENABLED);
182
183 OUT_PKT4(ring, REG_A6XX_SP_VS_CONFIG, 1);
184 OUT_RING(ring, COND(state->vs, A6XX_SP_VS_CONFIG_ENABLED) |
185 A6XX_SP_VS_CONFIG_NIBO(state->vs->image_mapping.num_ibo) |
186 A6XX_SP_VS_CONFIG_NTEX(state->vs->num_samp) |
187 A6XX_SP_VS_CONFIG_NSAMP(state->vs->num_samp));
188
189 OUT_PKT4(ring, REG_A6XX_SP_HS_CONFIG, 1);
190 OUT_RING(ring, COND(state->hs,
191 A6XX_SP_HS_CONFIG_ENABLED |
192 A6XX_SP_HS_CONFIG_NIBO(state->hs->image_mapping.num_ibo) |
193 A6XX_SP_HS_CONFIG_NTEX(state->hs->num_samp) |
194 A6XX_SP_HS_CONFIG_NSAMP(state->hs->num_samp)));
195
196 OUT_PKT4(ring, REG_A6XX_SP_DS_CONFIG, 1);
197 OUT_RING(ring, COND(state->ds,
198 A6XX_SP_DS_CONFIG_ENABLED |
199 A6XX_SP_DS_CONFIG_NIBO(state->ds->image_mapping.num_ibo) |
200 A6XX_SP_DS_CONFIG_NTEX(state->ds->num_samp) |
201 A6XX_SP_DS_CONFIG_NSAMP(state->ds->num_samp)));
202
203 OUT_PKT4(ring, REG_A6XX_SP_GS_CONFIG, 1);
204 OUT_RING(ring, COND(state->gs,
205 A6XX_SP_GS_CONFIG_ENABLED |
206 A6XX_SP_GS_CONFIG_NIBO(state->gs->image_mapping.num_ibo) |
207 A6XX_SP_GS_CONFIG_NTEX(state->gs->num_samp) |
208 A6XX_SP_GS_CONFIG_NSAMP(state->gs->num_samp)));
209
210 OUT_PKT4(ring, REG_A6XX_SP_FS_CONFIG, 1);
211 OUT_RING(ring, COND(state->fs, A6XX_SP_FS_CONFIG_ENABLED) |
212 A6XX_SP_FS_CONFIG_NIBO(state->fs->image_mapping.num_ibo) |
213 A6XX_SP_FS_CONFIG_NTEX(state->fs->num_samp) |
214 A6XX_SP_FS_CONFIG_NSAMP(state->fs->num_samp));
215
216 OUT_PKT4(ring, REG_A6XX_SP_IBO_COUNT, 1);
217 OUT_RING(ring, state->fs->image_mapping.num_ibo);
218 }
219
220 #define VALIDREG(r) ((r) != regid(63,0))
221 #define CONDREG(r, val) COND(VALIDREG(r), (val))
222
223 static inline uint32_t
224 next_regid(uint32_t reg, uint32_t increment)
225 {
226 if (VALIDREG(reg))
227 return reg + increment;
228 else
229 return regid(63,0);
230 }
231
232 static void
233 setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
234 struct fd6_program_state *state, const struct ir3_shader_key *key,
235 bool binning_pass)
236 {
237 uint32_t pos_regid, psize_regid, color_regid[8], posz_regid;
238 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
239 uint32_t smask_in_regid, smask_regid;
240 uint32_t vertex_regid, instance_regid;
241 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
242 enum a3xx_threadsize fssz;
243 uint8_t psize_loc = ~0, pos_loc = ~0;
244 int i, j;
245
246 static const struct ir3_shader_variant dummy_fs = {0};
247 const struct ir3_shader_variant *vs = binning_pass ? state->bs : state->vs;
248 const struct ir3_shader_variant *hs = state->hs;
249 const struct ir3_shader_variant *ds = state->ds;
250 const struct ir3_shader_variant *gs = state->gs;
251 const struct ir3_shader_variant *fs = binning_pass ? &dummy_fs : state->fs;
252
253 bool sample_shading = fs->per_samp | key->sample_shading;
254
255 fssz = FOUR_QUADS;
256
257 pos_regid = ir3_find_output_regid(vs, VARYING_SLOT_POS);
258 psize_regid = ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
259 vertex_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
260 instance_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
261
262 if (fs->color0_mrt) {
263 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
264 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
265 ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
266 } else {
267 color_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0);
268 color_regid[1] = ir3_find_output_regid(fs, FRAG_RESULT_DATA1);
269 color_regid[2] = ir3_find_output_regid(fs, FRAG_RESULT_DATA2);
270 color_regid[3] = ir3_find_output_regid(fs, FRAG_RESULT_DATA3);
271 color_regid[4] = ir3_find_output_regid(fs, FRAG_RESULT_DATA4);
272 color_regid[5] = ir3_find_output_regid(fs, FRAG_RESULT_DATA5);
273 color_regid[6] = ir3_find_output_regid(fs, FRAG_RESULT_DATA6);
274 color_regid[7] = ir3_find_output_regid(fs, FRAG_RESULT_DATA7);
275 }
276
277 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
278 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
279 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
280 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
281 zwcoord_regid = next_regid(coord_regid, 2);
282 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PIXEL);
283 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_SAMPLE);
284 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_CENTROID);
285 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_SIZE);
286 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
287 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
288
289 /* we can't write gl_SampleMask for !msaa.. if b0 is zero then we
290 * end up masking the single sample!!
291 */
292 if (!key->msaa)
293 smask_regid = regid(63, 0);
294
295 /* we could probably divide this up into things that need to be
296 * emitted if frag-prog is dirty vs if vert-prog is dirty..
297 */
298
299 OUT_PKT4(ring, REG_A6XX_SP_VS_INSTRLEN, 1);
300 OUT_RING(ring, vs->instrlen); /* SP_VS_INSTRLEN */
301
302 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
303 OUT_RING(ring, 0);
304
305 OUT_PKT4(ring, REG_A6XX_SP_HS_INSTRLEN, 1);
306 OUT_RING(ring, 0); /* SP_HS_INSTRLEN */
307
308 OUT_PKT4(ring, REG_A6XX_SP_DS_INSTRLEN, 1);
309 OUT_RING(ring, 0); /* SP_DS_INSTRLEN */
310
311 OUT_PKT4(ring, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
312 OUT_RING(ring, 0);
313
314 OUT_PKT4(ring, REG_A6XX_SP_GS_INSTRLEN, 1);
315 OUT_RING(ring, 0); /* SP_GS_INSTRLEN */
316
317 /* I believe this is related to pre-dispatch texture fetch.. we probably
318 * should't turn it on by accident:
319 */
320 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A99E, 1);
321 OUT_RING(ring, 0x0);
322
323 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A9A8, 1);
324 OUT_RING(ring, 0);
325
326 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_AB00, 1);
327 OUT_RING(ring, 0x5);
328
329 OUT_PKT4(ring, REG_A6XX_SP_FS_INSTRLEN, 1);
330 OUT_RING(ring, fs->instrlen); /* SP_FS_INSTRLEN */
331
332 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL0, 1);
333 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
334 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
335 0xfc000000);
336
337 OUT_PKT4(ring, REG_A6XX_SP_VS_CTRL_REG0, 1);
338 OUT_RING(ring, A6XX_SP_VS_CTRL_REG0_THREADSIZE(fssz) |
339 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
340 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
341 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack) |
342 COND(vs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE));
343
344 struct ir3_shader_linkage l = {0};
345 ir3_link_shaders(&l, vs, fs);
346
347 if (vs->shader->stream_output.num_outputs > 0)
348 link_stream_out(&l, vs);
349
350 BITSET_DECLARE(varbs, 128) = {0};
351 uint32_t *varmask = (uint32_t *)varbs;
352
353 for (i = 0; i < l.cnt; i++)
354 for (j = 0; j < util_last_bit(l.var[i].compmask); j++)
355 BITSET_SET(varbs, l.var[i].loc + j);
356
357 OUT_PKT4(ring, REG_A6XX_VPC_VAR_DISABLE(0), 4);
358 OUT_RING(ring, ~varmask[0]); /* VPC_VAR[0].DISABLE */
359 OUT_RING(ring, ~varmask[1]); /* VPC_VAR[1].DISABLE */
360 OUT_RING(ring, ~varmask[2]); /* VPC_VAR[2].DISABLE */
361 OUT_RING(ring, ~varmask[3]); /* VPC_VAR[3].DISABLE */
362
363 /* a6xx appends pos/psize to end of the linkage map: */
364 if (VALIDREG(pos_regid)) {
365 pos_loc = l.max_loc;
366 ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
367 }
368
369 if (VALIDREG(psize_regid)) {
370 psize_loc = l.max_loc;
371 ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
372 }
373
374 if (vs->shader->stream_output.num_outputs > 0) {
375 setup_stream_out(state, vs, &l);
376 }
377
378 debug_assert(l.cnt < 32);
379 OUT_PKT4(ring, REG_A6XX_SP_VS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
380 for (j = 0; j < l.cnt; ) {
381 uint32_t reg = 0;
382
383 reg |= A6XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
384 reg |= A6XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
385 j++;
386
387 reg |= A6XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
388 reg |= A6XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
389 j++;
390
391 OUT_RING(ring, reg);
392 }
393
394 OUT_PKT4(ring, REG_A6XX_SP_VS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
395 for (j = 0; j < l.cnt; ) {
396 uint32_t reg = 0;
397
398 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
399 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
400 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
401 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
402
403 OUT_RING(ring, reg);
404 }
405
406 OUT_PKT4(ring, REG_A6XX_SP_VS_OBJ_START_LO, 2);
407 OUT_RELOC(ring, vs->bo, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
408
409 if (vs->instrlen)
410 fd6_emit_shader(ring, vs);
411
412
413 OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
414 OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
415
416 bool enable_varyings = fs->total_in > 0;
417
418 OUT_PKT4(ring, REG_A6XX_VPC_CNTL_0, 1);
419 OUT_RING(ring, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
420 COND(enable_varyings, A6XX_VPC_CNTL_0_VARYING) |
421 0xff00ff00);
422
423 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
424 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l.max_loc) |
425 CONDREG(psize_regid, A6XX_PC_PRIMITIVE_CNTL_1_PSIZE));
426
427 if (binning_pass) {
428 OUT_PKT4(ring, REG_A6XX_SP_FS_OBJ_START_LO, 2);
429 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_LO */
430 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_HI */
431 } else {
432 OUT_PKT4(ring, REG_A6XX_SP_FS_OBJ_START_LO, 2);
433 OUT_RELOC(ring, fs->bo, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
434 }
435
436 OUT_PKT4(ring, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
437 OUT_RING(ring, 0x7); /* XXX */
438 OUT_RING(ring, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
439 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
440 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
441 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
442 OUT_RING(ring, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
443 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
444 0xfc00fc00); /* XXX */
445 OUT_RING(ring, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
446 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
447 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
448 0x0000fc00); /* XXX */
449 OUT_RING(ring, 0xfc); /* XXX */
450
451 OUT_PKT4(ring, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
452 OUT_RING(ring, enable_varyings ? 3 : 1);
453
454 OUT_PKT4(ring, REG_A6XX_SP_FS_CTRL_REG0, 1);
455 OUT_RING(ring, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
456 COND(enable_varyings, A6XX_SP_FS_CTRL_REG0_VARYING) |
457 COND(fs->frag_coord, A6XX_SP_FS_CTRL_REG0_VARYING) |
458 0x1000000 |
459 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
460 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
461 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack) |
462 COND(fs->need_pixlod, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE));
463
464 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A982, 1);
465 OUT_RING(ring, 0); /* XXX */
466
467 OUT_PKT4(ring, REG_A6XX_VPC_GS_SIV_CNTL, 1);
468 OUT_RING(ring, 0x0000ffff); /* XXX */
469
470 OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
471 OUT_RING(ring,
472 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
473 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
474 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
475 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
476 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
477 COND(fs->frag_coord,
478 A6XX_GRAS_CNTL_SIZE |
479 A6XX_GRAS_CNTL_XCOORD |
480 A6XX_GRAS_CNTL_YCOORD |
481 A6XX_GRAS_CNTL_ZCOORD |
482 A6XX_GRAS_CNTL_WCOORD) |
483 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
484
485 OUT_PKT4(ring, REG_A6XX_RB_RENDER_CONTROL0, 2);
486 OUT_RING(ring,
487 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
488 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
489 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
490 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
491 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
492 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
493 COND(fs->frag_coord,
494 A6XX_RB_RENDER_CONTROL0_SIZE |
495 A6XX_RB_RENDER_CONTROL0_XCOORD |
496 A6XX_RB_RENDER_CONTROL0_YCOORD |
497 A6XX_RB_RENDER_CONTROL0_ZCOORD |
498 A6XX_RB_RENDER_CONTROL0_WCOORD) |
499 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
500
501 OUT_RING(ring,
502 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
503 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
504 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
505 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
506
507 OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_CNTL, 1);
508 OUT_RING(ring, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
509
510 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8101, 1);
511 OUT_RING(ring, COND(sample_shading, 0x6)); // XXX
512
513 OUT_PKT4(ring, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
514 OUT_RING(ring, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
515
516 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
517 for (i = 0; i < 8; i++) {
518 OUT_RING(ring, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
519 COND(color_regid[i] & HALF_REG_ID, A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
520 }
521
522 OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
523 OUT_RING(ring, A6XX_VPC_PACK_POSITIONLOC(pos_loc) |
524 A6XX_VPC_PACK_PSIZELOC(psize_loc) |
525 A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
526
527 if (!binning_pass) {
528 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
529 for (j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
530 /* NOTE: varyings are packed, so if compmask is 0xb
531 * then first, third, and fourth component occupy
532 * three consecutive varying slots:
533 */
534 unsigned compmask = fs->inputs[j].compmask;
535
536 uint32_t inloc = fs->inputs[j].inloc;
537
538 if (fs->inputs[j].interpolate == INTERP_MODE_FLAT) {
539 uint32_t loc = inloc;
540
541 for (i = 0; i < 4; i++) {
542 if (compmask & (1 << i)) {
543 state->vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
544 loc++;
545 }
546 }
547 }
548 }
549 }
550
551 if (!binning_pass)
552 if (fs->instrlen)
553 fd6_emit_shader(ring, fs);
554
555 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_1, 6);
556 OUT_RING(ring, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
557 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
558 0xfcfc0000);
559 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_2 */
560 OUT_RING(ring, 0xfcfcfcfc); /* VFD_CONTROL_3 */
561 OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
562 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_5 */
563 OUT_RING(ring, 0x00000000); /* VFD_CONTROL_6 */
564
565 bool fragz = fs->no_earlyz | fs->writes_pos;
566
567 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
568 OUT_RING(ring, COND(fragz, A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));
569
570 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
571 OUT_RING(ring, COND(fragz, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));
572
573 ir3_emit_immediates(screen, vs, ring);
574
575 if (hs) {
576 ir3_emit_immediates(screen, hs, ring);
577 ir3_emit_immediates(screen, ds, ring);
578 }
579
580 if (gs) {
581 ir3_emit_immediates(screen, gs, ring);
582 }
583
584 if (!binning_pass)
585 ir3_emit_immediates(screen, fs, ring);
586 }
587
588 /* emits the program state which is not part of the stateobj because of
589 * dependency on other gl state (rasterflat or sprite-coord-replacement)
590 */
591 void
592 fd6_program_emit(struct fd_ringbuffer *ring, struct fd6_emit *emit)
593 {
594 const struct fd6_program_state *state = fd6_emit_get_prog(emit);
595
596 if (!unlikely(emit->rasterflat || emit->sprite_coord_enable)) {
597 /* fastpath: */
598 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
599 for (int i = 0; i < 8; i++)
600 OUT_RING(ring, state->vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
601
602 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
603 for (int i = 0; i < 8; i++)
604 OUT_RING(ring, 0x00000000); /* VPC_VARYING_PS_REPL[i] */
605 } else {
606 /* slow-path: */
607 struct ir3_shader_variant *fs = state->fs;
608 uint32_t vinterp[8], vpsrepl[8];
609
610 memset(vinterp, 0, sizeof(vinterp));
611 memset(vpsrepl, 0, sizeof(vpsrepl));
612
613 for (int j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
614
615 /* NOTE: varyings are packed, so if compmask is 0xb
616 * then first, third, and fourth component occupy
617 * three consecutive varying slots:
618 */
619 unsigned compmask = fs->inputs[j].compmask;
620
621 uint32_t inloc = fs->inputs[j].inloc;
622
623 if ((fs->inputs[j].interpolate == INTERP_MODE_FLAT) ||
624 (fs->inputs[j].rasterflat && emit->rasterflat)) {
625 uint32_t loc = inloc;
626
627 for (int i = 0; i < 4; i++) {
628 if (compmask & (1 << i)) {
629 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
630 loc++;
631 }
632 }
633 }
634
635 gl_varying_slot slot = fs->inputs[j].slot;
636
637 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
638 if (slot >= VARYING_SLOT_VAR0) {
639 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
640 /* Replace the .xy coordinates with S/T from the point sprite. Set
641 * interpolation bits for .zw such that they become .01
642 */
643 if (emit->sprite_coord_enable & texmask) {
644 /* mask is two 2-bit fields, where:
645 * '01' -> S
646 * '10' -> T
647 * '11' -> 1 - T (flip mode)
648 */
649 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
650 uint32_t loc = inloc;
651 if (compmask & 0x1) {
652 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
653 loc++;
654 }
655 if (compmask & 0x2) {
656 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
657 loc++;
658 }
659 if (compmask & 0x4) {
660 /* .z <- 0.0f */
661 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
662 loc++;
663 }
664 if (compmask & 0x8) {
665 /* .w <- 1.0f */
666 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
667 loc++;
668 }
669 }
670 }
671 }
672
673 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
674 for (int i = 0; i < 8; i++)
675 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
676
677 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
678 for (int i = 0; i < 8; i++)
679 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
680 }
681 }
682
683 static struct ir3_program_state *
684 fd6_program_create(void *data, struct ir3_shader_variant *bs,
685 struct ir3_shader_variant *vs,
686 struct ir3_shader_variant *hs,
687 struct ir3_shader_variant *ds,
688 struct ir3_shader_variant *gs,
689 struct ir3_shader_variant *fs,
690 const struct ir3_shader_key *key)
691 {
692 struct fd_context *ctx = data;
693 struct fd6_program_state *state = CALLOC_STRUCT(fd6_program_state);
694
695 /* if we have streamout, use full VS in binning pass, as the
696 * binning pass VS will have outputs on other than position/psize
697 * stripped out:
698 */
699 state->bs = vs->shader->stream_output.num_outputs ? vs : bs;
700 state->vs = vs;
701 state->hs = hs;
702 state->ds = ds;
703 state->gs = gs;
704 state->fs = fs;
705 state->config_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
706 state->binning_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
707 state->stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
708
709 #ifdef DEBUG
710 if (!ds) {
711 for (unsigned i = 0; i < bs->inputs_count; i++) {
712 if (vs->inputs[i].sysval)
713 continue;
714 debug_assert(bs->inputs[i].regid == vs->inputs[i].regid);
715 }
716 }
717 #endif
718
719 setup_config_stateobj(state->config_stateobj, state);
720 setup_stateobj(state->binning_stateobj, ctx->screen, state, key, true);
721 setup_stateobj(state->stateobj, ctx->screen, state, key, false);
722
723 return &state->base;
724 }
725
726 static void
727 fd6_program_destroy(void *data, struct ir3_program_state *state)
728 {
729 struct fd6_program_state *so = fd6_program_state(state);
730 fd_ringbuffer_del(so->stateobj);
731 fd_ringbuffer_del(so->binning_stateobj);
732 fd_ringbuffer_del(so->config_stateobj);
733 free(so);
734 }
735
736 static const struct ir3_cache_funcs cache_funcs = {
737 .create_state = fd6_program_create,
738 .destroy_state = fd6_program_destroy,
739 };
740
741 static void *
742 fd6_shader_state_create(struct pipe_context *pctx, const struct pipe_shader_state *cso)
743 {
744 struct fd_context *ctx = fd_context(pctx);
745 struct ir3_compiler *compiler = ctx->screen->compiler;
746 struct ir3_shader *shader =
747 ir3_shader_create(compiler, cso, &ctx->debug, pctx->screen);
748 unsigned packets, size;
749
750 /* pre-calculate size required for userconst stateobj: */
751 ir3_user_consts_size(&shader->ubo_state, &packets, &size);
752
753 /* also account for UBO addresses: */
754 packets += 1;
755 size += 2 * shader->const_state.num_ubos;
756
757 unsigned sizedwords = (4 * packets) + size;
758 shader->ubo_state.cmdstream_size = sizedwords * 4;
759
760 return shader;
761 }
762
763 static void
764 fd6_shader_state_delete(struct pipe_context *pctx, void *hwcso)
765 {
766 struct ir3_shader *so = hwcso;
767 struct fd_context *ctx = fd_context(pctx);
768 ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
769 ir3_shader_destroy(so);
770 }
771
772 void
773 fd6_prog_init(struct pipe_context *pctx)
774 {
775 struct fd_context *ctx = fd_context(pctx);
776
777 fd6_context(ctx)->shader_cache = ir3_cache_create(&cache_funcs, ctx);
778
779 pctx->create_vs_state = fd6_shader_state_create;
780 pctx->delete_vs_state = fd6_shader_state_delete;
781
782 pctx->create_tcs_state = fd6_shader_state_create;
783 pctx->delete_tcs_state = fd6_shader_state_delete;
784
785 pctx->create_tes_state = fd6_shader_state_create;
786 pctx->delete_tes_state = fd6_shader_state_delete;
787
788 pctx->create_gs_state = fd6_shader_state_create;
789 pctx->delete_gs_state = fd6_shader_state_delete;
790
791 pctx->create_fs_state = fd6_shader_state_create;
792 pctx->delete_fs_state = fd6_shader_state_delete;
793
794 fd_prog_init(pctx);
795 }