src/gallium/drivers/freedreno/freedreno_context.h

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #ifndef FREEDRENO_CONTEXT_H_
  30 #define FREEDRENO_CONTEXT_H_
  31
  32 #include "pipe/p_context.h"
  33 #include "indices/u_primconvert.h"
  34 #include "util/u_blitter.h"
  35 #include "util/list.h"
  36 #include "util/u_slab.h"
  37 #include "util/u_string.h"
  38
  39 #include "freedreno_screen.h"
  40 #include "freedreno_gmem.h"
  41 #include "freedreno_util.h"
  42
  43 struct fd_vertex_stateobj;
  44
  45 struct fd_texture_stateobj {
  46         struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS];
  47         unsigned num_textures;
  48         struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS];
  49         unsigned num_samplers;
  50         unsigned dirty_samplers;
  51 };
  52
  53 struct fd_program_stateobj {
  54         void *vp, *fp;
  55         enum {
  56                 FD_SHADER_DIRTY_VP = (1 << 0),
  57                 FD_SHADER_DIRTY_FP = (1 << 1),
  58         } dirty;
  59         uint8_t num_exports;
  60         /* Indexed by semantic name or TGSI_SEMANTIC_COUNT + semantic index
  61          * for TGSI_SEMANTIC_GENERIC.  Special vs exports (position and point-
  62          * size) are not included in this
  63          */
  64         uint8_t export_linkage[63];
  65 };
  66
  67 struct fd_constbuf_stateobj {
  68         struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
  69         uint32_t enabled_mask;
  70         uint32_t dirty_mask;
  71 };
  72
  73 struct fd_vertexbuf_stateobj {
  74         struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
  75         unsigned count;
  76         uint32_t enabled_mask;
  77         uint32_t dirty_mask;
  78 };
  79
  80 struct fd_vertex_stateobj {
  81         struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
  82         unsigned num_elements;
  83 };
  84
  85 struct fd_streamout_stateobj {
  86         struct pipe_stream_output_target *targets[PIPE_MAX_SO_BUFFERS];
  87         unsigned num_targets;
  88         /* Track offset from vtxcnt for streamout data.  This counter
  89          * is just incremented by # of vertices on each draw until
  90          * reset or new streamout buffer bound.
  91          *
  92          * When we eventually have GS, the CPU won't actually know the
  93          * number of vertices per draw, so I think we'll have to do
  94          * something more clever.
  95          */
  96         unsigned offsets[PIPE_MAX_SO_BUFFERS];
  97 };
  98
  99 /* group together the vertex and vertexbuf state.. for ease of passing
 100  * around, and because various internal operations (gmem<->mem, etc)
 101  * need their own vertex state:
 102  */
 103 struct fd_vertex_state {
 104         struct fd_vertex_stateobj *vtx;
 105         struct fd_vertexbuf_stateobj vertexbuf;
 106 };
 107
 108 /* Bitmask of stages in rendering that a particular query query is
 109  * active.  Queries will be automatically started/stopped (generating
 110  * additional fd_hw_sample_period's) on entrance/exit from stages that
 111  * are applicable to the query.
 112  *
 113  * NOTE: set the stage to NULL at end of IB to ensure no query is still
 114  * active.  Things aren't going to work out the way you want if a query
 115  * is active across IB's (or between tile IB and draw IB)
 116  */
 117 enum fd_render_stage {
 118         FD_STAGE_NULL     = 0x00,
 119         FD_STAGE_DRAW     = 0x01,
 120         FD_STAGE_CLEAR    = 0x02,
 121         /* TODO before queries which include MEM2GMEM or GMEM2MEM will
 122          * work we will need to call fd_hw_query_prepare() from somewhere
 123          * appropriate so that queries in the tiling IB get backed with
 124          * memory to write results to.
 125          */
 126         FD_STAGE_MEM2GMEM = 0x04,
 127         FD_STAGE_GMEM2MEM = 0x08,
 128         /* used for driver internal draws (ie. util_blitter_blit()): */
 129         FD_STAGE_BLIT     = 0x10,
 130 };
 131
 132 #define MAX_HW_SAMPLE_PROVIDERS 4
 133 struct fd_hw_sample_provider;
 134 struct fd_hw_sample;
 135
 136 struct fd_context {
 137         struct pipe_context base;
 138
 139         struct fd_device *dev;
 140         struct fd_screen *screen;
 141
 142         struct blitter_context *blitter;
 143         struct primconvert_context *primconvert;
 144
 145         /* slab for pipe_transfer allocations: */
 146         struct util_slab_mempool transfer_pool;
 147
 148         /* slabs for fd_hw_sample and fd_hw_sample_period allocations: */
 149         struct util_slab_mempool sample_pool;
 150         struct util_slab_mempool sample_period_pool;
 151
 152         /* next sample offset.. incremented for each sample in the batch/
 153          * submit, reset to zero on next submit.
 154          */
 155         uint32_t next_sample_offset;
 156
 157         /* sample-providers for hw queries: */
 158         const struct fd_hw_sample_provider *sample_providers[MAX_HW_SAMPLE_PROVIDERS];
 159
 160         /* cached samples (in case multiple queries need to reference
 161          * the same sample snapshot)
 162          */
 163         struct fd_hw_sample *sample_cache[MAX_HW_SAMPLE_PROVIDERS];
 164
 165         /* tracking for current stage, to know when to start/stop
 166          * any active queries:
 167          */
 168         enum fd_render_stage stage;
 169
 170         /* list of active queries: */
 171         struct list_head active_queries;
 172
 173         /* list of queries that are not active, but were active in the
 174          * current submit:
 175          */
 176         struct list_head current_queries;
 177
 178         /* current query result bo and tile stride: */
 179         struct fd_bo *query_bo;
 180         uint32_t query_tile_stride;
 181
 182         /* list of resources used by currently-unsubmitted renders */
 183         struct list_head used_resources;
 184
 185         /* table with PIPE_PRIM_MAX entries mapping PIPE_PRIM_x to
 186          * DI_PT_x value to use for draw initiator.  There are some
 187          * slight differences between generation:
 188          */
 189         const uint8_t *primtypes;
 190         uint32_t primtype_mask;
 191
 192         /* shaders used by clear, and gmem->mem blits: */
 193         struct fd_program_stateobj solid_prog; // TODO move to screen?
 194
 195         /* shaders used by mem->gmem blits: */
 196         struct fd_program_stateobj blit_prog[MAX_RENDER_TARGETS]; // TODO move to screen?
 197         struct fd_program_stateobj blit_z, blit_zs;
 198
 199         /* do we need to mem2gmem before rendering.  We don't, if for example,
 200          * there was a glClear() that invalidated the entire previous buffer
 201          * contents.  Keep track of which buffer(s) are cleared, or needs
 202          * restore.  Masks of PIPE_CLEAR_*
 203          *
 204          * The 'cleared' bits will be set for buffers which are *entirely*
 205          * cleared, and 'partial_cleared' bits will be set if you must
 206          * check cleared_scissor.
 207          */
 208         enum {
 209                 /* align bitmask values w/ PIPE_CLEAR_*.. since that is convenient.. */
 210                 FD_BUFFER_COLOR   = PIPE_CLEAR_COLOR,
 211                 FD_BUFFER_DEPTH   = PIPE_CLEAR_DEPTH,
 212                 FD_BUFFER_STENCIL = PIPE_CLEAR_STENCIL,
 213                 FD_BUFFER_ALL     = FD_BUFFER_COLOR | FD_BUFFER_DEPTH | FD_BUFFER_STENCIL,
 214         } cleared, partial_cleared, restore, resolve;
 215
 216         bool needs_flush;
 217
 218         /* To decide whether to render to system memory, keep track of the
 219          * number of draws, and whether any of them require multisample,
 220          * depth_test (or depth write), stencil_test, blending, and
 221          * color_logic_Op (since those functions are disabled when by-
 222          * passing GMEM.
 223          */
 224         enum {
 225                 FD_GMEM_CLEARS_DEPTH_STENCIL = 0x01,
 226                 FD_GMEM_DEPTH_ENABLED        = 0x02,
 227                 FD_GMEM_STENCIL_ENABLED      = 0x04,
 228
 229                 FD_GMEM_MSAA_ENABLED         = 0x08,
 230                 FD_GMEM_BLEND_ENABLED        = 0x10,
 231                 FD_GMEM_LOGICOP_ENABLED      = 0x20,
 232         } gmem_reason;
 233         unsigned num_draws;   /* number of draws in current batch */
 234
 235         /* Stats/counters:
 236          */
 237         struct {
 238                 uint64_t prims_emitted;
 239                 uint64_t draw_calls;
 240                 uint64_t batch_total, batch_sysmem, batch_gmem, batch_restore;
 241         } stats;
 242
 243         /* we can't really sanely deal with wraparound point in ringbuffer
 244          * and because of the way tiling works we can't really flush at
 245          * arbitrary points (without a big performance hit).  When we get
 246          * too close to the end of the current ringbuffer, cycle to the next
 247          * one (and wait for pending rendering from next rb to complete).
 248          * We want the # of ringbuffers to be high enough that we don't
 249          * normally have to wait before resetting to the start of the next
 250          * rb.
 251          */
 252         struct fd_ringbuffer *rings[8];
 253         unsigned rings_idx;
 254
 255         /* NOTE: currently using a single ringbuffer for both draw and
 256          * tiling commands, we need to make sure we need to leave enough
 257          * room at the end to append the tiling commands when we flush.
 258          * 0x7000 dwords should be a couple times more than we ever need
 259          * so should be a nice conservative threshold.
 260          */
 261 #define FD_TILING_COMMANDS_DWORDS 0x7000
 262
 263         /* normal draw/clear cmds: */
 264         struct fd_ringbuffer *ring;
 265         struct fd_ringmarker *draw_start, *draw_end;
 266
 267         /* binning pass draw/clear cmds: */
 268         struct fd_ringbuffer *binning_ring;
 269         struct fd_ringmarker *binning_start, *binning_end;
 270
 271         /* Keep track if WAIT_FOR_IDLE is needed for registers we need
 272          * to update via RMW:
 273          */
 274         bool needs_wfi;
 275
 276         /* Do we need to re-emit RB_FRAME_BUFFER_DIMENSION?  At least on a3xx
 277          * it is not a banked context register, so it needs a WFI to update.
 278          * Keep track if it has actually changed, to avoid unneeded WFI.
 279          * */
 280         bool needs_rb_fbd;
 281
 282         /* Keep track of DRAW initiators that need to be patched up depending
 283          * on whether we using binning or not:
 284          */
 285         struct util_dynarray draw_patches;
 286
 287         struct pipe_scissor_state scissor;
 288
 289         /* we don't have a disable/enable bit for scissor, so instead we keep
 290          * a disabled-scissor state which matches the entire bound framebuffer
 291          * and use that when scissor is not enabled.
 292          */
 293         struct pipe_scissor_state disabled_scissor;
 294
 295         /* Track the maximal bounds of the scissor of all the draws within a
 296          * batch.  Used at the tile rendering step (fd_gmem_render_tiles(),
 297          * mem2gmem/gmem2mem) to avoid needlessly moving data in/out of gmem.
 298          */
 299         struct pipe_scissor_state max_scissor;
 300
 301         /* Track the cleared scissor for color/depth/stencil, so we know
 302          * which, if any, tiles need to be restored (mem2gmem).  Only valid
 303          * if the corresponding bit in ctx->cleared is set.
 304          */
 305         struct {
 306                 struct pipe_scissor_state color, depth, stencil;
 307         } cleared_scissor;
 308
 309         /* Current gmem/tiling configuration.. gets updated on render_tiles()
 310          * if out of date with current maximal-scissor/cpp:
 311          */
 312         struct fd_gmem_stateobj gmem;
 313         struct fd_vsc_pipe      pipe[8];
 314         struct fd_tile          tile[256];
 315
 316         /* which state objects need to be re-emit'd: */
 317         enum {
 318                 FD_DIRTY_BLEND       = (1 <<  0),
 319                 FD_DIRTY_RASTERIZER  = (1 <<  1),
 320                 FD_DIRTY_ZSA         = (1 <<  2),
 321                 FD_DIRTY_FRAGTEX     = (1 <<  3),
 322                 FD_DIRTY_VERTTEX     = (1 <<  4),
 323                 FD_DIRTY_TEXSTATE    = (1 <<  5),
 324                 FD_DIRTY_PROG        = (1 <<  6),
 325                 FD_DIRTY_BLEND_COLOR = (1 <<  7),
 326                 FD_DIRTY_STENCIL_REF = (1 <<  8),
 327                 FD_DIRTY_SAMPLE_MASK = (1 <<  9),
 328                 FD_DIRTY_FRAMEBUFFER = (1 << 10),
 329                 FD_DIRTY_STIPPLE     = (1 << 11),
 330                 FD_DIRTY_VIEWPORT    = (1 << 12),
 331                 FD_DIRTY_CONSTBUF    = (1 << 13),
 332                 FD_DIRTY_VTXSTATE    = (1 << 14),
 333                 FD_DIRTY_VTXBUF      = (1 << 15),
 334                 FD_DIRTY_INDEXBUF    = (1 << 16),
 335                 FD_DIRTY_SCISSOR     = (1 << 17),
 336                 FD_DIRTY_STREAMOUT   = (1 << 18),
 337                 FD_DIRTY_UCP         = (1 << 19),
 338                 FD_DIRTY_BLEND_DUAL  = (1 << 20),
 339         } dirty;
 340
 341         struct pipe_blend_state *blend;
 342         struct pipe_rasterizer_state *rasterizer;
 343         struct pipe_depth_stencil_alpha_state *zsa;
 344
 345         struct fd_texture_stateobj verttex, fragtex;
 346
 347         struct fd_program_stateobj prog;
 348
 349         struct fd_vertex_state vtx;
 350
 351         struct pipe_blend_color blend_color;
 352         struct pipe_stencil_ref stencil_ref;
 353         unsigned sample_mask;
 354         struct pipe_framebuffer_state framebuffer;
 355         struct pipe_poly_stipple stipple;
 356         struct pipe_viewport_state viewport;
 357         struct fd_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
 358         struct pipe_index_buffer indexbuf;
 359         struct fd_streamout_stateobj streamout;
 360         struct pipe_clip_state ucp;
 361
 362         struct pipe_query *cond_query;
 363         bool cond_cond; /* inverted rendering condition */
 364         uint cond_mode;
 365
 366         /* GMEM/tile handling fxns: */
 367         void (*emit_tile_init)(struct fd_context *ctx);
 368         void (*emit_tile_prep)(struct fd_context *ctx, struct fd_tile *tile);
 369         void (*emit_tile_mem2gmem)(struct fd_context *ctx, struct fd_tile *tile);
 370         void (*emit_tile_renderprep)(struct fd_context *ctx, struct fd_tile *tile);
 371         void (*emit_tile_gmem2mem)(struct fd_context *ctx, struct fd_tile *tile);
 372
 373         /* optional, for GMEM bypass: */
 374         void (*emit_sysmem_prep)(struct fd_context *ctx);
 375
 376         /* draw: */
 377         void (*draw_vbo)(struct fd_context *ctx, const struct pipe_draw_info *info);
 378         void (*clear)(struct fd_context *ctx, unsigned buffers,
 379                         const union pipe_color_union *color, double depth, unsigned stencil);
 380
 381         /* constant emit:  (note currently not used/needed for a2xx) */
 382         void (*emit_const)(struct fd_ringbuffer *ring, enum shader_t type,
 383                         uint32_t regid, uint32_t offset, uint32_t sizedwords,
 384                         const uint32_t *dwords, struct pipe_resource *prsc);
 385         void (*emit_const_bo)(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
 386                         uint32_t regid, uint32_t num, struct fd_bo **bos, uint32_t *offsets);
 387 };
 388
 389 static inline struct fd_context *
 390 fd_context(struct pipe_context *pctx)
 391 {
 392         return (struct fd_context *)pctx;
 393 }
 394
 395 static inline struct pipe_scissor_state *
 396 fd_context_get_scissor(struct fd_context *ctx)
 397 {
 398         if (ctx->rasterizer && ctx->rasterizer->scissor)
 399                 return &ctx->scissor;
 400         return &ctx->disabled_scissor;
 401 }
 402
 403 static inline bool
 404 fd_supported_prim(struct fd_context *ctx, unsigned prim)
 405 {
 406         return (1 << prim) & ctx->primtype_mask;
 407 }
 408
 409 static inline void
 410 fd_reset_wfi(struct fd_context *ctx)
 411 {
 412         ctx->needs_wfi = true;
 413 }
 414
 415 /* emit a WAIT_FOR_IDLE only if needed, ie. if there has not already
 416  * been one since last draw:
 417  */
 418 static inline void
 419 fd_wfi(struct fd_context *ctx, struct fd_ringbuffer *ring)
 420 {
 421         if (ctx->needs_wfi) {
 422                 OUT_WFI(ring);
 423                 ctx->needs_wfi = false;
 424         }
 425 }
 426
 427 /* emit a CP_EVENT_WRITE:
 428  */
 429 static inline void
 430 fd_event_write(struct fd_context *ctx, struct fd_ringbuffer *ring,
 431                 enum vgt_event_type evt)
 432 {
 433         OUT_PKT3(ring, CP_EVENT_WRITE, 1);
 434         OUT_RING(ring, evt);
 435         fd_reset_wfi(ctx);
 436 }
 437
 438 struct pipe_context * fd_context_init(struct fd_context *ctx,
 439                 struct pipe_screen *pscreen, const uint8_t *primtypes,
 440                 void *priv);
 441
 442 void fd_context_render(struct pipe_context *pctx);
 443
 444 void fd_context_destroy(struct pipe_context *pctx);
 445
 446 #endif /* FREEDRENO_CONTEXT_H_ */