freedreno: per-generation OUT_IB packet
[mesa.git] / src / gallium / drivers / freedreno / freedreno_gmem.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_gmem.h"
36 #include "freedreno_context.h"
37 #include "freedreno_resource.h"
38 #include "freedreno_query_hw.h"
39 #include "freedreno_util.h"
40
41 /*
42 * GMEM is the small (ie. 256KiB for a200, 512KiB for a220, etc) tile buffer
43 * inside the GPU. All rendering happens to GMEM. Larger render targets
44 * are split into tiles that are small enough for the color (and depth and/or
45 * stencil, if enabled) buffers to fit within GMEM. Before rendering a tile,
46 * if there was not a clear invalidating the previous tile contents, we need
47 * to restore the previous tiles contents (system mem -> GMEM), and after all
48 * the draw calls, before moving to the next tile, we need to save the tile
49 * contents (GMEM -> system mem).
50 *
51 * The code in this file handles dealing with GMEM and tiling.
52 *
53 * The structure of the ringbuffer ends up being:
54 *
55 * +--<---<-- IB ---<---+---<---+---<---<---<--+
56 * | | | |
57 * v ^ ^ ^
58 * ------------------------------------------------------
59 * | clear/draw cmds | Tile0 | Tile1 | .... | TileN |
60 * ------------------------------------------------------
61 * ^
62 * |
63 * address submitted in issueibcmds
64 *
65 * Where the per-tile section handles scissor setup, mem2gmem restore (if
66 * needed), IB to draw cmds earlier in the ringbuffer, and then gmem2mem
67 * resolve.
68 */
69
70 static uint32_t bin_width(struct fd_context *ctx)
71 {
72 if (is_a4xx(ctx->screen))
73 return 1024;
74 if (is_a3xx(ctx->screen))
75 return 992;
76 return 512;
77 }
78
79 static uint32_t
80 total_size(uint8_t cbuf_cpp[], uint8_t zsbuf_cpp[2],
81 uint32_t bin_w, uint32_t bin_h, struct fd_gmem_stateobj *gmem)
82 {
83 uint32_t total = 0, i;
84
85 for (i = 0; i < MAX_RENDER_TARGETS; i++) {
86 if (cbuf_cpp[i]) {
87 gmem->cbuf_base[i] = align(total, 0x4000);
88 total = gmem->cbuf_base[i] + cbuf_cpp[i] * bin_w * bin_h;
89 }
90 }
91
92 if (zsbuf_cpp[0]) {
93 gmem->zsbuf_base[0] = align(total, 0x4000);
94 total = gmem->zsbuf_base[0] + zsbuf_cpp[0] * bin_w * bin_h;
95 }
96
97 if (zsbuf_cpp[1]) {
98 gmem->zsbuf_base[1] = align(total, 0x4000);
99 total = gmem->zsbuf_base[1] + zsbuf_cpp[1] * bin_w * bin_h;
100 }
101
102 return total;
103 }
104
105 static void
106 calculate_tiles(struct fd_context *ctx)
107 {
108 struct fd_gmem_stateobj *gmem = &ctx->gmem;
109 struct pipe_scissor_state *scissor = &ctx->max_scissor;
110 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
111 uint32_t gmem_size = ctx->screen->gmemsize_bytes;
112 uint32_t minx, miny, width, height;
113 uint32_t nbins_x = 1, nbins_y = 1;
114 uint32_t bin_w, bin_h;
115 uint32_t max_width = bin_width(ctx);
116 uint8_t cbuf_cpp[MAX_RENDER_TARGETS] = {0}, zsbuf_cpp[2] = {0};
117 uint32_t i, j, t, xoff, yoff;
118 uint32_t tpp_x, tpp_y;
119 bool has_zs = !!(ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL));
120 int tile_n[ARRAY_SIZE(ctx->pipe)];
121
122 if (has_zs) {
123 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
124 zsbuf_cpp[0] = rsc->cpp;
125 if (rsc->stencil)
126 zsbuf_cpp[1] = rsc->stencil->cpp;
127 }
128 for (i = 0; i < pfb->nr_cbufs; i++) {
129 if (pfb->cbufs[i])
130 cbuf_cpp[i] = util_format_get_blocksize(pfb->cbufs[i]->format);
131 else
132 cbuf_cpp[i] = 4;
133 }
134
135 if (!memcmp(gmem->zsbuf_cpp, zsbuf_cpp, sizeof(zsbuf_cpp)) &&
136 !memcmp(gmem->cbuf_cpp, cbuf_cpp, sizeof(cbuf_cpp)) &&
137 !memcmp(&gmem->scissor, scissor, sizeof(gmem->scissor))) {
138 /* everything is up-to-date */
139 return;
140 }
141
142 if (fd_mesa_debug & FD_DBG_NOSCIS) {
143 minx = 0;
144 miny = 0;
145 width = pfb->width;
146 height = pfb->height;
147 } else {
148 minx = scissor->minx & ~31; /* round down to multiple of 32 */
149 miny = scissor->miny & ~31;
150 width = scissor->maxx - minx;
151 height = scissor->maxy - miny;
152 }
153
154 bin_w = align(width, 32);
155 bin_h = align(height, 32);
156
157 /* first, find a bin width that satisfies the maximum width
158 * restrictions:
159 */
160 while (bin_w > max_width) {
161 nbins_x++;
162 bin_w = align(width / nbins_x, 32);
163 }
164
165 if (fd_mesa_debug & FD_DBG_MSGS) {
166 debug_printf("binning input: cbuf cpp:");
167 for (i = 0; i < pfb->nr_cbufs; i++)
168 debug_printf(" %d", cbuf_cpp[i]);
169 debug_printf(", zsbuf cpp: %d; %dx%d\n",
170 zsbuf_cpp[0], width, height);
171 }
172
173 /* then find a bin width/height that satisfies the memory
174 * constraints:
175 */
176 while (total_size(cbuf_cpp, zsbuf_cpp, bin_w, bin_h, gmem) > gmem_size) {
177 if (bin_w > bin_h) {
178 nbins_x++;
179 bin_w = align(width / nbins_x, 32);
180 } else {
181 nbins_y++;
182 bin_h = align(height / nbins_y, 32);
183 }
184 }
185
186 DBG("using %d bins of size %dx%d", nbins_x*nbins_y, bin_w, bin_h);
187
188 gmem->scissor = *scissor;
189 memcpy(gmem->cbuf_cpp, cbuf_cpp, sizeof(cbuf_cpp));
190 memcpy(gmem->zsbuf_cpp, zsbuf_cpp, sizeof(zsbuf_cpp));
191 gmem->bin_h = bin_h;
192 gmem->bin_w = bin_w;
193 gmem->nbins_x = nbins_x;
194 gmem->nbins_y = nbins_y;
195 gmem->minx = minx;
196 gmem->miny = miny;
197 gmem->width = width;
198 gmem->height = height;
199
200 /*
201 * Assign tiles and pipes:
202 *
203 * At some point it might be worth playing with different
204 * strategies and seeing if that makes much impact on
205 * performance.
206 */
207
208 #define div_round_up(v, a) (((v) + (a) - 1) / (a))
209 /* figure out number of tiles per pipe: */
210 tpp_x = tpp_y = 1;
211 while (div_round_up(nbins_y, tpp_y) > 8)
212 tpp_y += 2;
213 while ((div_round_up(nbins_y, tpp_y) *
214 div_round_up(nbins_x, tpp_x)) > 8)
215 tpp_x += 1;
216
217 /* configure pipes: */
218 xoff = yoff = 0;
219 for (i = 0; i < ARRAY_SIZE(ctx->pipe); i++) {
220 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
221
222 if (xoff >= nbins_x) {
223 xoff = 0;
224 yoff += tpp_y;
225 }
226
227 if (yoff >= nbins_y) {
228 break;
229 }
230
231 pipe->x = xoff;
232 pipe->y = yoff;
233 pipe->w = MIN2(tpp_x, nbins_x - xoff);
234 pipe->h = MIN2(tpp_y, nbins_y - yoff);
235
236 xoff += tpp_x;
237 }
238
239 for (; i < ARRAY_SIZE(ctx->pipe); i++) {
240 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
241 pipe->x = pipe->y = pipe->w = pipe->h = 0;
242 }
243
244 #if 0 /* debug */
245 printf("%dx%d ... tpp=%dx%d\n", nbins_x, nbins_y, tpp_x, tpp_y);
246 for (i = 0; i < 8; i++) {
247 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
248 printf("pipe[%d]: %ux%u @ %u,%u\n", i,
249 pipe->w, pipe->h, pipe->x, pipe->y);
250 }
251 #endif
252
253 /* configure tiles: */
254 t = 0;
255 yoff = miny;
256 memset(tile_n, 0, sizeof(tile_n));
257 for (i = 0; i < nbins_y; i++) {
258 uint32_t bw, bh;
259
260 xoff = minx;
261
262 /* clip bin height: */
263 bh = MIN2(bin_h, miny + height - yoff);
264
265 for (j = 0; j < nbins_x; j++) {
266 struct fd_tile *tile = &ctx->tile[t];
267 uint32_t p;
268
269 assert(t < ARRAY_SIZE(ctx->tile));
270
271 /* pipe number: */
272 p = ((i / tpp_y) * div_round_up(nbins_x, tpp_x)) + (j / tpp_x);
273
274 /* clip bin width: */
275 bw = MIN2(bin_w, minx + width - xoff);
276
277 tile->n = tile_n[p]++;
278 tile->p = p;
279 tile->bin_w = bw;
280 tile->bin_h = bh;
281 tile->xoff = xoff;
282 tile->yoff = yoff;
283
284 t++;
285
286 xoff += bw;
287 }
288
289 yoff += bh;
290 }
291
292 #if 0 /* debug */
293 t = 0;
294 for (i = 0; i < nbins_y; i++) {
295 for (j = 0; j < nbins_x; j++) {
296 struct fd_tile *tile = &ctx->tile[t++];
297 printf("|p:%u n:%u|", tile->p, tile->n);
298 }
299 printf("\n");
300 }
301 #endif
302 }
303
304 static void
305 render_tiles(struct fd_context *ctx)
306 {
307 struct fd_gmem_stateobj *gmem = &ctx->gmem;
308 int i;
309
310 ctx->emit_tile_init(ctx);
311
312 if (ctx->restore)
313 ctx->stats.batch_restore++;
314
315 for (i = 0; i < (gmem->nbins_x * gmem->nbins_y); i++) {
316 struct fd_tile *tile = &ctx->tile[i];
317
318 DBG("bin_h=%d, yoff=%d, bin_w=%d, xoff=%d",
319 tile->bin_h, tile->yoff, tile->bin_w, tile->xoff);
320
321 ctx->emit_tile_prep(ctx, tile);
322
323 if (ctx->restore) {
324 fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_MEM2GMEM);
325 ctx->emit_tile_mem2gmem(ctx, tile);
326 fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_NULL);
327 }
328
329 ctx->emit_tile_renderprep(ctx, tile);
330
331 fd_hw_query_prepare_tile(ctx, i, ctx->ring);
332
333 /* emit IB to drawcmds: */
334 ctx->emit_ib(ctx->ring, ctx->draw_start, ctx->draw_end);
335 fd_reset_wfi(ctx);
336
337 /* emit gmem2mem to transfer tile back to system memory: */
338 fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_GMEM2MEM);
339 ctx->emit_tile_gmem2mem(ctx, tile);
340 fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_NULL);
341 }
342 }
343
344 static void
345 render_sysmem(struct fd_context *ctx)
346 {
347 ctx->emit_sysmem_prep(ctx);
348
349 fd_hw_query_prepare_tile(ctx, 0, ctx->ring);
350
351 /* emit IB to drawcmds: */
352 ctx->emit_ib(ctx->ring, ctx->draw_start, ctx->draw_end);
353 fd_reset_wfi(ctx);
354 }
355
356 void
357 fd_gmem_render_tiles(struct fd_context *ctx)
358 {
359 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
360 bool sysmem = false;
361
362 if (ctx->emit_sysmem_prep) {
363 if (ctx->cleared || ctx->gmem_reason || (ctx->num_draws > 5)) {
364 DBG("GMEM: cleared=%x, gmem_reason=%x, num_draws=%u",
365 ctx->cleared, ctx->gmem_reason, ctx->num_draws);
366 } else if (!(fd_mesa_debug & FD_DBG_NOBYPASS)) {
367 sysmem = true;
368 }
369 }
370
371 /* close out the draw cmds by making sure any active queries are
372 * paused:
373 */
374 fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_NULL);
375
376 /* mark the end of the clear/draw cmds before emitting per-tile cmds: */
377 fd_ringmarker_mark(ctx->draw_end);
378 fd_ringmarker_mark(ctx->binning_end);
379
380 fd_reset_wfi(ctx);
381
382 ctx->stats.batch_total++;
383
384 if (sysmem) {
385 DBG("rendering sysmem (%s/%s)",
386 util_format_short_name(pipe_surface_format(pfb->cbufs[0])),
387 util_format_short_name(pipe_surface_format(pfb->zsbuf)));
388 fd_hw_query_prepare(ctx, 1);
389 render_sysmem(ctx);
390 ctx->stats.batch_sysmem++;
391 } else {
392 struct fd_gmem_stateobj *gmem = &ctx->gmem;
393 calculate_tiles(ctx);
394 DBG("rendering %dx%d tiles (%s/%s)", gmem->nbins_x, gmem->nbins_y,
395 util_format_short_name(pipe_surface_format(pfb->cbufs[0])),
396 util_format_short_name(pipe_surface_format(pfb->zsbuf)));
397 fd_hw_query_prepare(ctx, gmem->nbins_x * gmem->nbins_y);
398 render_tiles(ctx);
399 ctx->stats.batch_gmem++;
400 }
401
402 /* GPU executes starting from tile cmds, which IB back to draw cmds: */
403 fd_ringmarker_flush(ctx->draw_end);
404
405 /* mark start for next draw/binning cmds: */
406 fd_ringmarker_mark(ctx->draw_start);
407 fd_ringmarker_mark(ctx->binning_start);
408
409 fd_reset_wfi(ctx);
410
411 /* reset maximal bounds: */
412 ctx->max_scissor.minx = ctx->max_scissor.miny = ~0;
413 ctx->max_scissor.maxx = ctx->max_scissor.maxy = 0;
414
415 ctx->dirty = ~0;
416 }
417
418 /* tile needs restore if it isn't completely contained within the
419 * cleared scissor:
420 */
421 static bool
422 skip_restore(struct pipe_scissor_state *scissor, struct fd_tile *tile)
423 {
424 unsigned minx = tile->xoff;
425 unsigned maxx = tile->xoff + tile->bin_w;
426 unsigned miny = tile->yoff;
427 unsigned maxy = tile->yoff + tile->bin_h;
428 return (minx >= scissor->minx) && (maxx <= scissor->maxx) &&
429 (miny >= scissor->miny) && (maxy <= scissor->maxy);
430 }
431
432 /* When deciding whether a tile needs mem2gmem, we need to take into
433 * account the scissor rect(s) that were cleared. To simplify we only
434 * consider the last scissor rect for each buffer, since the common
435 * case would be a single clear.
436 */
437 bool
438 fd_gmem_needs_restore(struct fd_context *ctx, struct fd_tile *tile,
439 uint32_t buffers)
440 {
441 if (!(ctx->restore & buffers))
442 return false;
443
444 /* if buffers partially cleared, then slow-path to figure out
445 * if this particular tile needs restoring:
446 */
447 if ((buffers & FD_BUFFER_COLOR) &&
448 (ctx->partial_cleared & FD_BUFFER_COLOR) &&
449 skip_restore(&ctx->cleared_scissor.color, tile))
450 return false;
451 if ((buffers & FD_BUFFER_DEPTH) &&
452 (ctx->partial_cleared & FD_BUFFER_DEPTH) &&
453 skip_restore(&ctx->cleared_scissor.depth, tile))
454 return false;
455 if ((buffers & FD_BUFFER_STENCIL) &&
456 (ctx->partial_cleared & FD_BUFFER_STENCIL) &&
457 skip_restore(&ctx->cleared_scissor.stencil, tile))
458 return false;
459
460 return true;
461 }