src/gallium/drivers/freedreno/freedreno_gmem.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_inlines.h"
  33 #include "util/u_format.h"
  34
  35 #include "freedreno_gmem.h"
  36 #include "freedreno_context.h"
  37 #include "freedreno_resource.h"
  38 #include "freedreno_query_hw.h"
  39 #include "freedreno_util.h"
  40
  41 /*
  42  * GMEM is the small (ie. 256KiB for a200, 512KiB for a220, etc) tile buffer
  43  * inside the GPU.  All rendering happens to GMEM.  Larger render targets
  44  * are split into tiles that are small enough for the color (and depth and/or
  45  * stencil, if enabled) buffers to fit within GMEM.  Before rendering a tile,
  46  * if there was not a clear invalidating the previous tile contents, we need
  47  * to restore the previous tiles contents (system mem -> GMEM), and after all
  48  * the draw calls, before moving to the next tile, we need to save the tile
  49  * contents (GMEM -> system mem).
  50  *
  51  * The code in this file handles dealing with GMEM and tiling.
  52  *
  53  * The structure of the ringbuffer ends up being:
  54  *
  55  *     +--<---<-- IB ---<---+---<---+---<---<---<--+
  56  *     |                    |       |              |
  57  *     v                    ^       ^              ^
  58  *   ------------------------------------------------------
  59  *     | clear/draw cmds | Tile0 | Tile1 | .... | TileN |
  60  *   ------------------------------------------------------
  61  *                       ^
  62  *                       |
  63  *                       address submitted in issueibcmds
  64  *
  65  * Where the per-tile section handles scissor setup, mem2gmem restore (if
  66  * needed), IB to draw cmds earlier in the ringbuffer, and then gmem2mem
  67  * resolve.
  68  */
  69
  70 static uint32_t bin_width(struct fd_context *ctx)
  71 {
  72         if (ctx->screen->gpu_id >= 300)
  73                 return 992;
  74         return 512;
  75 }
  76
  77 static void
  78 calculate_tiles(struct fd_context *ctx)
  79 {
  80         struct fd_gmem_stateobj *gmem = &ctx->gmem;
  81         struct pipe_scissor_state *scissor = &ctx->max_scissor;
  82         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
  83         uint32_t gmem_size = ctx->screen->gmemsize_bytes;
  84         uint32_t minx, miny, width, height;
  85         uint32_t nbins_x = 1, nbins_y = 1;
  86         uint32_t bin_w, bin_h;
  87         uint32_t max_width = bin_width(ctx);
  88         uint32_t cpp = 4;
  89         uint32_t i, j, t, xoff, yoff;
  90         uint32_t tpp_x, tpp_y;
  91         bool has_zs = !!(ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL));
  92
  93         if (pfb->cbufs[0])
  94                 cpp = util_format_get_blocksize(pfb->cbufs[0]->format);
  95
  96         if ((gmem->cpp == cpp) && (gmem->has_zs == has_zs) &&
  97                         !memcmp(&gmem->scissor, scissor, sizeof(gmem->scissor))) {
  98                 /* everything is up-to-date */
  99                 return;
 100         }
 101
 102         /* if have depth/stencil, we need to leave room: */
 103         if (has_zs) {
 104                 gmem_size /= 2;
 105                 max_width /= 2;
 106         }
 107
 108         if (fd_mesa_debug & FD_DBG_DSCIS) {
 109                 minx = 0;
 110                 miny = 0;
 111                 width = pfb->width;
 112                 height = pfb->height;
 113         } else {
 114                 minx = scissor->minx & ~31; /* round down to multiple of 32 */
 115                 miny = scissor->miny & ~31;
 116                 width = scissor->maxx - minx;
 117                 height = scissor->maxy - miny;
 118         }
 119
 120         bin_w = align(width, 32);
 121         bin_h = align(height, 32);
 122
 123         /* first, find a bin width that satisfies the maximum width
 124          * restrictions:
 125          */
 126         while (bin_w > max_width) {
 127                 nbins_x++;
 128                 bin_w = align(width / nbins_x, 32);
 129         }
 130
 131         /* then find a bin height that satisfies the memory constraints:
 132          */
 133         while ((bin_w * bin_h * cpp) > gmem_size) {
 134                 nbins_y++;
 135                 bin_h = align(height / nbins_y, 32);
 136         }
 137
 138         DBG("using %d bins of size %dx%d", nbins_x*nbins_y, bin_w, bin_h);
 139
 140         gmem->scissor = *scissor;
 141         gmem->cpp = cpp;
 142         gmem->has_zs = has_zs;
 143         gmem->bin_h = bin_h;
 144         gmem->bin_w = bin_w;
 145         gmem->nbins_x = nbins_x;
 146         gmem->nbins_y = nbins_y;
 147         gmem->minx = minx;
 148         gmem->miny = miny;
 149         gmem->width = width;
 150         gmem->height = height;
 151
 152         /*
 153          * Assign tiles and pipes:
 154          *
 155          * At some point it might be worth playing with different
 156          * strategies and seeing if that makes much impact on
 157          * performance.
 158          */
 159
 160 #define div_round_up(v, a)  (((v) + (a) - 1) / (a))
 161         /* figure out number of tiles per pipe: */
 162         tpp_x = tpp_y = 1;
 163         while (div_round_up(nbins_y, tpp_y) > 8)
 164                 tpp_y += 2;
 165         while ((div_round_up(nbins_y, tpp_y) *
 166                         div_round_up(nbins_x, tpp_x)) > 8)
 167                 tpp_x += 1;
 168
 169         /* configure pipes: */
 170         xoff = yoff = 0;
 171         for (i = 0; i < ARRAY_SIZE(ctx->pipe); i++) {
 172                 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
 173
 174                 if (xoff >= nbins_x) {
 175                         xoff = 0;
 176                         yoff += tpp_y;
 177                 }
 178
 179                 if (yoff >= nbins_y) {
 180                         break;
 181                 }
 182
 183                 pipe->x = xoff;
 184                 pipe->y = yoff;
 185                 pipe->w = MIN2(tpp_x, nbins_x - xoff);
 186                 pipe->h = MIN2(tpp_y, nbins_y - yoff);
 187
 188                 xoff += tpp_x;
 189         }
 190
 191         for (; i < ARRAY_SIZE(ctx->pipe); i++) {
 192                 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
 193                 pipe->x = pipe->y = pipe->w = pipe->h = 0;
 194         }
 195
 196 #if 0 /* debug */
 197         printf("%dx%d ... tpp=%dx%d\n", nbins_x, nbins_y, tpp_x, tpp_y);
 198         for (i = 0; i < 8; i++) {
 199                 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
 200                 printf("pipe[%d]: %ux%u @ %u,%u\n", i,
 201                                 pipe->w, pipe->h, pipe->x, pipe->y);
 202         }
 203 #endif
 204
 205         /* configure tiles: */
 206         t = 0;
 207         yoff = miny;
 208         for (i = 0; i < nbins_y; i++) {
 209                 uint32_t bw, bh;
 210
 211                 xoff = minx;
 212
 213                 /* clip bin height: */
 214                 bh = MIN2(bin_h, miny + height - yoff);
 215
 216                 for (j = 0; j < nbins_x; j++) {
 217                         struct fd_tile *tile = &ctx->tile[t];
 218                         uint32_t n, p;
 219
 220                         assert(t < ARRAY_SIZE(ctx->tile));
 221
 222                         /* pipe number: */
 223                         p = ((i / tpp_y) * div_round_up(nbins_x, tpp_x)) + (j / tpp_x);
 224
 225                         /* slot number: */
 226                         n = ((i % tpp_y) * tpp_x) + (j % tpp_x);
 227
 228                         /* clip bin width: */
 229                         bw = MIN2(bin_w, minx + width - xoff);
 230
 231                         tile->n = n;
 232                         tile->p = p;
 233                         tile->bin_w = bw;
 234                         tile->bin_h = bh;
 235                         tile->xoff = xoff;
 236                         tile->yoff = yoff;
 237
 238                         t++;
 239
 240                         xoff += bw;
 241                 }
 242
 243                 yoff += bh;
 244         }
 245
 246 #if 0 /* debug */
 247         t = 0;
 248         for (i = 0; i < nbins_y; i++) {
 249                 for (j = 0; j < nbins_x; j++) {
 250                         struct fd_tile *tile = &ctx->tile[t++];
 251                         printf("|p:%u n:%u|", tile->p, tile->n);
 252                 }
 253                 printf("\n");
 254         }
 255 #endif
 256 }
 257
 258 static void
 259 render_tiles(struct fd_context *ctx)
 260 {
 261         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 262         int i;
 263
 264         ctx->emit_tile_init(ctx);
 265
 266         if (ctx->restore)
 267                 ctx->stats.batch_restore++;
 268
 269         for (i = 0; i < (gmem->nbins_x * gmem->nbins_y); i++) {
 270                 struct fd_tile *tile = &ctx->tile[i];
 271
 272                 DBG("bin_h=%d, yoff=%d, bin_w=%d, xoff=%d",
 273                         tile->bin_h, tile->yoff, tile->bin_w, tile->xoff);
 274
 275                 ctx->emit_tile_prep(ctx, tile);
 276
 277                 if (ctx->restore) {
 278                         fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_MEM2GMEM);
 279                         ctx->emit_tile_mem2gmem(ctx, tile);
 280                         fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_NULL);
 281                 }
 282
 283                 ctx->emit_tile_renderprep(ctx, tile);
 284
 285                 fd_hw_query_prepare_tile(ctx, i, ctx->ring);
 286
 287                 /* emit IB to drawcmds: */
 288                 OUT_IB(ctx->ring, ctx->draw_start, ctx->draw_end);
 289                 fd_reset_wfi(ctx);
 290
 291                 /* emit gmem2mem to transfer tile back to system memory: */
 292                 fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_GMEM2MEM);
 293                 ctx->emit_tile_gmem2mem(ctx, tile);
 294                 fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_NULL);
 295         }
 296 }
 297
 298 static void
 299 render_sysmem(struct fd_context *ctx)
 300 {
 301         ctx->emit_sysmem_prep(ctx);
 302
 303         fd_hw_query_prepare_tile(ctx, 0, ctx->ring);
 304
 305         /* emit IB to drawcmds: */
 306         OUT_IB(ctx->ring, ctx->draw_start, ctx->draw_end);
 307         fd_reset_wfi(ctx);
 308 }
 309
 310 void
 311 fd_gmem_render_tiles(struct pipe_context *pctx)
 312 {
 313         struct fd_context *ctx = fd_context(pctx);
 314         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 315         uint32_t timestamp = 0;
 316         bool sysmem = false;
 317
 318         if (ctx->emit_sysmem_prep) {
 319                 if (ctx->cleared || ctx->gmem_reason || (ctx->num_draws > 5)) {
 320                         DBG("GMEM: cleared=%x, gmem_reason=%x, num_draws=%u",
 321                                 ctx->cleared, ctx->gmem_reason, ctx->num_draws);
 322                 } else if (!(fd_mesa_debug & FD_DBG_DBYPASS)) {
 323                         sysmem = true;
 324                 }
 325         }
 326
 327         /* close out the draw cmds by making sure any active queries are
 328          * paused:
 329          */
 330         fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_NULL);
 331
 332         /* mark the end of the clear/draw cmds before emitting per-tile cmds: */
 333         fd_ringmarker_mark(ctx->draw_end);
 334         fd_ringmarker_mark(ctx->binning_end);
 335
 336         fd_reset_wfi(ctx);
 337
 338         ctx->stats.batch_total++;
 339
 340         if (sysmem) {
 341                 DBG("rendering sysmem (%s/%s)",
 342                         util_format_short_name(pipe_surface_format(pfb->cbufs[0])),
 343                         util_format_short_name(pipe_surface_format(pfb->zsbuf)));
 344                 fd_hw_query_prepare(ctx, 1);
 345                 render_sysmem(ctx);
 346                 ctx->stats.batch_sysmem++;
 347         } else {
 348                 struct fd_gmem_stateobj *gmem = &ctx->gmem;
 349                 calculate_tiles(ctx);
 350                 DBG("rendering %dx%d tiles (%s/%s)", gmem->nbins_x, gmem->nbins_y,
 351                         util_format_short_name(pipe_surface_format(pfb->cbufs[0])),
 352                         util_format_short_name(pipe_surface_format(pfb->zsbuf)));
 353                 fd_hw_query_prepare(ctx, gmem->nbins_x * gmem->nbins_y);
 354                 render_tiles(ctx);
 355                 ctx->stats.batch_gmem++;
 356         }
 357
 358         /* GPU executes starting from tile cmds, which IB back to draw cmds: */
 359         fd_ringmarker_flush(ctx->draw_end);
 360
 361         /* mark start for next draw/binning cmds: */
 362         fd_ringmarker_mark(ctx->draw_start);
 363         fd_ringmarker_mark(ctx->binning_start);
 364
 365         fd_reset_wfi(ctx);
 366
 367         /* update timestamps on render targets: */
 368         timestamp = fd_ringbuffer_timestamp(ctx->ring);
 369         if (pfb->cbufs[0])
 370                 fd_resource(pfb->cbufs[0]->texture)->timestamp = timestamp;
 371         if (pfb->zsbuf)
 372                 fd_resource(pfb->zsbuf->texture)->timestamp = timestamp;
 373
 374         /* reset maximal bounds: */
 375         ctx->max_scissor.minx = ctx->max_scissor.miny = ~0;
 376         ctx->max_scissor.maxx = ctx->max_scissor.maxy = 0;
 377
 378         /* Note that because the per-tile setup and mem2gmem/gmem2mem are emitted
 379          * after the draw/clear calls, but executed before, we need to preemptively
 380          * flag some state as dirty before the first draw/clear call.
 381          *
 382          * TODO maybe we need to mark all state as dirty to not worry about state
 383          * being clobbered by other contexts?
 384          */
 385         ctx->dirty |= FD_DIRTY_ZSA |
 386                         FD_DIRTY_RASTERIZER |
 387                         FD_DIRTY_FRAMEBUFFER |
 388                         FD_DIRTY_SAMPLE_MASK |
 389                         FD_DIRTY_VIEWPORT |
 390                         FD_DIRTY_CONSTBUF |
 391                         FD_DIRTY_PROG |
 392                         FD_DIRTY_SCISSOR |
 393                         /* probably only needed if we need to mem2gmem on the next
 394                          * draw..  but not sure if there is a good way to know?
 395                          */
 396                         FD_DIRTY_VERTTEX |
 397                         FD_DIRTY_FRAGTEX |
 398                         FD_DIRTY_BLEND;
 399
 400         if (fd_mesa_debug & FD_DBG_DGMEM)
 401                 ctx->dirty = 0xffffffff;
 402 }