src/gallium/drivers/freedreno/freedreno_gmem.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_inlines.h"
  33 #include "util/u_format.h"
  34
  35 #include "freedreno_gmem.h"
  36 #include "freedreno_context.h"
  37 #include "freedreno_resource.h"
  38 #include "freedreno_util.h"
  39
  40 /*
  41  * GMEM is the small (ie. 256KiB for a200, 512KiB for a220, etc) tile buffer
  42  * inside the GPU.  All rendering happens to GMEM.  Larger render targets
  43  * are split into tiles that are small enough for the color (and depth and/or
  44  * stencil, if enabled) buffers to fit within GMEM.  Before rendering a tile,
  45  * if there was not a clear invalidating the previous tile contents, we need
  46  * to restore the previous tiles contents (system mem -> GMEM), and after all
  47  * the draw calls, before moving to the next tile, we need to save the tile
  48  * contents (GMEM -> system mem).
  49  *
  50  * The code in this file handles dealing with GMEM and tiling.
  51  *
  52  * The structure of the ringbuffer ends up being:
  53  *
  54  *     +--<---<-- IB ---<---+---<---+---<---<---<--+
  55  *     |                    |       |              |
  56  *     v                    ^       ^              ^
  57  *   ------------------------------------------------------
  58  *     | clear/draw cmds | Tile0 | Tile1 | .... | TileN |
  59  *   ------------------------------------------------------
  60  *                       ^
  61  *                       |
  62  *                       address submitted in issueibcmds
  63  *
  64  * Where the per-tile section handles scissor setup, mem2gmem restore (if
  65  * needed), IB to draw cmds earlier in the ringbuffer, and then gmem2mem
  66  * resolve.
  67  */
  68
  69 static uint32_t bin_width(struct fd_context *ctx)
  70 {
  71         if (ctx->screen->gpu_id >= 300)
  72                 return 992;
  73         return 512;
  74 }
  75
  76 static void
  77 calculate_tiles(struct fd_context *ctx)
  78 {
  79         struct fd_gmem_stateobj *gmem = &ctx->gmem;
  80         struct pipe_scissor_state *scissor = &ctx->max_scissor;
  81         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
  82         uint32_t gmem_size = ctx->screen->gmemsize_bytes;
  83         uint32_t minx, miny, width, height;
  84         uint32_t nbins_x = 1, nbins_y = 1;
  85         uint32_t bin_w, bin_h;
  86         uint32_t max_width = bin_width(ctx);
  87         uint32_t cpp = 4;
  88         uint32_t i, j, t, p, n, xoff, yoff;
  89         bool has_zs = !!(ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL));
  90
  91         if (pfb->cbufs[0])
  92                 cpp = util_format_get_blocksize(pfb->cbufs[0]->format);
  93
  94         if ((gmem->cpp == cpp) && (gmem->has_zs == has_zs) &&
  95                         !memcmp(&gmem->scissor, scissor, sizeof(gmem->scissor))) {
  96                 /* everything is up-to-date */
  97                 return;
  98         }
  99
 100         /* if have depth/stencil, we need to leave room: */
 101         if (has_zs) {
 102                 gmem_size /= 2;
 103                 max_width /= 2;
 104         }
 105
 106         if (fd_mesa_debug & FD_DBG_DSCIS) {
 107                 minx = 0;
 108                 miny = 0;
 109                 width = pfb->width;
 110                 height = pfb->height;
 111         } else {
 112                 minx = scissor->minx & ~31; /* round down to multiple of 32 */
 113                 miny = scissor->miny & ~31;
 114                 width = scissor->maxx - minx;
 115                 height = scissor->maxy - miny;
 116         }
 117
 118         bin_w = align(width, 32);
 119         bin_h = align(height, 32);
 120
 121         /* first, find a bin width that satisfies the maximum width
 122          * restrictions:
 123          */
 124         while (bin_w > max_width) {
 125                 nbins_x++;
 126                 bin_w = align(width / nbins_x, 32);
 127         }
 128
 129         /* then find a bin height that satisfies the memory constraints:
 130          */
 131         while ((bin_w * bin_h * cpp) > gmem_size) {
 132                 nbins_y++;
 133                 bin_h = align(height / nbins_y, 32);
 134         }
 135
 136         DBG("using %d bins of size %dx%d", nbins_x*nbins_y, bin_w, bin_h);
 137
 138         gmem->scissor = *scissor;
 139         gmem->cpp = cpp;
 140         gmem->has_zs = has_zs;
 141         gmem->bin_h = bin_h;
 142         gmem->bin_w = bin_w;
 143         gmem->nbins_x = nbins_x;
 144         gmem->nbins_y = nbins_y;
 145         gmem->width = width;
 146         gmem->height = height;
 147
 148         /* Assign tiles and pipes:
 149          * NOTE we currently take a rather simplistic approach of
 150          * mapping rows of tiles to a pipe.  At some point it might
 151          * be worth playing with different strategies and seeing if
 152          * that makes much impact on performance.
 153          */
 154         t = p = n = 0;
 155         yoff = miny;
 156         for (i = 0; i < nbins_y; i++) {
 157                 struct fd_vsc_pipe *pipe = &ctx->pipe[p];
 158                 uint32_t bw, bh;
 159
 160                 assert(p < ARRAY_SIZE(ctx->pipe));
 161
 162                 xoff = minx;
 163
 164                 /* clip bin height: */
 165                 bh = MIN2(bin_h, miny + height - yoff);
 166
 167                 for (j = 0; j < nbins_x; j++) {
 168                         struct fd_tile *tile = &ctx->tile[t];
 169
 170                         assert(t < ARRAY_SIZE(ctx->tile));
 171
 172                         /* clip bin width: */
 173                         bw = MIN2(bin_w, minx + width - xoff);
 174
 175                         tile->n = n++;
 176                         tile->p = p;
 177                         tile->bin_w = bw;
 178                         tile->bin_h = bh;
 179                         tile->xoff = xoff;
 180                         tile->yoff = yoff;
 181
 182                         t++;
 183
 184                         xoff += bw;
 185                 }
 186
 187                 /* one pipe per row: */
 188                 pipe->x = 0;
 189                 pipe->y = i;
 190                 pipe->w = nbins_x;
 191                 pipe->h = 1;
 192
 193                 p++;
 194                 n = 0;
 195
 196                 yoff += bh;
 197         }
 198
 199         for (; p < ARRAY_SIZE(ctx->pipe); p++) {
 200                 struct fd_vsc_pipe *pipe = &ctx->pipe[p];
 201                 pipe->x = pipe->y = pipe->w = pipe->h = 0;
 202         }
 203 }
 204
 205 static void
 206 render_tiles(struct fd_context *ctx)
 207 {
 208         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 209         int i;
 210
 211         ctx->emit_tile_init(ctx);
 212
 213         for (i = 0; i < (gmem->nbins_x * gmem->nbins_y); i++) {
 214                 struct fd_tile *tile = &ctx->tile[i];
 215
 216                 DBG("bin_h=%d, yoff=%d, bin_w=%d, xoff=%d",
 217                         tile->bin_h, tile->yoff, tile->bin_w, tile->xoff);
 218
 219                 ctx->emit_tile_prep(ctx, tile);
 220
 221                 if (ctx->restore)
 222                         ctx->emit_tile_mem2gmem(ctx, tile);
 223
 224                 ctx->emit_tile_renderprep(ctx, tile);
 225
 226                 /* emit IB to drawcmds: */
 227                 OUT_IB(ctx->ring, ctx->draw_start, ctx->draw_end);
 228
 229                 /* emit gmem2mem to transfer tile back to system memory: */
 230                 ctx->emit_tile_gmem2mem(ctx, tile);
 231         }
 232 }
 233
 234 static void
 235 render_sysmem(struct fd_context *ctx)
 236 {
 237         ctx->emit_sysmem_prep(ctx);
 238
 239         /* emit IB to drawcmds: */
 240         OUT_IB(ctx->ring, ctx->draw_start, ctx->draw_end);
 241 }
 242
 243 void
 244 fd_gmem_render_tiles(struct pipe_context *pctx)
 245 {
 246         struct fd_context *ctx = fd_context(pctx);
 247         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 248         uint32_t timestamp = 0;
 249         bool sysmem = false;
 250
 251         if (ctx->emit_sysmem_prep) {
 252                 if (ctx->cleared || ctx->gmem_reason || (ctx->num_draws > 5)) {
 253                         DBG("GMEM: cleared=%x, gmem_reason=%x, num_draws=%u",
 254                                 ctx->cleared, ctx->gmem_reason, ctx->num_draws);
 255                 } else if (!(fd_mesa_debug & FD_DBG_DBYPASS)) {
 256                         sysmem = true;
 257                 }
 258         }
 259
 260         /* mark the end of the clear/draw cmds before emitting per-tile cmds: */
 261         fd_ringmarker_mark(ctx->draw_end);
 262
 263         if (sysmem) {
 264                 DBG("rendering sysmem (%s/%s)",
 265                         util_format_short_name(pipe_surface_format(pfb->cbufs[0])),
 266                         util_format_short_name(pipe_surface_format(pfb->zsbuf)));
 267                 render_sysmem(ctx);
 268         } else {
 269                 struct fd_gmem_stateobj *gmem = &ctx->gmem;
 270                 calculate_tiles(ctx);
 271                 DBG("rendering %dx%d tiles (%s/%s)", gmem->nbins_x, gmem->nbins_y,
 272                         util_format_short_name(pipe_surface_format(pfb->cbufs[0])),
 273                         util_format_short_name(pipe_surface_format(pfb->zsbuf)));
 274                 render_tiles(ctx);
 275         }
 276
 277         /* GPU executes starting from tile cmds, which IB back to draw cmds: */
 278         fd_ringmarker_flush(ctx->draw_end);
 279
 280         /* mark start for next draw cmds: */
 281         fd_ringmarker_mark(ctx->draw_start);
 282
 283         fd_reset_rmw_state(ctx);
 284
 285         /* update timestamps on render targets: */
 286         timestamp = fd_ringbuffer_timestamp(ctx->ring);
 287         if (pfb->cbufs[0])
 288                 fd_resource(pfb->cbufs[0]->texture)->timestamp = timestamp;
 289         if (pfb->zsbuf)
 290                 fd_resource(pfb->zsbuf->texture)->timestamp = timestamp;
 291
 292         /* reset maximal bounds: */
 293         ctx->max_scissor.minx = ctx->max_scissor.miny = ~0;
 294         ctx->max_scissor.maxx = ctx->max_scissor.maxy = 0;
 295
 296         /* Note that because the per-tile setup and mem2gmem/gmem2mem are emitted
 297          * after the draw/clear calls, but executed before, we need to preemptively
 298          * flag some state as dirty before the first draw/clear call.
 299          *
 300          * TODO maybe we need to mark all state as dirty to not worry about state
 301          * being clobbered by other contexts?
 302          */
 303         ctx->dirty |= FD_DIRTY_ZSA |
 304                         FD_DIRTY_RASTERIZER |
 305                         FD_DIRTY_FRAMEBUFFER |
 306                         FD_DIRTY_SAMPLE_MASK |
 307                         FD_DIRTY_VIEWPORT |
 308                         FD_DIRTY_CONSTBUF |
 309                         FD_DIRTY_PROG |
 310                         FD_DIRTY_SCISSOR |
 311                         /* probably only needed if we need to mem2gmem on the next
 312                          * draw..  but not sure if there is a good way to know?
 313                          */
 314                         FD_DIRTY_VERTTEX |
 315                         FD_DIRTY_FRAGTEX |
 316                         FD_DIRTY_BLEND;
 317
 318         if (fd_mesa_debug & FD_DBG_DGMEM)
 319                 ctx->dirty = 0xffffffff;
 320 }