freedreno: move more batch related tracking to fd_batch
[mesa.git] / src / gallium / drivers / freedreno / freedreno_gmem.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_gmem.h"
36 #include "freedreno_context.h"
37 #include "freedreno_resource.h"
38 #include "freedreno_query_hw.h"
39 #include "freedreno_util.h"
40
41 /*
42 * GMEM is the small (ie. 256KiB for a200, 512KiB for a220, etc) tile buffer
43 * inside the GPU. All rendering happens to GMEM. Larger render targets
44 * are split into tiles that are small enough for the color (and depth and/or
45 * stencil, if enabled) buffers to fit within GMEM. Before rendering a tile,
46 * if there was not a clear invalidating the previous tile contents, we need
47 * to restore the previous tiles contents (system mem -> GMEM), and after all
48 * the draw calls, before moving to the next tile, we need to save the tile
49 * contents (GMEM -> system mem).
50 *
51 * The code in this file handles dealing with GMEM and tiling.
52 *
53 * The structure of the ringbuffer ends up being:
54 *
55 * +--<---<-- IB ---<---+---<---+---<---<---<--+
56 * | | | |
57 * v ^ ^ ^
58 * ------------------------------------------------------
59 * | clear/draw cmds | Tile0 | Tile1 | .... | TileN |
60 * ------------------------------------------------------
61 * ^
62 * |
63 * address submitted in issueibcmds
64 *
65 * Where the per-tile section handles scissor setup, mem2gmem restore (if
66 * needed), IB to draw cmds earlier in the ringbuffer, and then gmem2mem
67 * resolve.
68 */
69
70 static uint32_t bin_width(struct fd_screen *screen)
71 {
72 if (is_a4xx(screen))
73 return 1024;
74 if (is_a3xx(screen))
75 return 992;
76 return 512;
77 }
78
79 static uint32_t
80 total_size(uint8_t cbuf_cpp[], uint8_t zsbuf_cpp[2],
81 uint32_t bin_w, uint32_t bin_h, struct fd_gmem_stateobj *gmem)
82 {
83 uint32_t total = 0, i;
84
85 for (i = 0; i < MAX_RENDER_TARGETS; i++) {
86 if (cbuf_cpp[i]) {
87 gmem->cbuf_base[i] = align(total, 0x4000);
88 total = gmem->cbuf_base[i] + cbuf_cpp[i] * bin_w * bin_h;
89 }
90 }
91
92 if (zsbuf_cpp[0]) {
93 gmem->zsbuf_base[0] = align(total, 0x4000);
94 total = gmem->zsbuf_base[0] + zsbuf_cpp[0] * bin_w * bin_h;
95 }
96
97 if (zsbuf_cpp[1]) {
98 gmem->zsbuf_base[1] = align(total, 0x4000);
99 total = gmem->zsbuf_base[1] + zsbuf_cpp[1] * bin_w * bin_h;
100 }
101
102 return total;
103 }
104
105 static void
106 calculate_tiles(struct fd_batch *batch)
107 {
108 struct fd_context *ctx = batch->ctx;
109 struct fd_gmem_stateobj *gmem = &ctx->gmem;
110 struct pipe_scissor_state *scissor = &batch->max_scissor;
111 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
112 uint32_t gmem_size = ctx->screen->gmemsize_bytes;
113 uint32_t minx, miny, width, height;
114 uint32_t nbins_x = 1, nbins_y = 1;
115 uint32_t bin_w, bin_h;
116 uint32_t max_width = bin_width(ctx->screen);
117 uint8_t cbuf_cpp[MAX_RENDER_TARGETS] = {0}, zsbuf_cpp[2] = {0};
118 uint32_t i, j, t, xoff, yoff;
119 uint32_t tpp_x, tpp_y;
120 bool has_zs = !!(batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL));
121 int tile_n[ARRAY_SIZE(ctx->pipe)];
122
123 if (has_zs) {
124 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
125 zsbuf_cpp[0] = rsc->cpp;
126 if (rsc->stencil)
127 zsbuf_cpp[1] = rsc->stencil->cpp;
128 }
129 for (i = 0; i < pfb->nr_cbufs; i++) {
130 if (pfb->cbufs[i])
131 cbuf_cpp[i] = util_format_get_blocksize(pfb->cbufs[i]->format);
132 else
133 cbuf_cpp[i] = 4;
134 }
135
136 if (!memcmp(gmem->zsbuf_cpp, zsbuf_cpp, sizeof(zsbuf_cpp)) &&
137 !memcmp(gmem->cbuf_cpp, cbuf_cpp, sizeof(cbuf_cpp)) &&
138 !memcmp(&gmem->scissor, scissor, sizeof(gmem->scissor))) {
139 /* everything is up-to-date */
140 return;
141 }
142
143 if (fd_mesa_debug & FD_DBG_NOSCIS) {
144 minx = 0;
145 miny = 0;
146 width = pfb->width;
147 height = pfb->height;
148 } else {
149 minx = scissor->minx & ~31; /* round down to multiple of 32 */
150 miny = scissor->miny & ~31;
151 width = scissor->maxx - minx;
152 height = scissor->maxy - miny;
153 }
154
155 bin_w = align(width, 32);
156 bin_h = align(height, 32);
157
158 /* first, find a bin width that satisfies the maximum width
159 * restrictions:
160 */
161 while (bin_w > max_width) {
162 nbins_x++;
163 bin_w = align(width / nbins_x, 32);
164 }
165
166 if (fd_mesa_debug & FD_DBG_MSGS) {
167 debug_printf("binning input: cbuf cpp:");
168 for (i = 0; i < pfb->nr_cbufs; i++)
169 debug_printf(" %d", cbuf_cpp[i]);
170 debug_printf(", zsbuf cpp: %d; %dx%d\n",
171 zsbuf_cpp[0], width, height);
172 }
173
174 /* then find a bin width/height that satisfies the memory
175 * constraints:
176 */
177 while (total_size(cbuf_cpp, zsbuf_cpp, bin_w, bin_h, gmem) > gmem_size) {
178 if (bin_w > bin_h) {
179 nbins_x++;
180 bin_w = align(width / nbins_x, 32);
181 } else {
182 nbins_y++;
183 bin_h = align(height / nbins_y, 32);
184 }
185 }
186
187 DBG("using %d bins of size %dx%d", nbins_x*nbins_y, bin_w, bin_h);
188
189 gmem->scissor = *scissor;
190 memcpy(gmem->cbuf_cpp, cbuf_cpp, sizeof(cbuf_cpp));
191 memcpy(gmem->zsbuf_cpp, zsbuf_cpp, sizeof(zsbuf_cpp));
192 gmem->bin_h = bin_h;
193 gmem->bin_w = bin_w;
194 gmem->nbins_x = nbins_x;
195 gmem->nbins_y = nbins_y;
196 gmem->minx = minx;
197 gmem->miny = miny;
198 gmem->width = width;
199 gmem->height = height;
200
201 /*
202 * Assign tiles and pipes:
203 *
204 * At some point it might be worth playing with different
205 * strategies and seeing if that makes much impact on
206 * performance.
207 */
208
209 #define div_round_up(v, a) (((v) + (a) - 1) / (a))
210 /* figure out number of tiles per pipe: */
211 tpp_x = tpp_y = 1;
212 while (div_round_up(nbins_y, tpp_y) > 8)
213 tpp_y += 2;
214 while ((div_round_up(nbins_y, tpp_y) *
215 div_round_up(nbins_x, tpp_x)) > 8)
216 tpp_x += 1;
217
218 /* configure pipes: */
219 xoff = yoff = 0;
220 for (i = 0; i < ARRAY_SIZE(ctx->pipe); i++) {
221 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
222
223 if (xoff >= nbins_x) {
224 xoff = 0;
225 yoff += tpp_y;
226 }
227
228 if (yoff >= nbins_y) {
229 break;
230 }
231
232 pipe->x = xoff;
233 pipe->y = yoff;
234 pipe->w = MIN2(tpp_x, nbins_x - xoff);
235 pipe->h = MIN2(tpp_y, nbins_y - yoff);
236
237 xoff += tpp_x;
238 }
239
240 for (; i < ARRAY_SIZE(ctx->pipe); i++) {
241 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
242 pipe->x = pipe->y = pipe->w = pipe->h = 0;
243 }
244
245 #if 0 /* debug */
246 printf("%dx%d ... tpp=%dx%d\n", nbins_x, nbins_y, tpp_x, tpp_y);
247 for (i = 0; i < 8; i++) {
248 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
249 printf("pipe[%d]: %ux%u @ %u,%u\n", i,
250 pipe->w, pipe->h, pipe->x, pipe->y);
251 }
252 #endif
253
254 /* configure tiles: */
255 t = 0;
256 yoff = miny;
257 memset(tile_n, 0, sizeof(tile_n));
258 for (i = 0; i < nbins_y; i++) {
259 uint32_t bw, bh;
260
261 xoff = minx;
262
263 /* clip bin height: */
264 bh = MIN2(bin_h, miny + height - yoff);
265
266 for (j = 0; j < nbins_x; j++) {
267 struct fd_tile *tile = &ctx->tile[t];
268 uint32_t p;
269
270 assert(t < ARRAY_SIZE(ctx->tile));
271
272 /* pipe number: */
273 p = ((i / tpp_y) * div_round_up(nbins_x, tpp_x)) + (j / tpp_x);
274
275 /* clip bin width: */
276 bw = MIN2(bin_w, minx + width - xoff);
277
278 tile->n = tile_n[p]++;
279 tile->p = p;
280 tile->bin_w = bw;
281 tile->bin_h = bh;
282 tile->xoff = xoff;
283 tile->yoff = yoff;
284
285 t++;
286
287 xoff += bw;
288 }
289
290 yoff += bh;
291 }
292
293 #if 0 /* debug */
294 t = 0;
295 for (i = 0; i < nbins_y; i++) {
296 for (j = 0; j < nbins_x; j++) {
297 struct fd_tile *tile = &ctx->tile[t++];
298 printf("|p:%u n:%u|", tile->p, tile->n);
299 }
300 printf("\n");
301 }
302 #endif
303 }
304
305 static void
306 render_tiles(struct fd_batch *batch)
307 {
308 struct fd_context *ctx = batch->ctx;
309 struct fd_gmem_stateobj *gmem = &ctx->gmem;
310 int i;
311
312 ctx->emit_tile_init(batch);
313
314 if (batch->restore)
315 ctx->stats.batch_restore++;
316
317 for (i = 0; i < (gmem->nbins_x * gmem->nbins_y); i++) {
318 struct fd_tile *tile = &ctx->tile[i];
319
320 DBG("bin_h=%d, yoff=%d, bin_w=%d, xoff=%d",
321 tile->bin_h, tile->yoff, tile->bin_w, tile->xoff);
322
323 ctx->emit_tile_prep(batch, tile);
324
325 if (batch->restore) {
326 fd_hw_query_set_stage(ctx, batch->gmem, FD_STAGE_MEM2GMEM);
327 ctx->emit_tile_mem2gmem(batch, tile);
328 fd_hw_query_set_stage(ctx, batch->gmem, FD_STAGE_NULL);
329 }
330
331 ctx->emit_tile_renderprep(batch, tile);
332
333 fd_hw_query_prepare_tile(ctx, i, batch->gmem);
334
335 /* emit IB to drawcmds: */
336 ctx->emit_ib(batch->gmem, batch->draw);
337 fd_reset_wfi(ctx);
338
339 /* emit gmem2mem to transfer tile back to system memory: */
340 fd_hw_query_set_stage(ctx, batch->gmem, FD_STAGE_GMEM2MEM);
341 ctx->emit_tile_gmem2mem(batch, tile);
342 fd_hw_query_set_stage(ctx, batch->gmem, FD_STAGE_NULL);
343 }
344 }
345
346 static void
347 render_sysmem(struct fd_batch *batch)
348 {
349 struct fd_context *ctx = batch->ctx;
350
351 ctx->emit_sysmem_prep(batch);
352
353 fd_hw_query_prepare_tile(ctx, 0, batch->gmem);
354
355 /* emit IB to drawcmds: */
356 ctx->emit_ib(batch->gmem, batch->draw);
357 fd_reset_wfi(ctx);
358 }
359
360 void
361 fd_gmem_render_tiles(struct fd_batch *batch)
362 {
363 struct fd_context *ctx = batch->ctx;
364 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
365 bool sysmem = false;
366
367 if (ctx->emit_sysmem_prep) {
368 if (batch->cleared || batch->gmem_reason || (batch->num_draws > 5)) {
369 DBG("GMEM: cleared=%x, gmem_reason=%x, num_draws=%u",
370 batch->cleared, batch->gmem_reason, batch->num_draws);
371 } else if (!(fd_mesa_debug & FD_DBG_NOBYPASS)) {
372 sysmem = true;
373 }
374 }
375
376 /* close out the draw cmds by making sure any active queries are
377 * paused:
378 */
379 fd_hw_query_set_stage(ctx, batch->draw, FD_STAGE_NULL);
380
381 fd_reset_wfi(ctx);
382
383 ctx->stats.batch_total++;
384
385 if (sysmem) {
386 DBG("rendering sysmem (%s/%s)",
387 util_format_short_name(pipe_surface_format(pfb->cbufs[0])),
388 util_format_short_name(pipe_surface_format(pfb->zsbuf)));
389 fd_hw_query_prepare(ctx, 1);
390 render_sysmem(batch);
391 ctx->stats.batch_sysmem++;
392 } else {
393 struct fd_gmem_stateobj *gmem = &ctx->gmem;
394 calculate_tiles(batch);
395 DBG("rendering %dx%d tiles (%s/%s)", gmem->nbins_x, gmem->nbins_y,
396 util_format_short_name(pipe_surface_format(pfb->cbufs[0])),
397 util_format_short_name(pipe_surface_format(pfb->zsbuf)));
398 fd_hw_query_prepare(ctx, gmem->nbins_x * gmem->nbins_y);
399 render_tiles(batch);
400 ctx->stats.batch_gmem++;
401 }
402
403 fd_ringbuffer_flush(batch->gmem);
404
405 fd_reset_wfi(ctx);
406
407 ctx->dirty = ~0;
408 }
409
410 /* tile needs restore if it isn't completely contained within the
411 * cleared scissor:
412 */
413 static bool
414 skip_restore(struct pipe_scissor_state *scissor, struct fd_tile *tile)
415 {
416 unsigned minx = tile->xoff;
417 unsigned maxx = tile->xoff + tile->bin_w;
418 unsigned miny = tile->yoff;
419 unsigned maxy = tile->yoff + tile->bin_h;
420 return (minx >= scissor->minx) && (maxx <= scissor->maxx) &&
421 (miny >= scissor->miny) && (maxy <= scissor->maxy);
422 }
423
424 /* When deciding whether a tile needs mem2gmem, we need to take into
425 * account the scissor rect(s) that were cleared. To simplify we only
426 * consider the last scissor rect for each buffer, since the common
427 * case would be a single clear.
428 */
429 bool
430 fd_gmem_needs_restore(struct fd_batch *batch, struct fd_tile *tile,
431 uint32_t buffers)
432 {
433 if (!(batch->restore & buffers))
434 return false;
435
436 /* if buffers partially cleared, then slow-path to figure out
437 * if this particular tile needs restoring:
438 */
439 if ((buffers & FD_BUFFER_COLOR) &&
440 (batch->partial_cleared & FD_BUFFER_COLOR) &&
441 skip_restore(&batch->cleared_scissor.color, tile))
442 return false;
443 if ((buffers & FD_BUFFER_DEPTH) &&
444 (batch->partial_cleared & FD_BUFFER_DEPTH) &&
445 skip_restore(&batch->cleared_scissor.depth, tile))
446 return false;
447 if ((buffers & FD_BUFFER_STENCIL) &&
448 (batch->partial_cleared & FD_BUFFER_STENCIL) &&
449 skip_restore(&batch->cleared_scissor.stencil, tile))
450 return false;
451
452 return true;
453 }