freedreno/ir3: debug cleanup
[mesa.git] / src / gallium / drivers / freedreno / freedreno_perfcntr.h
1 /*
2 * Copyright (C) 2018 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #ifndef FREEDRENO_PERFCNTR_H_
28 #define FREEDRENO_PERFCNTR_H_
29
30 #include "pipe/p_defines.h"
31
32 /*
33 * Mapping very closely to the AMD_performance_monitor extension, adreno has
34 * groups of performance counters where each group has N counters, which can
35 * select from M different countables (things that can be counted), where
36 * generally M > N.
37 */
38
39 /* Describes a single counter: */
40 struct fd_perfcntr_counter {
41 /* offset of the select register to choose what to count: */
42 unsigned select_reg;
43 /* offset of the lo/hi 32b to read current counter value: */
44 unsigned counter_reg_lo;
45 unsigned counter_reg_hi;
46 /* Optional, most counters don't have enable/clear registers: */
47 unsigned enable;
48 unsigned clear;
49 };
50
51 /* Describes a single countable: */
52 struct fd_perfcntr_countable {
53 const char *name;
54 /* selector register enum value to select this countable: */
55 unsigned selector;
56
57 /* description of the countable: */
58 enum pipe_driver_query_type query_type;
59 enum pipe_driver_query_result_type result_type;
60 };
61
62 /* Describes an entire counter group: */
63 struct fd_perfcntr_group {
64 const char *name;
65 unsigned num_counters;
66 const struct fd_perfcntr_counter *counters;
67 unsigned num_countables;
68 const struct fd_perfcntr_countable *countables;
69 };
70
71
72 #endif /* FREEDRENO_PERFCNTR_H_ */