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[mesa.git] / src / gallium / drivers / freedreno / freedreno_screen.c
1 /*
2 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27
28 #include "pipe/p_defines.h"
29 #include "pipe/p_screen.h"
30 #include "pipe/p_state.h"
31
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/format/u_format.h"
35 #include "util/format/u_format_s3tc.h"
36 #include "util/u_screen.h"
37 #include "util/u_string.h"
38 #include "util/u_debug.h"
39
40 #include "util/os_time.h"
41
42 #include "drm-uapi/drm_fourcc.h"
43 #include <errno.h>
44 #include <stdio.h>
45 #include <stdlib.h>
46 #include <sys/sysinfo.h>
47
48 #include "freedreno_screen.h"
49 #include "freedreno_resource.h"
50 #include "freedreno_fence.h"
51 #include "freedreno_query.h"
52 #include "freedreno_util.h"
53
54 #include "a2xx/fd2_screen.h"
55 #include "a3xx/fd3_screen.h"
56 #include "a4xx/fd4_screen.h"
57 #include "a5xx/fd5_screen.h"
58 #include "a6xx/fd6_screen.h"
59
60
61 #include "ir3/ir3_nir.h"
62 #include "a2xx/ir2.h"
63
64 /* XXX this should go away */
65 #include "state_tracker/drm_driver.h"
66
67 static const struct debug_named_value debug_options[] = {
68 {"msgs", FD_DBG_MSGS, "Print debug messages"},
69 {"disasm", FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly (a2xx only, see IR3_SHADER_DEBUG)"},
70 {"dclear", FD_DBG_DCLEAR, "Mark all state dirty after clear"},
71 {"ddraw", FD_DBG_DDRAW, "Mark all state dirty after draw"},
72 {"noscis", FD_DBG_NOSCIS, "Disable scissor optimization"},
73 {"direct", FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
74 {"nobypass", FD_DBG_NOBYPASS, "Disable GMEM bypass"},
75 {"fraghalf", FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
76 {"nobin", FD_DBG_NOBIN, "Disable hw binning"},
77 {"nogmem", FD_DBG_NOGMEM, "Disable GMEM rendering (bypass only)"},
78 {"glsl120", FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
79 {"shaderdb", FD_DBG_SHADERDB, "Enable shaderdb output"},
80 {"flush", FD_DBG_FLUSH, "Force flush after every draw"},
81 {"deqp", FD_DBG_DEQP, "Enable dEQP hacks"},
82 {"inorder", FD_DBG_INORDER,"Disable reordering for draws/blits"},
83 {"bstat", FD_DBG_BSTAT, "Print batch stats at context destroy"},
84 {"nogrow", FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
85 {"lrz", FD_DBG_LRZ, "Enable experimental LRZ support (a5xx)"},
86 {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
87 {"noblit", FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
88 {"hiprio", FD_DBG_HIPRIO, "Force high-priority context"},
89 {"ttile", FD_DBG_TTILE, "Enable texture tiling (a2xx/a3xx/a5xx)"},
90 {"perfcntrs", FD_DBG_PERFC, "Expose performance counters"},
91 {"noubwc", FD_DBG_NOUBWC, "Disable UBWC for all internal buffers"},
92 {"nolrz", FD_DBG_NOLRZ, "Disable LRZ (a6xx)"},
93 {"notile", FD_DBG_NOTILE, "Disable tiling for all internal buffers"},
94 DEBUG_NAMED_VALUE_END
95 };
96
97 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
98
99 int fd_mesa_debug = 0;
100 bool fd_binning_enabled = true;
101 static bool glsl120 = false;
102
103 static const char *
104 fd_screen_get_name(struct pipe_screen *pscreen)
105 {
106 static char buffer[128];
107 snprintf(buffer, sizeof(buffer), "FD%03d",
108 fd_screen(pscreen)->device_id);
109 return buffer;
110 }
111
112 static const char *
113 fd_screen_get_vendor(struct pipe_screen *pscreen)
114 {
115 return "freedreno";
116 }
117
118 static const char *
119 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
120 {
121 return "Qualcomm";
122 }
123
124
125 static uint64_t
126 fd_screen_get_timestamp(struct pipe_screen *pscreen)
127 {
128 struct fd_screen *screen = fd_screen(pscreen);
129
130 if (screen->has_timestamp) {
131 uint64_t n;
132 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
133 debug_assert(screen->max_freq > 0);
134 return n * 1000000000 / screen->max_freq;
135 } else {
136 int64_t cpu_time = os_time_get() * 1000;
137 return cpu_time + screen->cpu_gpu_time_delta;
138 }
139
140 }
141
142 static void
143 fd_screen_destroy(struct pipe_screen *pscreen)
144 {
145 struct fd_screen *screen = fd_screen(pscreen);
146
147 if (screen->pipe)
148 fd_pipe_del(screen->pipe);
149
150 if (screen->dev)
151 fd_device_del(screen->dev);
152
153 if (screen->ro)
154 FREE(screen->ro);
155
156 fd_bc_fini(&screen->batch_cache);
157 fd_gmem_screen_fini(pscreen);
158
159 slab_destroy_parent(&screen->transfer_pool);
160
161 mtx_destroy(&screen->lock);
162
163 ralloc_free(screen->compiler);
164
165 free(screen->perfcntr_queries);
166 free(screen);
167 }
168
169 /*
170 TODO either move caps to a2xx/a3xx specific code, or maybe have some
171 tables for things that differ if the delta is not too much..
172 */
173 static int
174 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
175 {
176 struct fd_screen *screen = fd_screen(pscreen);
177
178 /* this is probably not totally correct.. but it's a start: */
179 switch (param) {
180 /* Supported features (boolean caps). */
181 case PIPE_CAP_NPOT_TEXTURES:
182 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
183 case PIPE_CAP_ANISOTROPIC_FILTER:
184 case PIPE_CAP_POINT_SPRITE:
185 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
186 case PIPE_CAP_TEXTURE_SWIZZLE:
187 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
188 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
189 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
190 case PIPE_CAP_SEAMLESS_CUBE_MAP:
191 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
192 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
193 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
194 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
195 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
196 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
197 case PIPE_CAP_STRING_MARKER:
198 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
199 case PIPE_CAP_TEXTURE_BARRIER:
200 case PIPE_CAP_INVALIDATE_BUFFER:
201 case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
202 return 1;
203
204 case PIPE_CAP_PACKED_UNIFORMS:
205 return !is_a2xx(screen);
206
207 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
208 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
209 return screen->has_robustness;
210
211 case PIPE_CAP_VERTEXID_NOBASE:
212 return is_a3xx(screen) || is_a4xx(screen);
213
214 case PIPE_CAP_COMPUTE:
215 return has_compute(screen);
216
217 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
218 case PIPE_CAP_PCI_GROUP:
219 case PIPE_CAP_PCI_BUS:
220 case PIPE_CAP_PCI_DEVICE:
221 case PIPE_CAP_PCI_FUNCTION:
222 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
223 return 0;
224
225 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
226 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
227 case PIPE_CAP_VERTEX_SHADER_SATURATE:
228 case PIPE_CAP_PRIMITIVE_RESTART:
229 case PIPE_CAP_TGSI_INSTANCEID:
230 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
231 case PIPE_CAP_INDEP_BLEND_ENABLE:
232 case PIPE_CAP_INDEP_BLEND_FUNC:
233 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
234 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
235 case PIPE_CAP_CONDITIONAL_RENDER:
236 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
237 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
238 case PIPE_CAP_CLIP_HALFZ:
239 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
240
241 case PIPE_CAP_FAKE_SW_MSAA:
242 return !fd_screen_get_param(pscreen, PIPE_CAP_TEXTURE_MULTISAMPLE);
243
244 case PIPE_CAP_TEXTURE_MULTISAMPLE:
245 return is_a5xx(screen) || is_a6xx(screen);
246
247 case PIPE_CAP_SURFACE_SAMPLE_COUNT:
248 return is_a6xx(screen);
249
250 case PIPE_CAP_DEPTH_CLIP_DISABLE:
251 return is_a3xx(screen) || is_a4xx(screen);
252
253 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
254 return is_a5xx(screen) || is_a6xx(screen);
255
256 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
257 if (is_a3xx(screen)) return 16;
258 if (is_a4xx(screen)) return 32;
259 if (is_a5xx(screen)) return 32;
260 if (is_a6xx(screen)) return 64;
261 return 0;
262 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
263 /* We could possibly emulate more by pretending 2d/rect textures and
264 * splitting high bits of index into 2nd dimension..
265 */
266 if (is_a3xx(screen)) return 8192;
267 if (is_a4xx(screen)) return 16384;
268 if (is_a5xx(screen)) return 16384;
269 if (is_a6xx(screen)) return 1 << 27;
270 return 0;
271
272 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
273 case PIPE_CAP_CUBE_MAP_ARRAY:
274 case PIPE_CAP_SAMPLER_VIEW_TARGET:
275 case PIPE_CAP_TEXTURE_QUERY_LOD:
276 return is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
277
278 case PIPE_CAP_START_INSTANCE:
279 /* Note that a5xx can do this, it just can't (at least with
280 * current firmware) do draw_indirect with base_instance.
281 * Since draw_indirect is needed sooner (gles31 and gl40 vs
282 * gl42), hide base_instance on a5xx. :-/
283 */
284 return is_a4xx(screen);
285
286 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
287 return 64;
288
289 case PIPE_CAP_GLSL_FEATURE_LEVEL:
290 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
291 if (glsl120)
292 return 120;
293 return is_ir3(screen) ? 140 : 120;
294
295 case PIPE_CAP_ESSL_FEATURE_LEVEL:
296 /* we can probably enable 320 for a5xx too, but need to test: */
297 if (is_a6xx(screen)) return 320;
298 if (is_a5xx(screen)) return 310;
299 if (is_ir3(screen)) return 300;
300 return 120;
301
302 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
303 if (is_a6xx(screen)) return 64;
304 if (is_a5xx(screen)) return 4;
305 return 0;
306
307 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
308 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
309 return 4;
310 return 0;
311
312 /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
313 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
314 return 0;
315
316 case PIPE_CAP_FBFETCH:
317 if (fd_device_version(screen->dev) >= FD_VERSION_GMEM_BASE &&
318 is_a6xx(screen))
319 return 1;
320 return 0;
321 case PIPE_CAP_SAMPLE_SHADING:
322 if (is_a6xx(screen)) return 1;
323 return 0;
324
325 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
326 return screen->priority_mask;
327
328 case PIPE_CAP_DRAW_INDIRECT:
329 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
330 return 1;
331 return 0;
332
333 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
334 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
335 return 1;
336 return 0;
337
338 case PIPE_CAP_LOAD_CONSTBUF:
339 /* name is confusing, but this turns on std430 packing */
340 if (is_ir3(screen))
341 return 1;
342 return 0;
343
344 case PIPE_CAP_MAX_VIEWPORTS:
345 return 1;
346
347 case PIPE_CAP_MAX_VARYINGS:
348 return 16;
349
350 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
351 /* We don't really have a limit on this, it all goes into the main
352 * memory buffer. Needs to be at least 120 / 4 (minimum requirement
353 * for GL_MAX_TESS_PATCH_COMPONENTS).
354 */
355 return 128;
356
357 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
358 return 64 * 1024 * 1024;
359
360 case PIPE_CAP_SHAREABLE_SHADERS:
361 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
362 /* manage the variants for these ourself, to avoid breaking precompile: */
363 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
364 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
365 if (is_ir3(screen))
366 return 1;
367 return 0;
368
369 /* Geometry shaders.. */
370 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
371 return 512;
372 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
373 return 2048;
374 case PIPE_CAP_MAX_GS_INVOCATIONS:
375 return 32;
376
377 /* Stream output. */
378 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
379 if (is_ir3(screen))
380 return PIPE_MAX_SO_BUFFERS;
381 return 0;
382 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
383 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
384 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
385 if (is_ir3(screen))
386 return 1;
387 return 0;
388 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
389 return 1;
390 case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
391 return is_a2xx(screen);
392 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
393 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
394 if (is_ir3(screen))
395 return 16 * 4; /* should only be shader out limit? */
396 return 0;
397
398 /* Texturing. */
399 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
400 return 1 << (MAX_MIP_LEVELS - 1);
401 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
402 return MAX_MIP_LEVELS;
403 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
404 return 11;
405
406 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
407 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 256 : 0;
408
409 /* Render targets. */
410 case PIPE_CAP_MAX_RENDER_TARGETS:
411 return screen->max_rts;
412 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
413 return is_a3xx(screen) ? 1 : 0;
414
415 /* Queries. */
416 case PIPE_CAP_OCCLUSION_QUERY:
417 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
418 case PIPE_CAP_QUERY_TIMESTAMP:
419 case PIPE_CAP_QUERY_TIME_ELAPSED:
420 /* only a4xx, requires new enough kernel so we know max_freq: */
421 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen));
422
423 case PIPE_CAP_VENDOR_ID:
424 return 0x5143;
425 case PIPE_CAP_DEVICE_ID:
426 return 0xFFFFFFFF;
427 case PIPE_CAP_ACCELERATED:
428 return 1;
429 case PIPE_CAP_VIDEO_MEMORY:
430 DBG("FINISHME: The value returned is incorrect\n");
431 return 10;
432 case PIPE_CAP_UMA:
433 return 1;
434 case PIPE_CAP_NATIVE_FENCE_FD:
435 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
436 default:
437 return u_pipe_screen_get_param_defaults(pscreen, param);
438 }
439 }
440
441 static float
442 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
443 {
444 switch (param) {
445 case PIPE_CAPF_MAX_LINE_WIDTH:
446 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
447 /* NOTE: actual value is 127.0f, but this is working around a deqp
448 * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
449 * uses too small of a render target size, and gets confused when
450 * the lines start going offscreen.
451 *
452 * See: https://code.google.com/p/android/issues/detail?id=206513
453 */
454 if (fd_mesa_debug & FD_DBG_DEQP)
455 return 48.0f;
456 return 127.0f;
457 case PIPE_CAPF_MAX_POINT_WIDTH:
458 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
459 return 4092.0f;
460 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
461 return 16.0f;
462 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
463 return 15.0f;
464 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
465 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
466 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
467 return 0.0f;
468 }
469 debug_printf("unknown paramf %d\n", param);
470 return 0;
471 }
472
473 static int
474 fd_screen_get_shader_param(struct pipe_screen *pscreen,
475 enum pipe_shader_type shader,
476 enum pipe_shader_cap param)
477 {
478 struct fd_screen *screen = fd_screen(pscreen);
479
480 switch(shader)
481 {
482 case PIPE_SHADER_FRAGMENT:
483 case PIPE_SHADER_VERTEX:
484 break;
485 case PIPE_SHADER_TESS_CTRL:
486 case PIPE_SHADER_TESS_EVAL:
487 case PIPE_SHADER_GEOMETRY:
488 if (is_a6xx(screen))
489 break;
490 return 0;
491 case PIPE_SHADER_COMPUTE:
492 if (has_compute(screen))
493 break;
494 return 0;
495 default:
496 DBG("unknown shader type %d", shader);
497 return 0;
498 }
499
500 /* this is probably not totally correct.. but it's a start: */
501 switch (param) {
502 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
503 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
504 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
505 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
506 return 16384;
507 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
508 return 8; /* XXX */
509 case PIPE_SHADER_CAP_MAX_INPUTS:
510 case PIPE_SHADER_CAP_MAX_OUTPUTS:
511 return 16;
512 case PIPE_SHADER_CAP_MAX_TEMPS:
513 return 64; /* Max native temporaries. */
514 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
515 /* NOTE: seems to be limit for a3xx is actually 512 but
516 * split between VS and FS. Use lower limit of 256 to
517 * avoid getting into impossible situations:
518 */
519 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 4096 : 64) * sizeof(float[4]);
520 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
521 return is_ir3(screen) ? 16 : 1;
522 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
523 return 1;
524 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
525 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
526 /* Technically this should be the same as for TEMP/CONST, since
527 * everything is just normal registers. This is just temporary
528 * hack until load_input/store_output handle arrays in a similar
529 * way as load_var/store_var..
530 *
531 * For tessellation stages, inputs are loaded using ldlw or ldg, both
532 * of which support indirection.
533 */
534 return shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL;
535 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
536 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
537 /* a2xx compiler doesn't handle indirect: */
538 return is_ir3(screen) ? 1 : 0;
539 case PIPE_SHADER_CAP_SUBROUTINES:
540 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
541 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
542 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
543 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
544 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
545 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
546 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
547 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
548 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
549 return 0;
550 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
551 return 1;
552 case PIPE_SHADER_CAP_INTEGERS:
553 if (glsl120)
554 return 0;
555 return is_ir3(screen) ? 1 : 0;
556 case PIPE_SHADER_CAP_INT64_ATOMICS:
557 return 0;
558 case PIPE_SHADER_CAP_FP16:
559 return 0;
560 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
561 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
562 return 16;
563 case PIPE_SHADER_CAP_PREFERRED_IR:
564 return PIPE_SHADER_IR_NIR;
565 case PIPE_SHADER_CAP_SUPPORTED_IRS:
566 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
567 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
568 return 32;
569 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
570 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
571 if (is_a5xx(screen) || is_a6xx(screen)) {
572 /* a5xx (and a4xx for that matter) has one state-block
573 * for compute-shader SSBO's and another that is shared
574 * by VS/HS/DS/GS/FS.. so to simplify things for now
575 * just advertise SSBOs for FS and CS. We could possibly
576 * do what blob does, and partition the space for
577 * VS/HS/DS/GS/FS. The blob advertises:
578 *
579 * GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
580 * GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
581 * GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
582 * GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
583 * GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
584 * GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
585 * GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
586 *
587 * I think that way we could avoid having to patch shaders
588 * for actual SSBO indexes by using a static partitioning.
589 *
590 * Note same state block is used for images and buffers,
591 * but images also need texture state for read access
592 * (isam/isam.3d)
593 */
594 switch(shader)
595 {
596 case PIPE_SHADER_FRAGMENT:
597 case PIPE_SHADER_COMPUTE:
598 return 24;
599 default:
600 return 0;
601 }
602 }
603 return 0;
604 }
605 debug_printf("unknown shader param %d\n", param);
606 return 0;
607 }
608
609 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
610 * into per-generation backend?
611 */
612 static int
613 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
614 enum pipe_compute_cap param, void *ret)
615 {
616 struct fd_screen *screen = fd_screen(pscreen);
617 const char * const ir = "ir3";
618
619 if (!has_compute(screen))
620 return 0;
621
622 #define RET(x) do { \
623 if (ret) \
624 memcpy(ret, x, sizeof(x)); \
625 return sizeof(x); \
626 } while (0)
627
628 switch (param) {
629 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
630 // don't expose 64b pointer support yet, until ir3 supports 64b
631 // math, otherwise spir64 target is used and we get 64b pointer
632 // calculations that we can't do yet
633 // if (is_a5xx(screen))
634 // RET((uint32_t []){ 64 });
635 RET((uint32_t []){ 32 });
636
637 case PIPE_COMPUTE_CAP_IR_TARGET:
638 if (ret)
639 sprintf(ret, "%s", ir);
640 return strlen(ir) * sizeof(char);
641
642 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
643 RET((uint64_t []) { 3 });
644
645 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
646 RET(((uint64_t []) { 65535, 65535, 65535 }));
647
648 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
649 RET(((uint64_t []) { 1024, 1024, 64 }));
650
651 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
652 RET((uint64_t []) { 1024 });
653
654 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
655 RET((uint64_t []) { screen->ram_size });
656
657 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
658 RET((uint64_t []) { 32768 });
659
660 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
661 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
662 RET((uint64_t []) { 4096 });
663
664 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
665 RET((uint64_t []) { screen->ram_size });
666
667 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
668 RET((uint32_t []) { screen->max_freq / 1000000 });
669
670 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
671 RET((uint32_t []) { 9999 }); // TODO
672
673 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
674 RET((uint32_t []) { 1 });
675
676 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
677 RET((uint32_t []) { 32 }); // TODO
678
679 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
680 RET((uint64_t []) { 1024 }); // TODO
681 }
682
683 return 0;
684 }
685
686 static const void *
687 fd_get_compiler_options(struct pipe_screen *pscreen,
688 enum pipe_shader_ir ir, unsigned shader)
689 {
690 struct fd_screen *screen = fd_screen(pscreen);
691
692 if (is_ir3(screen))
693 return ir3_get_compiler_options(screen->compiler);
694
695 return ir2_get_compiler_options();
696 }
697
698 bool
699 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
700 struct fd_bo *bo,
701 struct renderonly_scanout *scanout,
702 unsigned stride,
703 struct winsys_handle *whandle)
704 {
705 whandle->stride = stride;
706
707 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
708 return fd_bo_get_name(bo, &whandle->handle) == 0;
709 } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
710 if (renderonly_get_handle(scanout, whandle))
711 return true;
712 whandle->handle = fd_bo_handle(bo);
713 return true;
714 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
715 whandle->handle = fd_bo_dmabuf(bo);
716 return true;
717 } else {
718 return false;
719 }
720 }
721
722 static void
723 fd_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
724 enum pipe_format format,
725 int max, uint64_t *modifiers,
726 unsigned int *external_only,
727 int *count)
728 {
729 struct fd_screen *screen = fd_screen(pscreen);
730 int i, num = 0;
731
732 max = MIN2(max, screen->num_supported_modifiers);
733
734 if (!max) {
735 max = screen->num_supported_modifiers;
736 external_only = NULL;
737 modifiers = NULL;
738 }
739
740 for (i = 0; i < max; i++) {
741 if (modifiers)
742 modifiers[num] = screen->supported_modifiers[i];
743
744 if (external_only)
745 external_only[num] = 0;
746
747 num++;
748 }
749
750 *count = num;
751 }
752
753 struct fd_bo *
754 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
755 struct winsys_handle *whandle)
756 {
757 struct fd_screen *screen = fd_screen(pscreen);
758 struct fd_bo *bo;
759
760 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
761 bo = fd_bo_from_name(screen->dev, whandle->handle);
762 } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
763 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
764 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
765 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
766 } else {
767 DBG("Attempt to import unsupported handle type %d", whandle->type);
768 return NULL;
769 }
770
771 if (!bo) {
772 DBG("ref name 0x%08x failed", whandle->handle);
773 return NULL;
774 }
775
776 return bo;
777 }
778
779 static void _fd_fence_ref(struct pipe_screen *pscreen,
780 struct pipe_fence_handle **ptr,
781 struct pipe_fence_handle *pfence)
782 {
783 fd_fence_ref(ptr, pfence);
784 }
785
786 struct pipe_screen *
787 fd_screen_create(struct fd_device *dev, struct renderonly *ro)
788 {
789 struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
790 struct pipe_screen *pscreen;
791 uint64_t val;
792
793 fd_mesa_debug = debug_get_option_fd_mesa_debug();
794
795 if (fd_mesa_debug & FD_DBG_NOBIN)
796 fd_binning_enabled = false;
797
798 glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
799
800 if (!screen)
801 return NULL;
802
803 pscreen = &screen->base;
804
805 screen->dev = dev;
806 screen->refcnt = 1;
807
808 if (ro) {
809 screen->ro = renderonly_dup(ro);
810 if (!screen->ro) {
811 DBG("could not create renderonly object");
812 goto fail;
813 }
814 }
815
816 // maybe this should be in context?
817 screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
818 if (!screen->pipe) {
819 DBG("could not create 3d pipe");
820 goto fail;
821 }
822
823 if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
824 DBG("could not get GMEM size");
825 goto fail;
826 }
827 screen->gmemsize_bytes = val;
828
829 if (fd_device_version(dev) >= FD_VERSION_GMEM_BASE) {
830 fd_pipe_get_param(screen->pipe, FD_GMEM_BASE, &screen->gmem_base);
831 }
832
833 if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
834 DBG("could not get device-id");
835 goto fail;
836 }
837 screen->device_id = val;
838
839 if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
840 DBG("could not get gpu freq");
841 /* this limits what performance related queries are
842 * supported but is not fatal
843 */
844 screen->max_freq = 0;
845 } else {
846 screen->max_freq = val;
847 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
848 screen->has_timestamp = true;
849 }
850
851 if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
852 DBG("could not get gpu-id");
853 goto fail;
854 }
855 screen->gpu_id = val;
856
857 if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
858 DBG("could not get chip-id");
859 /* older kernels may not have this property: */
860 unsigned core = screen->gpu_id / 100;
861 unsigned major = (screen->gpu_id % 100) / 10;
862 unsigned minor = screen->gpu_id % 10;
863 unsigned patch = 0; /* assume the worst */
864 val = (patch & 0xff) | ((minor & 0xff) << 8) |
865 ((major & 0xff) << 16) | ((core & 0xff) << 24);
866 }
867 screen->chip_id = val;
868
869 if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) {
870 DBG("could not get # of rings");
871 screen->priority_mask = 0;
872 } else {
873 /* # of rings equates to number of unique priority values: */
874 screen->priority_mask = (1 << val) - 1;
875 }
876
877 if ((fd_device_version(dev) >= FD_VERSION_ROBUSTNESS) &&
878 (fd_pipe_get_param(screen->pipe, FD_PP_PGTABLE, &val) == 0)) {
879 screen->has_robustness = val;
880 }
881
882 struct sysinfo si;
883 sysinfo(&si);
884 screen->ram_size = si.totalram;
885
886 DBG("Pipe Info:");
887 DBG(" GPU-id: %d", screen->gpu_id);
888 DBG(" Chip-id: 0x%08x", screen->chip_id);
889 DBG(" GMEM size: 0x%08x", screen->gmemsize_bytes);
890
891 /* explicitly checking for GPU revisions that are known to work. This
892 * may be overly conservative for a3xx, where spoofing the gpu_id with
893 * the blob driver seems to generate identical cmdstream dumps. But
894 * on a2xx, there seem to be small differences between the GPU revs
895 * so it is probably better to actually test first on real hardware
896 * before enabling:
897 *
898 * If you have a different adreno version, feel free to add it to one
899 * of the cases below and see what happens. And if it works, please
900 * send a patch ;-)
901 */
902 switch (screen->gpu_id) {
903 case 200:
904 case 201:
905 case 205:
906 case 220:
907 fd2_screen_init(pscreen);
908 break;
909 case 305:
910 case 307:
911 case 320:
912 case 330:
913 fd3_screen_init(pscreen);
914 break;
915 case 420:
916 case 430:
917 fd4_screen_init(pscreen);
918 break;
919 case 510:
920 case 530:
921 case 540:
922 fd5_screen_init(pscreen);
923 break;
924 case 618:
925 case 630:
926 case 640:
927 fd6_screen_init(pscreen);
928 break;
929 default:
930 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
931 goto fail;
932 }
933
934 if (screen->gpu_id >= 600) {
935 screen->gmem_alignw = 32;
936 screen->gmem_alignh = 32;
937 screen->num_vsc_pipes = 32;
938 } else if (screen->gpu_id >= 500) {
939 screen->gmem_alignw = 64;
940 screen->gmem_alignh = 32;
941 screen->num_vsc_pipes = 16;
942 } else {
943 screen->gmem_alignw = 32;
944 screen->gmem_alignh = 32;
945 screen->num_vsc_pipes = 8;
946 }
947
948 if (fd_mesa_debug & FD_DBG_PERFC) {
949 screen->perfcntr_groups = fd_perfcntrs(screen->gpu_id,
950 &screen->num_perfcntr_groups);
951 }
952
953 /* NOTE: don't enable if we have too old of a kernel to support
954 * growable cmdstream buffers, since memory requirement for cmdstream
955 * buffers would be too much otherwise.
956 */
957 if (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS)
958 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
959
960 fd_bc_init(&screen->batch_cache);
961
962 (void) mtx_init(&screen->lock, mtx_plain);
963
964 pscreen->destroy = fd_screen_destroy;
965 pscreen->get_param = fd_screen_get_param;
966 pscreen->get_paramf = fd_screen_get_paramf;
967 pscreen->get_shader_param = fd_screen_get_shader_param;
968 pscreen->get_compute_param = fd_get_compute_param;
969 pscreen->get_compiler_options = fd_get_compiler_options;
970
971 fd_resource_screen_init(pscreen);
972 fd_query_screen_init(pscreen);
973 fd_gmem_screen_init(pscreen);
974
975 pscreen->get_name = fd_screen_get_name;
976 pscreen->get_vendor = fd_screen_get_vendor;
977 pscreen->get_device_vendor = fd_screen_get_device_vendor;
978
979 pscreen->get_timestamp = fd_screen_get_timestamp;
980
981 pscreen->fence_reference = _fd_fence_ref;
982 pscreen->fence_finish = fd_fence_finish;
983 pscreen->fence_get_fd = fd_fence_get_fd;
984
985 pscreen->query_dmabuf_modifiers = fd_screen_query_dmabuf_modifiers;
986
987 if (!screen->supported_modifiers) {
988 static const uint64_t supported_modifiers[] = {
989 DRM_FORMAT_MOD_LINEAR,
990 };
991
992 screen->supported_modifiers = supported_modifiers;
993 screen->num_supported_modifiers = ARRAY_SIZE(supported_modifiers);
994 }
995
996 slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
997
998 return pscreen;
999
1000 fail:
1001 fd_screen_destroy(pscreen);
1002 return NULL;
1003 }