src/gallium/drivers/freedreno/freedreno_screen.c

   1 /*
   2  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27
  28 #include "pipe/p_defines.h"
  29 #include "pipe/p_screen.h"
  30 #include "pipe/p_state.h"
  31
  32 #include "util/u_memory.h"
  33 #include "util/u_inlines.h"
  34 #include "util/format/u_format.h"
  35 #include "util/format/u_format_s3tc.h"
  36 #include "util/u_screen.h"
  37 #include "util/u_string.h"
  38 #include "util/u_debug.h"
  39
  40 #include "util/os_time.h"
  41
  42 #include "drm-uapi/drm_fourcc.h"
  43 #include <errno.h>
  44 #include <stdio.h>
  45 #include <stdlib.h>
  46 #include <sys/sysinfo.h>
  47
  48 #include "freedreno_screen.h"
  49 #include "freedreno_resource.h"
  50 #include "freedreno_fence.h"
  51 #include "freedreno_query.h"
  52 #include "freedreno_util.h"
  53
  54 #include "a2xx/fd2_screen.h"
  55 #include "a3xx/fd3_screen.h"
  56 #include "a4xx/fd4_screen.h"
  57 #include "a5xx/fd5_screen.h"
  58 #include "a6xx/fd6_screen.h"
  59
  60 /* for fd_get_driver/device_uuid() */
  61 #include "common/freedreno_uuid.h"
  62
  63 #include "ir3/ir3_nir.h"
  64 #include "ir3/ir3_compiler.h"
  65 #include "a2xx/ir2.h"
  66
  67 static const struct debug_named_value debug_options[] = {
  68                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  69                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly (a2xx only, see IR3_SHADER_DEBUG)"},
  70                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  71                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  72                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  73                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  74                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  75                 {"log",       FD_DBG_LOG,    "Enable GPU timestamp based logging (a6xx+)"},
  76                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  77                 {"nogmem",    FD_DBG_NOGMEM,  "Disable GMEM rendering (bypass only)"},
  78                 /* BIT(10) */
  79                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  80                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  81                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  82                 {"inorder",   FD_DBG_INORDER,"Disable reordering for draws/blits"},
  83                 {"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
  84                 {"nogrow",    FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
  85                 {"lrz",       FD_DBG_LRZ,    "Enable experimental LRZ support (a5xx)"},
  86                 {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
  87                 {"noblit",    FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
  88                 {"hiprio",    FD_DBG_HIPRIO, "Force high-priority context"},
  89                 {"ttile",     FD_DBG_TTILE,  "Enable texture tiling (a2xx/a3xx/a5xx)"},
  90                 {"perfcntrs", FD_DBG_PERFC,  "Expose performance counters"},
  91                 {"noubwc",    FD_DBG_NOUBWC, "Disable UBWC for all internal buffers"},
  92                 {"nolrz",     FD_DBG_NOLRZ,  "Disable LRZ (a6xx)"},
  93                 {"notile",    FD_DBG_NOTILE, "Disable tiling for all internal buffers"},
  94                 {"layout",    FD_DBG_LAYOUT, "Dump resource layouts"},
  95                 {"nofp16",    FD_DBG_NOFP16, "Disable mediump precision lowering"},
  96                 {"nohw",      FD_DBG_NOHW,   "Disable submitting commands to the HW"},
  97                 DEBUG_NAMED_VALUE_END
  98 };
  99
 100 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
 101
 102 int fd_mesa_debug = 0;
 103 bool fd_binning_enabled = true;
 104
 105 static const char *
 106 fd_screen_get_name(struct pipe_screen *pscreen)
 107 {
 108         static char buffer[128];
 109         snprintf(buffer, sizeof(buffer), "FD%03d",
 110                         fd_screen(pscreen)->device_id);
 111         return buffer;
 112 }
 113
 114 static const char *
 115 fd_screen_get_vendor(struct pipe_screen *pscreen)
 116 {
 117         return "freedreno";
 118 }
 119
 120 static const char *
 121 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 122 {
 123         return "Qualcomm";
 124 }
 125
 126
 127 static uint64_t
 128 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 129 {
 130         struct fd_screen *screen = fd_screen(pscreen);
 131
 132         if (screen->has_timestamp) {
 133                 uint64_t n;
 134                 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
 135                 debug_assert(screen->max_freq > 0);
 136                 return n * 1000000000 / screen->max_freq;
 137         } else {
 138                 int64_t cpu_time = os_time_get() * 1000;
 139                 return cpu_time + screen->cpu_gpu_time_delta;
 140         }
 141
 142 }
 143
 144 static void
 145 fd_screen_destroy(struct pipe_screen *pscreen)
 146 {
 147         struct fd_screen *screen = fd_screen(pscreen);
 148
 149         if (screen->pipe)
 150                 fd_pipe_del(screen->pipe);
 151
 152         if (screen->dev)
 153                 fd_device_del(screen->dev);
 154
 155         if (screen->ro)
 156                 FREE(screen->ro);
 157
 158         fd_bc_fini(&screen->batch_cache);
 159         fd_gmem_screen_fini(pscreen);
 160
 161         slab_destroy_parent(&screen->transfer_pool);
 162
 163         simple_mtx_destroy(&screen->lock);
 164
 165         if (screen->compiler)
 166                 ir3_compiler_destroy(screen->compiler);
 167
 168         ralloc_free(screen->live_batches);
 169
 170         free(screen->perfcntr_queries);
 171         free(screen);
 172 }
 173
 174 /*
 175 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 176 tables for things that differ if the delta is not too much..
 177  */
 178 static int
 179 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 180 {
 181         struct fd_screen *screen = fd_screen(pscreen);
 182
 183         /* this is probably not totally correct.. but it's a start: */
 184         switch (param) {
 185         /* Supported features (boolean caps). */
 186         case PIPE_CAP_NPOT_TEXTURES:
 187         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 188         case PIPE_CAP_ANISOTROPIC_FILTER:
 189         case PIPE_CAP_POINT_SPRITE:
 190         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 191         case PIPE_CAP_TEXTURE_SWIZZLE:
 192         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 193         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 194         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 195         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 196         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 197         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 198         case PIPE_CAP_STRING_MARKER:
 199         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 200         case PIPE_CAP_TEXTURE_BARRIER:
 201         case PIPE_CAP_INVALIDATE_BUFFER:
 202         case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 203         case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 204         case PIPE_CAP_NIR_COMPACT_ARRAYS:
 205                 return 1;
 206
 207         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 208         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 209         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 210                 return !is_a2xx(screen);
 211
 212         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 213                 return is_a2xx(screen);
 214         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 215                 return !is_a2xx(screen);
 216
 217         case PIPE_CAP_PACKED_UNIFORMS:
 218                 return !is_a2xx(screen);
 219
 220         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 221         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 222                 return screen->has_robustness;
 223
 224         case PIPE_CAP_VERTEXID_NOBASE:
 225                 return is_a3xx(screen) || is_a4xx(screen);
 226
 227         case PIPE_CAP_COMPUTE:
 228                 return has_compute(screen);
 229
 230         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 231         case PIPE_CAP_PCI_GROUP:
 232         case PIPE_CAP_PCI_BUS:
 233         case PIPE_CAP_PCI_DEVICE:
 234         case PIPE_CAP_PCI_FUNCTION:
 235                 return 0;
 236
 237         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 238         case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
 239         case PIPE_CAP_VERTEX_SHADER_SATURATE:
 240         case PIPE_CAP_PRIMITIVE_RESTART:
 241         case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
 242         case PIPE_CAP_TGSI_INSTANCEID:
 243         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 244         case PIPE_CAP_INDEP_BLEND_ENABLE:
 245         case PIPE_CAP_INDEP_BLEND_FUNC:
 246         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 247         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 248         case PIPE_CAP_CONDITIONAL_RENDER:
 249         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 250         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 251         case PIPE_CAP_CLIP_HALFZ:
 252                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 253
 254         case PIPE_CAP_FAKE_SW_MSAA:
 255                 return !fd_screen_get_param(pscreen, PIPE_CAP_TEXTURE_MULTISAMPLE);
 256
 257         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 258                 return is_a5xx(screen) || is_a6xx(screen);
 259
 260         case PIPE_CAP_SURFACE_SAMPLE_COUNT:
 261                 return is_a6xx(screen);
 262
 263         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 264                 return is_a3xx(screen) || is_a4xx(screen) || is_a6xx(screen);
 265
 266         case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 267                 return is_a6xx(screen);
 268
 269         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 270                 return is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 271
 272         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 273                 if (is_a3xx(screen)) return 16;
 274                 if (is_a4xx(screen)) return 32;
 275                 if (is_a5xx(screen)) return 32;
 276                 if (is_a6xx(screen)) return 64;
 277                 return 0;
 278         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 279                 /* We could possibly emulate more by pretending 2d/rect textures and
 280                  * splitting high bits of index into 2nd dimension..
 281                  */
 282                 if (is_a3xx(screen)) return 8192;
 283                 if (is_a4xx(screen)) return 16384;
 284                 if (is_a5xx(screen)) return 16384;
 285                 if (is_a6xx(screen)) return 1 << 27;
 286                 return 0;
 287
 288         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 289         case PIPE_CAP_CUBE_MAP_ARRAY:
 290         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 291         case PIPE_CAP_TEXTURE_QUERY_LOD:
 292                 return is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 293
 294         case PIPE_CAP_START_INSTANCE:
 295                 /* Note that a5xx can do this, it just can't (at least with
 296                  * current firmware) do draw_indirect with base_instance.
 297                  * Since draw_indirect is needed sooner (gles31 and gl40 vs
 298                  * gl42), hide base_instance on a5xx.  :-/
 299                  */
 300                 return is_a4xx(screen);
 301
 302         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 303                 return is_a2xx(screen) ? 64 : 32;
 304
 305         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 306         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 307                 return is_ir3(screen) ? 140 : 120;
 308
 309         case PIPE_CAP_ESSL_FEATURE_LEVEL:
 310                 /* we can probably enable 320 for a5xx too, but need to test: */
 311                 if (is_a6xx(screen)) return 320;
 312                 if (is_a5xx(screen)) return 310;
 313                 if (is_ir3(screen))  return 300;
 314                 return 120;
 315
 316         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 317                 if (is_a6xx(screen)) return 64;
 318                 if (is_a5xx(screen)) return 4;
 319                 return 0;
 320
 321         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 322                 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
 323                         return 4;
 324                 return 0;
 325
 326         /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 327         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 328                 return 0;
 329
 330         case PIPE_CAP_FBFETCH:
 331                 if (fd_device_version(screen->dev) >= FD_VERSION_GMEM_BASE &&
 332                                 is_a6xx(screen))
 333                         return 1;
 334                 return 0;
 335         case PIPE_CAP_SAMPLE_SHADING:
 336                 if (is_a6xx(screen)) return 1;
 337                 return 0;
 338
 339         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 340                 return screen->priority_mask;
 341
 342         case PIPE_CAP_DRAW_INDIRECT:
 343                 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
 344                         return 1;
 345                 return 0;
 346
 347         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 348                 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
 349                         return 1;
 350                 return 0;
 351
 352         case PIPE_CAP_LOAD_CONSTBUF:
 353                 /* name is confusing, but this turns on std430 packing */
 354                 if (is_ir3(screen))
 355                         return 1;
 356                 return 0;
 357
 358         case PIPE_CAP_NIR_IMAGES_AS_DEREF:
 359                 return 0;
 360
 361         case PIPE_CAP_MAX_VIEWPORTS:
 362                 return 1;
 363
 364         case PIPE_CAP_MAX_VARYINGS:
 365                 return 16;
 366
 367         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 368                 /* We don't really have a limit on this, it all goes into the main
 369                  * memory buffer. Needs to be at least 120 / 4 (minimum requirement
 370                  * for GL_MAX_TESS_PATCH_COMPONENTS).
 371                  */
 372                 return 128;
 373
 374         case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 375                 return 64 * 1024 * 1024;
 376
 377         case PIPE_CAP_SHAREABLE_SHADERS:
 378         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 379         /* manage the variants for these ourself, to avoid breaking precompile: */
 380         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 381         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 382                 if (is_ir3(screen))
 383                         return 1;
 384                 return 0;
 385
 386         /* Geometry shaders.. */
 387         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 388                 return 512;
 389         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 390                 return 2048;
 391         case PIPE_CAP_MAX_GS_INVOCATIONS:
 392                 return 32;
 393
 394         /* Stream output. */
 395         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 396                 if (is_ir3(screen))
 397                         return PIPE_MAX_SO_BUFFERS;
 398                 return 0;
 399         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 400         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 401         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 402         case PIPE_CAP_TGSI_TEXCOORD:
 403                 if (is_ir3(screen))
 404                         return 1;
 405                 return 0;
 406         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 407                 return 1;
 408         case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
 409                 return is_a2xx(screen);
 410         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 411         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 412                 if (is_ir3(screen))
 413                         return 16 * 4;   /* should only be shader out limit? */
 414                 return 0;
 415
 416         /* Texturing. */
 417         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 418                 if (is_a6xx(screen) || is_a5xx(screen) || is_a4xx(screen))
 419                         return 16384;
 420                 else
 421                         return 8192;
 422         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 423                 if (is_a6xx(screen) || is_a5xx(screen) || is_a4xx(screen))
 424                         return 15;
 425                 else
 426                         return 14;
 427         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 428                 return 11;
 429
 430         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 431                 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 256 : 0;
 432
 433         /* Render targets. */
 434         case PIPE_CAP_MAX_RENDER_TARGETS:
 435                 return screen->max_rts;
 436         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 437                 return is_a3xx(screen) ? 1 : 0;
 438
 439         /* Queries. */
 440         case PIPE_CAP_OCCLUSION_QUERY:
 441                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 442         case PIPE_CAP_QUERY_TIMESTAMP:
 443         case PIPE_CAP_QUERY_TIME_ELAPSED:
 444                 /* only a4xx, requires new enough kernel so we know max_freq: */
 445                 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen));
 446
 447         case PIPE_CAP_VENDOR_ID:
 448                 return 0x5143;
 449         case PIPE_CAP_DEVICE_ID:
 450                 return 0xFFFFFFFF;
 451         case PIPE_CAP_ACCELERATED:
 452                 return 1;
 453         case PIPE_CAP_VIDEO_MEMORY:
 454                 DBG("FINISHME: The value returned is incorrect\n");
 455                 return 10;
 456         case PIPE_CAP_UMA:
 457                 return 1;
 458         case PIPE_CAP_MEMOBJ:
 459                 return fd_device_version(screen->dev) >= FD_VERSION_MEMORY_FD;
 460         case PIPE_CAP_NATIVE_FENCE_FD:
 461                 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
 462         case PIPE_CAP_FENCE_SIGNAL:
 463                 return screen->has_syncobj;
 464         default:
 465                 return u_pipe_screen_get_param_defaults(pscreen, param);
 466         }
 467 }
 468
 469 static float
 470 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 471 {
 472         switch (param) {
 473         case PIPE_CAPF_MAX_LINE_WIDTH:
 474         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 475                 /* NOTE: actual value is 127.0f, but this is working around a deqp
 476                  * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
 477                  * uses too small of a render target size, and gets confused when
 478                  * the lines start going offscreen.
 479                  *
 480                  * See: https://code.google.com/p/android/issues/detail?id=206513
 481                  */
 482                 if (fd_mesa_debug & FD_DBG_DEQP)
 483                         return 48.0f;
 484                 return 127.0f;
 485         case PIPE_CAPF_MAX_POINT_WIDTH:
 486         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 487                 return 4092.0f;
 488         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 489                 return 16.0f;
 490         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 491                 return 15.0f;
 492         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 493         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 494         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 495                 return 0.0f;
 496         }
 497         debug_printf("unknown paramf %d\n", param);
 498         return 0;
 499 }
 500
 501 static int
 502 fd_screen_get_shader_param(struct pipe_screen *pscreen,
 503                 enum pipe_shader_type shader,
 504                 enum pipe_shader_cap param)
 505 {
 506         struct fd_screen *screen = fd_screen(pscreen);
 507
 508         switch(shader)
 509         {
 510         case PIPE_SHADER_FRAGMENT:
 511         case PIPE_SHADER_VERTEX:
 512                 break;
 513         case PIPE_SHADER_TESS_CTRL:
 514         case PIPE_SHADER_TESS_EVAL:
 515         case PIPE_SHADER_GEOMETRY:
 516                 if (is_a6xx(screen))
 517                         break;
 518                 return 0;
 519         case PIPE_SHADER_COMPUTE:
 520                 if (has_compute(screen))
 521                         break;
 522                 return 0;
 523         default:
 524                 DBG("unknown shader type %d", shader);
 525                 return 0;
 526         }
 527
 528         /* this is probably not totally correct.. but it's a start: */
 529         switch (param) {
 530         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 531         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 532         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 533         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 534                 return 16384;
 535         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 536                 return 8; /* XXX */
 537         case PIPE_SHADER_CAP_MAX_INPUTS:
 538         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 539                 return 16;
 540         case PIPE_SHADER_CAP_MAX_TEMPS:
 541                 return 64; /* Max native temporaries. */
 542         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 543                 /* NOTE: seems to be limit for a3xx is actually 512 but
 544                  * split between VS and FS.  Use lower limit of 256 to
 545                  * avoid getting into impossible situations:
 546                  */
 547                 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 548         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 549                 return is_ir3(screen) ? 16 : 1;
 550         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 551                 return 1;
 552         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 553         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 554                 /* Technically this should be the same as for TEMP/CONST, since
 555                  * everything is just normal registers.  This is just temporary
 556                  * hack until load_input/store_output handle arrays in a similar
 557                  * way as load_var/store_var..
 558                  *
 559                  * For tessellation stages, inputs are loaded using ldlw or ldg, both
 560                  * of which support indirection.
 561                  */
 562                 return shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL;
 563         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 564         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 565                 /* a2xx compiler doesn't handle indirect: */
 566                 return is_ir3(screen) ? 1 : 0;
 567         case PIPE_SHADER_CAP_SUBROUTINES:
 568         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 569         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 570         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 571         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 572         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 573         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 574         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 575         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 576         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 577                 return 0;
 578         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 579                 return 1;
 580         case PIPE_SHADER_CAP_INTEGERS:
 581                 return is_ir3(screen) ? 1 : 0;
 582         case PIPE_SHADER_CAP_INT64_ATOMICS:
 583         case PIPE_SHADER_CAP_FP16_DERIVATIVES:
 584         case PIPE_SHADER_CAP_INT16:
 585         case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
 586                 return 0;
 587         case PIPE_SHADER_CAP_FP16:
 588                 return ((is_a5xx(screen) || is_a6xx(screen)) &&
 589                                 (shader == PIPE_SHADER_COMPUTE ||
 590                                         shader == PIPE_SHADER_FRAGMENT) &&
 591                                 !(fd_mesa_debug & FD_DBG_NOFP16));
 592         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 593         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 594                 return 16;
 595         case PIPE_SHADER_CAP_PREFERRED_IR:
 596                 return PIPE_SHADER_IR_NIR;
 597         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 598                 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
 599         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 600                 return 32;
 601         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 602         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 603                 if (is_a5xx(screen) || is_a6xx(screen)) {
 604                         /* a5xx (and a4xx for that matter) has one state-block
 605                          * for compute-shader SSBO's and another that is shared
 606                          * by VS/HS/DS/GS/FS..  so to simplify things for now
 607                          * just advertise SSBOs for FS and CS.  We could possibly
 608                          * do what blob does, and partition the space for
 609                          * VS/HS/DS/GS/FS.  The blob advertises:
 610                          *
 611                          *   GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
 612                          *   GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
 613                          *   GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
 614                          *   GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
 615                          *   GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
 616                          *   GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
 617                          *   GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
 618                          *
 619                          * I think that way we could avoid having to patch shaders
 620                          * for actual SSBO indexes by using a static partitioning.
 621                          *
 622                          * Note same state block is used for images and buffers,
 623                          * but images also need texture state for read access
 624                          * (isam/isam.3d)
 625                          */
 626                         switch(shader)
 627                         {
 628                         case PIPE_SHADER_FRAGMENT:
 629                         case PIPE_SHADER_COMPUTE:
 630                                 return 24;
 631                         default:
 632                                 return 0;
 633                         }
 634                 }
 635                 return 0;
 636         }
 637         debug_printf("unknown shader param %d\n", param);
 638         return 0;
 639 }
 640
 641 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
 642  * into per-generation backend?
 643  */
 644 static int
 645 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 646                 enum pipe_compute_cap param, void *ret)
 647 {
 648         struct fd_screen *screen = fd_screen(pscreen);
 649         const char * const ir = "ir3";
 650
 651         if (!has_compute(screen))
 652                 return 0;
 653
 654 #define RET(x) do {                  \
 655    if (ret)                          \
 656       memcpy(ret, x, sizeof(x));     \
 657    return sizeof(x);                 \
 658 } while (0)
 659
 660         switch (param) {
 661         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 662 // don't expose 64b pointer support yet, until ir3 supports 64b
 663 // math, otherwise spir64 target is used and we get 64b pointer
 664 // calculations that we can't do yet
 665 //              if (is_a5xx(screen))
 666 //                      RET((uint32_t []){ 64 });
 667                 RET((uint32_t []){ 32 });
 668
 669         case PIPE_COMPUTE_CAP_IR_TARGET:
 670                 if (ret)
 671                         sprintf(ret, "%s", ir);
 672                 return strlen(ir) * sizeof(char);
 673
 674         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 675                 RET((uint64_t []) { 3 });
 676
 677         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 678                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 679
 680         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 681                 RET(((uint64_t []) { 1024, 1024, 64 }));
 682
 683         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 684                 RET((uint64_t []) { 1024 });
 685
 686         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 687                 RET((uint64_t []) { screen->ram_size });
 688
 689         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 690                 RET((uint64_t []) { 32768 });
 691
 692         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 693         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 694                 RET((uint64_t []) { 4096 });
 695
 696         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 697                 RET((uint64_t []) { screen->ram_size });
 698
 699         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 700                 RET((uint32_t []) { screen->max_freq / 1000000 });
 701
 702         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 703                 RET((uint32_t []) { 9999 });  // TODO
 704
 705         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 706                 RET((uint32_t []) { 1 });
 707
 708         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 709                 RET((uint32_t []) { 32 });  // TODO
 710
 711         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 712                 RET((uint64_t []) { 1024 }); // TODO
 713         }
 714
 715         return 0;
 716 }
 717
 718 static const void *
 719 fd_get_compiler_options(struct pipe_screen *pscreen,
 720                 enum pipe_shader_ir ir, unsigned shader)
 721 {
 722         struct fd_screen *screen = fd_screen(pscreen);
 723
 724         if (is_ir3(screen))
 725                 return ir3_get_compiler_options(screen->compiler);
 726
 727         return ir2_get_compiler_options();
 728 }
 729
 730 static struct disk_cache *
 731 fd_get_disk_shader_cache(struct pipe_screen *pscreen)
 732 {
 733         struct fd_screen *screen = fd_screen(pscreen);
 734
 735         if (is_ir3(screen)) {
 736                 struct ir3_compiler *compiler = screen->compiler;
 737                 return compiler->disk_cache;
 738         }
 739
 740         return NULL;
 741 }
 742
 743 bool
 744 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 745                 struct fd_bo *bo,
 746                 struct renderonly_scanout *scanout,
 747                 unsigned stride,
 748                 struct winsys_handle *whandle)
 749 {
 750         whandle->stride = stride;
 751
 752         if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 753                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 754         } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
 755                 if (renderonly_get_handle(scanout, whandle))
 756                         return true;
 757                 whandle->handle = fd_bo_handle(bo);
 758                 return true;
 759         } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 760                 whandle->handle = fd_bo_dmabuf(bo);
 761                 return true;
 762         } else {
 763                 return false;
 764         }
 765 }
 766
 767 static void
 768 fd_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
 769                 enum pipe_format format,
 770                 int max, uint64_t *modifiers,
 771                 unsigned int *external_only,
 772                 int *count)
 773 {
 774         struct fd_screen *screen = fd_screen(pscreen);
 775         int i, num = 0;
 776
 777         max = MIN2(max, screen->num_supported_modifiers);
 778
 779         if (!max) {
 780                 max = screen->num_supported_modifiers;
 781                 external_only = NULL;
 782                 modifiers = NULL;
 783         }
 784
 785         for (i = 0; i < max; i++) {
 786                 if (modifiers)
 787                         modifiers[num] = screen->supported_modifiers[i];
 788
 789                 if (external_only)
 790                         external_only[num] = 0;
 791
 792                 num++;
 793         }
 794
 795         *count = num;
 796 }
 797
 798 struct fd_bo *
 799 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 800                 struct winsys_handle *whandle)
 801 {
 802         struct fd_screen *screen = fd_screen(pscreen);
 803         struct fd_bo *bo;
 804
 805         if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 806                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 807         } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
 808                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 809         } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 810                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 811         } else {
 812                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 813                 return NULL;
 814         }
 815
 816         if (!bo) {
 817                 DBG("ref name 0x%08x failed", whandle->handle);
 818                 return NULL;
 819         }
 820
 821         return bo;
 822 }
 823
 824 static void _fd_fence_ref(struct pipe_screen *pscreen,
 825                 struct pipe_fence_handle **ptr,
 826                 struct pipe_fence_handle *pfence)
 827 {
 828         fd_fence_ref(ptr, pfence);
 829 }
 830
 831 static void
 832 fd_screen_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 833 {
 834         struct fd_screen *screen = fd_screen(pscreen);
 835
 836         fd_get_device_uuid(uuid, screen->gpu_id);
 837 }
 838
 839 static void
 840 fd_screen_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 841 {
 842         fd_get_driver_uuid(uuid);
 843 }
 844
 845 struct pipe_screen *
 846 fd_screen_create(struct fd_device *dev, struct renderonly *ro)
 847 {
 848         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 849         struct pipe_screen *pscreen;
 850         uint64_t val;
 851
 852         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 853
 854         if (fd_mesa_debug & FD_DBG_NOBIN)
 855                 fd_binning_enabled = false;
 856
 857         if (!screen)
 858                 return NULL;
 859
 860         pscreen = &screen->base;
 861
 862         screen->dev = dev;
 863         screen->refcnt = 1;
 864
 865         if (ro) {
 866                 screen->ro = renderonly_dup(ro);
 867                 if (!screen->ro) {
 868                         DBG("could not create renderonly object");
 869                         goto fail;
 870                 }
 871         }
 872
 873         // maybe this should be in context?
 874         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 875         if (!screen->pipe) {
 876                 DBG("could not create 3d pipe");
 877                 goto fail;
 878         }
 879
 880         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 881                 DBG("could not get GMEM size");
 882                 goto fail;
 883         }
 884         screen->gmemsize_bytes = env_var_as_unsigned("FD_MESA_GMEM", val);
 885
 886         if (fd_device_version(dev) >= FD_VERSION_GMEM_BASE) {
 887                 fd_pipe_get_param(screen->pipe, FD_GMEM_BASE, &screen->gmem_base);
 888         }
 889
 890         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 891                 DBG("could not get device-id");
 892                 goto fail;
 893         }
 894         screen->device_id = val;
 895
 896         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 897                 DBG("could not get gpu freq");
 898                 /* this limits what performance related queries are
 899                  * supported but is not fatal
 900                  */
 901                 screen->max_freq = 0;
 902         } else {
 903                 screen->max_freq = val;
 904                 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
 905                         screen->has_timestamp = true;
 906         }
 907
 908         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 909                 DBG("could not get gpu-id");
 910                 goto fail;
 911         }
 912         screen->gpu_id = val;
 913
 914         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 915                 DBG("could not get chip-id");
 916                 /* older kernels may not have this property: */
 917                 unsigned core  = screen->gpu_id / 100;
 918                 unsigned major = (screen->gpu_id % 100) / 10;
 919                 unsigned minor = screen->gpu_id % 10;
 920                 unsigned patch = 0;  /* assume the worst */
 921                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 922                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 923         }
 924         screen->chip_id = val;
 925
 926         if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) {
 927                 DBG("could not get # of rings");
 928                 screen->priority_mask = 0;
 929         } else {
 930                 /* # of rings equates to number of unique priority values: */
 931                 screen->priority_mask = (1 << val) - 1;
 932         }
 933
 934         if (fd_device_version(dev) >= FD_VERSION_ROBUSTNESS)
 935                 screen->has_robustness = true;
 936
 937         screen->has_syncobj = fd_has_syncobj(screen->dev);
 938
 939         struct sysinfo si;
 940         sysinfo(&si);
 941         screen->ram_size = si.totalram;
 942
 943         DBG("Pipe Info:");
 944         DBG(" GPU-id:          %d", screen->gpu_id);
 945         DBG(" Chip-id:         0x%08x", screen->chip_id);
 946         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 947
 948         /* explicitly checking for GPU revisions that are known to work.  This
 949          * may be overly conservative for a3xx, where spoofing the gpu_id with
 950          * the blob driver seems to generate identical cmdstream dumps.  But
 951          * on a2xx, there seem to be small differences between the GPU revs
 952          * so it is probably better to actually test first on real hardware
 953          * before enabling:
 954          *
 955          * If you have a different adreno version, feel free to add it to one
 956          * of the cases below and see what happens.  And if it works, please
 957          * send a patch ;-)
 958          */
 959         switch (screen->gpu_id) {
 960         case 200:
 961         case 201:
 962         case 205:
 963         case 220:
 964                 fd2_screen_init(pscreen);
 965                 break;
 966         case 305:
 967         case 307:
 968         case 320:
 969         case 330:
 970                 fd3_screen_init(pscreen);
 971                 break;
 972         case 405:
 973         case 420:
 974         case 430:
 975                 fd4_screen_init(pscreen);
 976                 break;
 977         case 510:
 978         case 530:
 979         case 540:
 980                 fd5_screen_init(pscreen);
 981                 break;
 982         case 618:
 983         case 630:
 984         case 640:
 985         case 650:
 986                 fd6_screen_init(pscreen);
 987                 break;
 988         default:
 989                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 990                 goto fail;
 991         }
 992
 993         if (screen->gpu_id >= 600) {
 994                 screen->gmem_alignw = 16;
 995                 screen->gmem_alignh = 4;
 996                 screen->tile_alignw = is_a650(screen) ? 96 : 32;
 997                 screen->tile_alignh = 32;
 998                 screen->num_vsc_pipes = 32;
 999         } else if (screen->gpu_id >= 500) {
1000                 screen->gmem_alignw = screen->tile_alignw = 64;
1001                 screen->gmem_alignh = screen->tile_alignh = 32;
1002                 screen->num_vsc_pipes = 16;
1003         } else {
1004                 screen->gmem_alignw = screen->tile_alignw = 32;
1005                 screen->gmem_alignh = screen->tile_alignh = 32;
1006                 screen->num_vsc_pipes = 8;
1007         }
1008
1009         if (fd_mesa_debug & FD_DBG_PERFC) {
1010                 screen->perfcntr_groups = fd_perfcntrs(screen->gpu_id,
1011                                 &screen->num_perfcntr_groups);
1012         }
1013
1014         /* NOTE: don't enable if we have too old of a kernel to support
1015          * growable cmdstream buffers, since memory requirement for cmdstream
1016          * buffers would be too much otherwise.
1017          */
1018         if (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS)
1019                 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
1020
1021         if (BATCH_DEBUG)
1022                 screen->live_batches = _mesa_pointer_set_create(NULL);
1023
1024         fd_bc_init(&screen->batch_cache);
1025
1026         list_inithead(&screen->context_list);
1027
1028         (void) simple_mtx_init(&screen->lock, mtx_plain);
1029
1030         pscreen->destroy = fd_screen_destroy;
1031         pscreen->get_param = fd_screen_get_param;
1032         pscreen->get_paramf = fd_screen_get_paramf;
1033         pscreen->get_shader_param = fd_screen_get_shader_param;
1034         pscreen->get_compute_param = fd_get_compute_param;
1035         pscreen->get_compiler_options = fd_get_compiler_options;
1036         pscreen->get_disk_shader_cache = fd_get_disk_shader_cache;
1037
1038         fd_resource_screen_init(pscreen);
1039         fd_query_screen_init(pscreen);
1040         fd_gmem_screen_init(pscreen);
1041
1042         pscreen->get_name = fd_screen_get_name;
1043         pscreen->get_vendor = fd_screen_get_vendor;
1044         pscreen->get_device_vendor = fd_screen_get_device_vendor;
1045
1046         pscreen->get_timestamp = fd_screen_get_timestamp;
1047
1048         pscreen->fence_reference = _fd_fence_ref;
1049         pscreen->fence_finish = fd_fence_finish;
1050         pscreen->fence_get_fd = fd_fence_get_fd;
1051
1052         pscreen->query_dmabuf_modifiers = fd_screen_query_dmabuf_modifiers;
1053
1054         pscreen->get_device_uuid = fd_screen_get_device_uuid;
1055         pscreen->get_driver_uuid = fd_screen_get_driver_uuid;
1056
1057         slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
1058
1059         return pscreen;
1060
1061 fail:
1062         fd_screen_destroy(pscreen);
1063         return NULL;
1064 }