src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "util/os_time.h"
  42
  43 #include <errno.h>
  44 #include <stdio.h>
  45 #include <stdlib.h>
  46 #include <sys/sysinfo.h>
  47
  48 #include "freedreno_screen.h"
  49 #include "freedreno_resource.h"
  50 #include "freedreno_fence.h"
  51 #include "freedreno_query.h"
  52 #include "freedreno_util.h"
  53
  54 #include "a2xx/fd2_screen.h"
  55 #include "a3xx/fd3_screen.h"
  56 #include "a4xx/fd4_screen.h"
  57 #include "a5xx/fd5_screen.h"
  58
  59 #include "ir3/ir3_nir.h"
  60
  61 /* XXX this should go away */
  62 #include "state_tracker/drm_driver.h"
  63
  64 static const struct debug_named_value debug_options[] = {
  65                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  66                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  67                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  68                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  69                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  70                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  71                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  72                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  73                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  74                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  75                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  76                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  77                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  78                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  79                 {"inorder",   FD_DBG_INORDER,"Disable reordering for draws/blits"},
  80                 {"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
  81                 {"nogrow",    FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
  82                 {"lrz",       FD_DBG_LRZ,    "Enable experimental LRZ support (a5xx+)"},
  83                 {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
  84                 {"noblit",    FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
  85                 {"hiprio",    FD_DBG_HIPRIO, "Force high-priority context"},
  86                 {"ttile",     FD_DBG_TTILE,  "Enable texture tiling (a5xx)"},
  87                 DEBUG_NAMED_VALUE_END
  88 };
  89
  90 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  91
  92 int fd_mesa_debug = 0;
  93 bool fd_binning_enabled = true;
  94 static bool glsl120 = false;
  95
  96 static const struct debug_named_value shader_debug_options[] = {
  97                 {"vs", FD_DBG_SHADER_VS, "Print shader disasm for vertex shaders"},
  98                 {"fs", FD_DBG_SHADER_FS, "Print shader disasm for fragment shaders"},
  99                 {"cs", FD_DBG_SHADER_CS, "Print shader disasm for compute shaders"},
 100                 DEBUG_NAMED_VALUE_END
 101 };
 102
 103 DEBUG_GET_ONCE_FLAGS_OPTION(fd_shader_debug, "FD_SHADER_DEBUG", shader_debug_options, 0)
 104
 105 enum fd_shader_debug fd_shader_debug = 0;
 106
 107 static const char *
 108 fd_screen_get_name(struct pipe_screen *pscreen)
 109 {
 110         static char buffer[128];
 111         util_snprintf(buffer, sizeof(buffer), "FD%03d",
 112                         fd_screen(pscreen)->device_id);
 113         return buffer;
 114 }
 115
 116 static const char *
 117 fd_screen_get_vendor(struct pipe_screen *pscreen)
 118 {
 119         return "freedreno";
 120 }
 121
 122 static const char *
 123 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 124 {
 125         return "Qualcomm";
 126 }
 127
 128
 129 static uint64_t
 130 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 131 {
 132         struct fd_screen *screen = fd_screen(pscreen);
 133
 134         if (screen->has_timestamp) {
 135                 uint64_t n;
 136                 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
 137                 debug_assert(screen->max_freq > 0);
 138                 return n * 1000000000 / screen->max_freq;
 139         } else {
 140                 int64_t cpu_time = os_time_get() * 1000;
 141                 return cpu_time + screen->cpu_gpu_time_delta;
 142         }
 143
 144 }
 145
 146 static void
 147 fd_screen_destroy(struct pipe_screen *pscreen)
 148 {
 149         struct fd_screen *screen = fd_screen(pscreen);
 150
 151         if (screen->pipe)
 152                 fd_pipe_del(screen->pipe);
 153
 154         if (screen->dev)
 155                 fd_device_del(screen->dev);
 156
 157         fd_bc_fini(&screen->batch_cache);
 158
 159         slab_destroy_parent(&screen->transfer_pool);
 160
 161         mtx_destroy(&screen->lock);
 162
 163         ralloc_free(screen->compiler);
 164
 165         free(screen->perfcntr_queries);
 166         free(screen);
 167 }
 168
 169 /*
 170 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 171 tables for things that differ if the delta is not too much..
 172  */
 173 static int
 174 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 175 {
 176         struct fd_screen *screen = fd_screen(pscreen);
 177
 178         /* this is probably not totally correct.. but it's a start: */
 179         switch (param) {
 180         /* Supported features (boolean caps). */
 181         case PIPE_CAP_NPOT_TEXTURES:
 182         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 183         case PIPE_CAP_ANISOTROPIC_FILTER:
 184         case PIPE_CAP_POINT_SPRITE:
 185         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 186         case PIPE_CAP_TEXTURE_SWIZZLE:
 187         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 188         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 189         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 190         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 191         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 192         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 193         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 194         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 195         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 196         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 197         case PIPE_CAP_STRING_MARKER:
 198         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 199         case PIPE_CAP_TEXTURE_BARRIER:
 200         case PIPE_CAP_INVALIDATE_BUFFER:
 201                 return 1;
 202
 203         case PIPE_CAP_VERTEXID_NOBASE:
 204                 return is_a3xx(screen) || is_a4xx(screen);
 205
 206         case PIPE_CAP_COMPUTE:
 207                 return has_compute(screen);
 208
 209         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 210         case PIPE_CAP_TGSI_TEXCOORD:
 211         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 212         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 213         case PIPE_CAP_QUERY_MEMORY_INFO:
 214         case PIPE_CAP_PCI_GROUP:
 215         case PIPE_CAP_PCI_BUS:
 216         case PIPE_CAP_PCI_DEVICE:
 217         case PIPE_CAP_PCI_FUNCTION:
 218                 return 0;
 219
 220         case PIPE_CAP_SM3:
 221         case PIPE_CAP_PRIMITIVE_RESTART:
 222         case PIPE_CAP_TGSI_INSTANCEID:
 223         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 224         case PIPE_CAP_INDEP_BLEND_ENABLE:
 225         case PIPE_CAP_INDEP_BLEND_FUNC:
 226         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 227         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 228         case PIPE_CAP_CONDITIONAL_RENDER:
 229         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 230         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 231         case PIPE_CAP_CLIP_HALFZ:
 232                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
 233
 234         case PIPE_CAP_FAKE_SW_MSAA:
 235                 return !fd_screen_get_param(pscreen, PIPE_CAP_TEXTURE_MULTISAMPLE);
 236
 237         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 238                 return is_a5xx(screen);
 239
 240         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 241                 return is_a3xx(screen) || is_a4xx(screen);
 242
 243         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 244                 return is_a5xx(screen);
 245
 246         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 247                 return 0;
 248         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 249                 if (is_a3xx(screen)) return 16;
 250                 if (is_a4xx(screen)) return 32;
 251                 if (is_a5xx(screen)) return 32;
 252                 return 0;
 253         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 254                 /* We could possibly emulate more by pretending 2d/rect textures and
 255                  * splitting high bits of index into 2nd dimension..
 256                  */
 257                 if (is_a3xx(screen)) return 8192;
 258                 if (is_a4xx(screen)) return 16384;
 259                 if (is_a5xx(screen)) return 16384;
 260                 return 0;
 261
 262         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 263         case PIPE_CAP_CUBE_MAP_ARRAY:
 264         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 265         case PIPE_CAP_TEXTURE_QUERY_LOD:
 266                 return is_a4xx(screen) || is_a5xx(screen);
 267
 268         case PIPE_CAP_START_INSTANCE:
 269                 /* Note that a5xx can do this, it just can't (at least with
 270                  * current firmware) do draw_indirect with base_instance.
 271                  * Since draw_indirect is needed sooner (gles31 and gl40 vs
 272                  * gl42), hide base_instance on a5xx.  :-/
 273                  */
 274                 return is_a4xx(screen);
 275
 276         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 277                 return 64;
 278
 279         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 280         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 281                 if (glsl120)
 282                         return 120;
 283                 return is_ir3(screen) ? 140 : 120;
 284
 285         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 286                 if (is_a5xx(screen))
 287                         return 4;
 288                 return 0;
 289
 290         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 291                 if (is_a4xx(screen) || is_a5xx(screen))
 292                         return 4;
 293                 return 0;
 294
 295         /* Unsupported features. */
 296         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 297         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 298         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 299         case PIPE_CAP_USER_VERTEX_BUFFERS:
 300         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 301         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 302         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 303         case PIPE_CAP_TEXTURE_GATHER_SM5:
 304         case PIPE_CAP_SAMPLE_SHADING:
 305         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 306         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 307         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 308         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 309         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 310         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 311         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 312         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 313         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 314         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 315         case PIPE_CAP_TGSI_TXQS:
 316         /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 317         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 318         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 319         case PIPE_CAP_CLEAR_TEXTURE:
 320         case PIPE_CAP_DRAW_PARAMETERS:
 321         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 322         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 323         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 324         case PIPE_CAP_GENERATE_MIPMAP:
 325         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 326         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 327         case PIPE_CAP_CULL_DISTANCE:
 328         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 329         case PIPE_CAP_TGSI_VOTE:
 330         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 331         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 332         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 333         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 334         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 335         case PIPE_CAP_TGSI_FS_FBFETCH:
 336         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 337         case PIPE_CAP_DOUBLES:
 338         case PIPE_CAP_INT64:
 339         case PIPE_CAP_INT64_DIVMOD:
 340         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 341         case PIPE_CAP_TGSI_CLOCK:
 342         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 343         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 344         case PIPE_CAP_TGSI_BALLOT:
 345         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 346         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 347         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 348         case PIPE_CAP_POST_DEPTH_COVERAGE:
 349         case PIPE_CAP_BINDLESS_TEXTURE:
 350         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 351         case PIPE_CAP_QUERY_SO_OVERFLOW:
 352         case PIPE_CAP_MEMOBJ:
 353         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 354         case PIPE_CAP_TILE_RASTER_ORDER:
 355         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 356         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 357         case PIPE_CAP_FENCE_SIGNAL:
 358         case PIPE_CAP_CONSTBUF0_FLAGS:
 359         case PIPE_CAP_PACKED_UNIFORMS:
 360         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 361         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 362         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 363         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 364         case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 365         case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 366         case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 367                 return 0;
 368
 369         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 370                 return screen->priority_mask;
 371
 372         case PIPE_CAP_DRAW_INDIRECT:
 373                 if (is_a4xx(screen) || is_a5xx(screen))
 374                         return 1;
 375                 return 0;
 376
 377         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 378                 if (is_a4xx(screen) || is_a5xx(screen))
 379                         return 1;
 380                 return 0;
 381
 382         case PIPE_CAP_LOAD_CONSTBUF:
 383                 /* name is confusing, but this turns on std430 packing */
 384                 if (is_ir3(screen))
 385                         return 1;
 386                 return 0;
 387
 388         case PIPE_CAP_MAX_VIEWPORTS:
 389                 return 1;
 390
 391         case PIPE_CAP_SHAREABLE_SHADERS:
 392         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 393         /* manage the variants for these ourself, to avoid breaking precompile: */
 394         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 395         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 396                 if (is_ir3(screen))
 397                         return 1;
 398                 return 0;
 399
 400         /* Stream output. */
 401         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 402                 if (is_ir3(screen))
 403                         return PIPE_MAX_SO_BUFFERS;
 404                 return 0;
 405         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 406         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 407                 if (is_ir3(screen))
 408                         return 1;
 409                 return 0;
 410         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 411         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 412                 if (is_ir3(screen))
 413                         return 16 * 4;   /* should only be shader out limit? */
 414                 return 0;
 415
 416         /* Geometry shader output, unsupported. */
 417         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 418         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 419         case PIPE_CAP_MAX_VERTEX_STREAMS:
 420                 return 0;
 421
 422         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 423                 return 2048;
 424
 425         /* Texturing. */
 426         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 427         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 428                 return MAX_MIP_LEVELS;
 429         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 430                 return 11;
 431
 432         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 433                 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 256 : 0;
 434
 435         /* Render targets. */
 436         case PIPE_CAP_MAX_RENDER_TARGETS:
 437                 return screen->max_rts;
 438         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 439                 return is_a3xx(screen) ? 1 : 0;
 440
 441         /* Queries. */
 442         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 443                 return 0;
 444         case PIPE_CAP_OCCLUSION_QUERY:
 445                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
 446         case PIPE_CAP_QUERY_TIMESTAMP:
 447         case PIPE_CAP_QUERY_TIME_ELAPSED:
 448                 /* only a4xx, requires new enough kernel so we know max_freq: */
 449                 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen));
 450
 451         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 452         case PIPE_CAP_MIN_TEXEL_OFFSET:
 453                 return -8;
 454
 455         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 456         case PIPE_CAP_MAX_TEXEL_OFFSET:
 457                 return 7;
 458
 459         case PIPE_CAP_ENDIANNESS:
 460                 return PIPE_ENDIAN_LITTLE;
 461
 462         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 463                 return 64;
 464
 465         case PIPE_CAP_VENDOR_ID:
 466                 return 0x5143;
 467         case PIPE_CAP_DEVICE_ID:
 468                 return 0xFFFFFFFF;
 469         case PIPE_CAP_ACCELERATED:
 470                 return 1;
 471         case PIPE_CAP_VIDEO_MEMORY:
 472                 DBG("FINISHME: The value returned is incorrect\n");
 473                 return 10;
 474         case PIPE_CAP_UMA:
 475                 return 1;
 476         case PIPE_CAP_NATIVE_FENCE_FD:
 477                 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
 478         }
 479         debug_printf("unknown param %d\n", param);
 480         return 0;
 481 }
 482
 483 static float
 484 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 485 {
 486         switch (param) {
 487         case PIPE_CAPF_MAX_LINE_WIDTH:
 488         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 489                 /* NOTE: actual value is 127.0f, but this is working around a deqp
 490                  * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
 491                  * uses too small of a render target size, and gets confused when
 492                  * the lines start going offscreen.
 493                  *
 494                  * See: https://code.google.com/p/android/issues/detail?id=206513
 495                  */
 496                 if (fd_mesa_debug & FD_DBG_DEQP)
 497                         return 48.0f;
 498                 return 127.0f;
 499         case PIPE_CAPF_MAX_POINT_WIDTH:
 500         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 501                 return 4092.0f;
 502         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 503                 return 16.0f;
 504         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 505                 return 15.0f;
 506         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 507         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 508         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 509                 return 0.0f;
 510         }
 511         debug_printf("unknown paramf %d\n", param);
 512         return 0;
 513 }
 514
 515 static int
 516 fd_screen_get_shader_param(struct pipe_screen *pscreen,
 517                 enum pipe_shader_type shader,
 518                 enum pipe_shader_cap param)
 519 {
 520         struct fd_screen *screen = fd_screen(pscreen);
 521
 522         switch(shader)
 523         {
 524         case PIPE_SHADER_FRAGMENT:
 525         case PIPE_SHADER_VERTEX:
 526                 break;
 527         case PIPE_SHADER_COMPUTE:
 528                 if (has_compute(screen))
 529                         break;
 530                 return 0;
 531         case PIPE_SHADER_GEOMETRY:
 532                 /* maye we could emulate.. */
 533                 return 0;
 534         default:
 535                 DBG("unknown shader type %d", shader);
 536                 return 0;
 537         }
 538
 539         /* this is probably not totally correct.. but it's a start: */
 540         switch (param) {
 541         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 542         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 543         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 544         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 545                 return 16384;
 546         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 547                 return 8; /* XXX */
 548         case PIPE_SHADER_CAP_MAX_INPUTS:
 549         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 550                 return 16;
 551         case PIPE_SHADER_CAP_MAX_TEMPS:
 552                 return 64; /* Max native temporaries. */
 553         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 554                 /* NOTE: seems to be limit for a3xx is actually 512 but
 555                  * split between VS and FS.  Use lower limit of 256 to
 556                  * avoid getting into impossible situations:
 557                  */
 558                 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 559         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 560                 return is_ir3(screen) ? 16 : 1;
 561         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 562                 return 1;
 563         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 564         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 565                 /* Technically this should be the same as for TEMP/CONST, since
 566                  * everything is just normal registers.  This is just temporary
 567                  * hack until load_input/store_output handle arrays in a similar
 568                  * way as load_var/store_var..
 569                  */
 570                 return 0;
 571         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 572         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 573                 /* a2xx compiler doesn't handle indirect: */
 574                 return is_ir3(screen) ? 1 : 0;
 575         case PIPE_SHADER_CAP_SUBROUTINES:
 576         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 577         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 578         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 579         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 580         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 581         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 582                 return 0;
 583         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 584                 return 1;
 585         case PIPE_SHADER_CAP_INTEGERS:
 586                 if (glsl120)
 587                         return 0;
 588                 return is_ir3(screen) ? 1 : 0;
 589         case PIPE_SHADER_CAP_INT64_ATOMICS:
 590                 return 0;
 591         case PIPE_SHADER_CAP_FP16:
 592                 return 0;
 593         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 594         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 595                 return 16;
 596         case PIPE_SHADER_CAP_PREFERRED_IR:
 597                 if (is_ir3(screen))
 598                         return PIPE_SHADER_IR_NIR;
 599                 return PIPE_SHADER_IR_TGSI;
 600         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 601                 if (is_ir3(screen)) {
 602                         return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
 603                 } else {
 604                         return (1 << PIPE_SHADER_IR_TGSI);
 605                 }
 606                 return 0;
 607         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 608                 return 32;
 609         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 610         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 611         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 612         case PIPE_SHADER_CAP_SCALAR_ISA:
 613                 return 1;
 614         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 615         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 616                 if (is_a5xx(screen)) {
 617                         /* a5xx (and a4xx for that matter) has one state-block
 618                          * for compute-shader SSBO's and another that is shared
 619                          * by VS/HS/DS/GS/FS..  so to simplify things for now
 620                          * just advertise SSBOs for FS and CS.  We could possibly
 621                          * do what blob does, and partition the space for
 622                          * VS/HS/DS/GS/FS.  The blob advertises:
 623                          *
 624                          *   GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
 625                          *   GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
 626                          *   GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
 627                          *   GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
 628                          *   GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
 629                          *   GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
 630                          *   GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
 631                          *
 632                          * I think that way we could avoid having to patch shaders
 633                          * for actual SSBO indexes by using a static partitioning.
 634                          *
 635                          * Note same state block is used for images and buffers,
 636                          * but images also need texture state for read access
 637                          * (isam/isam.3d)
 638                          */
 639                         switch(shader)
 640                         {
 641                         case PIPE_SHADER_FRAGMENT:
 642                         case PIPE_SHADER_COMPUTE:
 643                                 return 24;
 644                         default:
 645                                 return 0;
 646                         }
 647                 }
 648                 return 0;
 649         }
 650         debug_printf("unknown shader param %d\n", param);
 651         return 0;
 652 }
 653
 654 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
 655  * into per-generation backend?
 656  */
 657 static int
 658 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 659                 enum pipe_compute_cap param, void *ret)
 660 {
 661         struct fd_screen *screen = fd_screen(pscreen);
 662         const char * const ir = "ir3";
 663
 664         if (!has_compute(screen))
 665                 return 0;
 666
 667 #define RET(x) do {                  \
 668    if (ret)                          \
 669       memcpy(ret, x, sizeof(x));     \
 670    return sizeof(x);                 \
 671 } while (0)
 672
 673         switch (param) {
 674         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 675 // don't expose 64b pointer support yet, until ir3 supports 64b
 676 // math, otherwise spir64 target is used and we get 64b pointer
 677 // calculations that we can't do yet
 678 //              if (is_a5xx(screen))
 679 //                      RET((uint32_t []){ 64 });
 680                 RET((uint32_t []){ 32 });
 681
 682         case PIPE_COMPUTE_CAP_IR_TARGET:
 683                 if (ret)
 684                         sprintf(ret, ir);
 685                 return strlen(ir) * sizeof(char);
 686
 687         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 688                 RET((uint64_t []) { 3 });
 689
 690         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 691                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 692
 693         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 694                 RET(((uint64_t []) { 1024, 1024, 64 }));
 695
 696         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 697                 RET((uint64_t []) { 1024 });
 698
 699         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 700                 RET((uint64_t []) { screen->ram_size });
 701
 702         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 703                 RET((uint64_t []) { 32768 });
 704
 705         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 706         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 707                 RET((uint64_t []) { 4096 });
 708
 709         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 710                 RET((uint64_t []) { screen->ram_size });
 711
 712         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 713                 RET((uint32_t []) { screen->max_freq / 1000000 });
 714
 715         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 716                 RET((uint32_t []) { 9999 });  // TODO
 717
 718         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 719                 RET((uint32_t []) { 1 });
 720
 721         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 722                 RET((uint32_t []) { 32 });  // TODO
 723
 724         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 725                 RET((uint64_t []) { 1024 }); // TODO
 726         }
 727
 728         return 0;
 729 }
 730
 731 static const void *
 732 fd_get_compiler_options(struct pipe_screen *pscreen,
 733                 enum pipe_shader_ir ir, unsigned shader)
 734 {
 735         struct fd_screen *screen = fd_screen(pscreen);
 736
 737         if (is_ir3(screen))
 738                 return ir3_get_compiler_options(screen->compiler);
 739
 740         return NULL;
 741 }
 742
 743 boolean
 744 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 745                 struct fd_bo *bo,
 746                 unsigned stride,
 747                 struct winsys_handle *whandle)
 748 {
 749         whandle->stride = stride;
 750
 751         if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 752                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 753         } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
 754                 whandle->handle = fd_bo_handle(bo);
 755                 return TRUE;
 756         } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 757                 whandle->handle = fd_bo_dmabuf(bo);
 758                 return TRUE;
 759         } else {
 760                 return FALSE;
 761         }
 762 }
 763
 764 struct fd_bo *
 765 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 766                 struct winsys_handle *whandle)
 767 {
 768         struct fd_screen *screen = fd_screen(pscreen);
 769         struct fd_bo *bo;
 770
 771         if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 772                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 773         } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
 774                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 775         } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 776                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 777         } else {
 778                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 779                 return NULL;
 780         }
 781
 782         if (!bo) {
 783                 DBG("ref name 0x%08x failed", whandle->handle);
 784                 return NULL;
 785         }
 786
 787         return bo;
 788 }
 789
 790 struct pipe_screen *
 791 fd_screen_create(struct fd_device *dev)
 792 {
 793         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 794         struct pipe_screen *pscreen;
 795         uint64_t val;
 796
 797         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 798         fd_shader_debug = debug_get_option_fd_shader_debug();
 799
 800         if (fd_mesa_debug & FD_DBG_NOBIN)
 801                 fd_binning_enabled = false;
 802
 803         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 804
 805         if (!screen)
 806                 return NULL;
 807
 808         pscreen = &screen->base;
 809
 810         screen->dev = dev;
 811         screen->refcnt = 1;
 812
 813         // maybe this should be in context?
 814         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 815         if (!screen->pipe) {
 816                 DBG("could not create 3d pipe");
 817                 goto fail;
 818         }
 819
 820         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 821                 DBG("could not get GMEM size");
 822                 goto fail;
 823         }
 824         screen->gmemsize_bytes = val;
 825
 826         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 827                 DBG("could not get device-id");
 828                 goto fail;
 829         }
 830         screen->device_id = val;
 831
 832         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 833                 DBG("could not get gpu freq");
 834                 /* this limits what performance related queries are
 835                  * supported but is not fatal
 836                  */
 837                 screen->max_freq = 0;
 838         } else {
 839                 screen->max_freq = val;
 840                 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
 841                         screen->has_timestamp = true;
 842         }
 843
 844         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 845                 DBG("could not get gpu-id");
 846                 goto fail;
 847         }
 848         screen->gpu_id = val;
 849
 850         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 851                 DBG("could not get chip-id");
 852                 /* older kernels may not have this property: */
 853                 unsigned core  = screen->gpu_id / 100;
 854                 unsigned major = (screen->gpu_id % 100) / 10;
 855                 unsigned minor = screen->gpu_id % 10;
 856                 unsigned patch = 0;  /* assume the worst */
 857                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 858                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 859         }
 860         screen->chip_id = val;
 861
 862         if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) {
 863                 DBG("could not get # of rings");
 864                 screen->priority_mask = 0;
 865         } else {
 866                 /* # of rings equates to number of unique priority values: */
 867                 screen->priority_mask = (1 << val) - 1;
 868         }
 869
 870         struct sysinfo si;
 871         sysinfo(&si);
 872         screen->ram_size = si.totalram;
 873
 874         DBG("Pipe Info:");
 875         DBG(" GPU-id:          %d", screen->gpu_id);
 876         DBG(" Chip-id:         0x%08x", screen->chip_id);
 877         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 878
 879         /* explicitly checking for GPU revisions that are known to work.  This
 880          * may be overly conservative for a3xx, where spoofing the gpu_id with
 881          * the blob driver seems to generate identical cmdstream dumps.  But
 882          * on a2xx, there seem to be small differences between the GPU revs
 883          * so it is probably better to actually test first on real hardware
 884          * before enabling:
 885          *
 886          * If you have a different adreno version, feel free to add it to one
 887          * of the cases below and see what happens.  And if it works, please
 888          * send a patch ;-)
 889          */
 890         switch (screen->gpu_id) {
 891         case 205:
 892         case 220:
 893                 fd2_screen_init(pscreen);
 894                 break;
 895         case 305:
 896         case 307:
 897         case 320:
 898         case 330:
 899                 fd3_screen_init(pscreen);
 900                 break;
 901         case 420:
 902         case 430:
 903                 fd4_screen_init(pscreen);
 904                 break;
 905         case 530:
 906                 fd5_screen_init(pscreen);
 907                 break;
 908         default:
 909                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 910                 goto fail;
 911         }
 912
 913         if (screen->gpu_id >= 500) {
 914                 screen->gmem_alignw = 64;
 915                 screen->gmem_alignh = 32;
 916                 screen->num_vsc_pipes = 16;
 917         } else {
 918                 screen->gmem_alignw = 32;
 919                 screen->gmem_alignh = 32;
 920                 screen->num_vsc_pipes = 8;
 921         }
 922
 923         /* NOTE: don't enable reordering on a2xx, since completely untested.
 924          * Also, don't enable if we have too old of a kernel to support
 925          * growable cmdstream buffers, since memory requirement for cmdstream
 926          * buffers would be too much otherwise.
 927          */
 928         if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
 929                 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
 930
 931         fd_bc_init(&screen->batch_cache);
 932
 933         (void) mtx_init(&screen->lock, mtx_plain);
 934
 935         pscreen->destroy = fd_screen_destroy;
 936         pscreen->get_param = fd_screen_get_param;
 937         pscreen->get_paramf = fd_screen_get_paramf;
 938         pscreen->get_shader_param = fd_screen_get_shader_param;
 939         pscreen->get_compute_param = fd_get_compute_param;
 940         pscreen->get_compiler_options = fd_get_compiler_options;
 941
 942         fd_resource_screen_init(pscreen);
 943         fd_query_screen_init(pscreen);
 944
 945         pscreen->get_name = fd_screen_get_name;
 946         pscreen->get_vendor = fd_screen_get_vendor;
 947         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 948
 949         pscreen->get_timestamp = fd_screen_get_timestamp;
 950
 951         pscreen->fence_reference = fd_fence_ref;
 952         pscreen->fence_finish = fd_fence_finish;
 953         pscreen->fence_get_fd = fd_fence_get_fd;
 954
 955         slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
 956
 957         return pscreen;
 958
 959 fail:
 960         fd_screen_destroy(pscreen);
 961         return NULL;
 962 }