1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
36 #include "freedreno_util.h"
38 #include "ir3_compiler.h"
39 #include "ir3_shader.h"
42 #include "instr-a3xx.h"
47 struct ir3_compiler
*compiler
;
52 struct ir3_shader_variant
*so
;
54 struct ir3_block
*block
; /* the current block */
55 struct ir3_block
*in_block
; /* block created for shader inputs */
57 nir_function_impl
*impl
;
59 /* For fragment shaders, from the hw perspective the only
60 * actual input is r0.xy position register passed to bary.f.
61 * But TGSI doesn't know that, it still declares things as
62 * IN[] registers. So we do all the input tracking normally
63 * and fix things up after compile_instructions()
65 * NOTE that frag_pos is the hardware position (possibly it
66 * is actually an index or tag or some such.. it is *not*
67 * values that can be directly used for gl_FragCoord..)
69 struct ir3_instruction
*frag_pos
, *frag_face
, *frag_coord
[4];
71 /* For vertex shaders, keep track of the system values sources */
72 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
74 /* mapping from nir_register to defining instruction: */
75 struct hash_table
*def_ht
;
79 /* a common pattern for indirect addressing is to request the
80 * same address register multiple times. To avoid generating
81 * duplicate instruction sequences (which our backend does not
82 * try to clean up, since that should be done as the NIR stage)
83 * we cache the address value generated for a given src value:
85 struct hash_table
*addr_ht
;
87 /* maps nir_block to ir3_block, mostly for the purposes of
88 * figuring out the blocks successors
90 struct hash_table
*block_ht
;
92 /* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
93 * so we need to use ldlv.u32 to load the varying directly:
97 /* on a3xx, we need to add one to # of array levels:
101 /* on a3xx, we need to scale up integer coords for isaml based
104 bool unminify_coords
;
106 /* on a4xx, for array textures we need to add 0.5 to the array
109 bool array_index_add_half
;
111 /* on a4xx, bitmask of samplers which need astc+srgb workaround: */
114 unsigned max_texture_index
;
116 /* set if we encounter something we can't handle yet, so we
117 * can bail cleanly and fallback to TGSI compiler f/e
123 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
124 static struct ir3_block
* get_block(struct ir3_compile
*ctx
, nir_block
*nblock
);
127 static struct ir3_compile
*
128 compile_init(struct ir3_compiler
*compiler
,
129 struct ir3_shader_variant
*so
)
131 struct ir3_compile
*ctx
= rzalloc(NULL
, struct ir3_compile
);
133 if (compiler
->gpu_id
>= 400) {
134 /* need special handling for "flat" */
135 ctx
->flat_bypass
= true;
136 ctx
->levels_add_one
= false;
137 ctx
->unminify_coords
= false;
138 ctx
->array_index_add_half
= true;
140 if (so
->type
== SHADER_VERTEX
)
141 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
142 else if (so
->type
== SHADER_FRAGMENT
)
143 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
146 /* no special handling for "flat" */
147 ctx
->flat_bypass
= false;
148 ctx
->levels_add_one
= true;
149 ctx
->unminify_coords
= true;
150 ctx
->array_index_add_half
= false;
153 ctx
->compiler
= compiler
;
156 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
157 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
158 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
159 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
161 /* TODO: maybe generate some sort of bitmask of what key
162 * lowers vs what shader has (ie. no need to lower
163 * texture clamp lowering if no texture sample instrs)..
164 * although should be done further up the stack to avoid
165 * creating duplicate variants..
168 if (ir3_key_lowers_nir(&so
->key
)) {
169 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
170 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
172 /* fast-path for shader key that lowers nothing in NIR: */
173 ctx
->s
= so
->shader
->nir
;
176 if (fd_mesa_debug
& FD_DBG_DISASM
) {
177 DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
178 so
->shader
->id
, so
->id
, so
->type
,
179 so
->key
.binning_pass
, so
->key
.color_two_side
,
180 so
->key
.half_precision
);
181 nir_print_shader(ctx
->s
, stdout
);
184 so
->first_driver_param
= so
->first_immediate
= ctx
->s
->num_uniforms
;
186 /* Layout of constant registers:
188 * num_uniform * vec4 - user consts
189 * 4 * vec4 - UBO addresses
190 * if (vertex shader) {
191 * N * vec4 - driver params (IR3_DP_*)
192 * 1 * vec4 - stream-out addresses
195 * TODO this could be made more dynamic, to at least skip sections
196 * that we don't need..
199 /* reserve 4 (vec4) slots for ubo base addresses: */
200 so
->first_immediate
+= 4;
202 if (so
->type
== SHADER_VERTEX
) {
203 /* driver params (see ir3_driver_param): */
204 so
->first_immediate
+= IR3_DP_COUNT
/4; /* convert to vec4 */
205 /* one (vec4) slot for stream-output base addresses: */
206 so
->first_immediate
++;
213 compile_error(struct ir3_compile
*ctx
, const char *format
, ...)
216 va_start(ap
, format
);
217 _debug_vprintf(format
, ap
);
219 nir_print_shader(ctx
->s
, stdout
);
224 #define compile_assert(ctx, cond) do { \
225 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
229 compile_free(struct ir3_compile
*ctx
)
235 declare_var(struct ir3_compile
*ctx
, nir_variable
*var
)
237 unsigned length
= glsl_get_length(var
->type
) * 4; /* always vec4, at least with ttn */
238 struct ir3_array
*arr
= ralloc(ctx
, struct ir3_array
);
239 arr
->id
= ++ctx
->num_arrays
;
240 arr
->length
= length
;
242 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
245 static struct ir3_array
*
246 get_var(struct ir3_compile
*ctx
, nir_variable
*var
)
248 list_for_each_entry (struct ir3_array
, arr
, &ctx
->ir
->array_list
, node
) {
252 compile_error(ctx
, "bogus var: %s\n", var
->name
);
256 /* allocate a n element value array (to be populated by caller) and
259 static struct ir3_instruction
**
260 __get_dst(struct ir3_compile
*ctx
, void *key
, unsigned n
)
262 struct ir3_instruction
**value
=
263 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
264 _mesa_hash_table_insert(ctx
->def_ht
, key
, value
);
268 static struct ir3_instruction
**
269 get_dst(struct ir3_compile
*ctx
, nir_dest
*dst
, unsigned n
)
271 compile_assert(ctx
, dst
->is_ssa
);
273 return __get_dst(ctx
, &dst
->ssa
, n
);
275 return __get_dst(ctx
, dst
->reg
.reg
, n
);
279 static struct ir3_instruction
**
280 get_dst_ssa(struct ir3_compile
*ctx
, nir_ssa_def
*dst
, unsigned n
)
282 return __get_dst(ctx
, dst
, n
);
285 static struct ir3_instruction
**
286 get_src(struct ir3_compile
*ctx
, nir_src
*src
)
288 struct hash_entry
*entry
;
289 compile_assert(ctx
, src
->is_ssa
);
291 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
293 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->reg
.reg
);
295 compile_assert(ctx
, entry
);
299 static struct ir3_instruction
*
300 create_immed(struct ir3_block
*block
, uint32_t val
)
302 struct ir3_instruction
*mov
;
304 mov
= ir3_instr_create(block
, OPC_MOV
);
305 mov
->cat1
.src_type
= TYPE_U32
;
306 mov
->cat1
.dst_type
= TYPE_U32
;
307 ir3_reg_create(mov
, 0, 0);
308 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
313 static struct ir3_instruction
*
314 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
)
316 struct ir3_instruction
*instr
, *immed
;
318 /* TODO in at least some cases, the backend could probably be
319 * made clever enough to propagate IR3_REG_HALF..
321 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
322 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
324 immed
= create_immed(block
, 2);
325 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
327 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
328 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
329 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
331 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
332 instr
->regs
[0]->num
= regid(REG_A0
, 0);
333 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
334 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
339 /* caches addr values to avoid generating multiple cov/shl/mova
340 * sequences for each use of a given NIR level src as address
342 static struct ir3_instruction
*
343 get_addr(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
345 struct ir3_instruction
*addr
;
348 ctx
->addr_ht
= _mesa_hash_table_create(ctx
,
349 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
351 struct hash_entry
*entry
;
352 entry
= _mesa_hash_table_search(ctx
->addr_ht
, src
);
357 addr
= create_addr(ctx
->block
, src
);
358 _mesa_hash_table_insert(ctx
->addr_ht
, src
, addr
);
363 static struct ir3_instruction
*
364 get_predicate(struct ir3_compile
*ctx
, struct ir3_instruction
*src
)
366 struct ir3_block
*b
= ctx
->block
;
367 struct ir3_instruction
*cond
;
369 /* NOTE: only cmps.*.* can write p0.x: */
370 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
371 cond
->cat2
.condition
= IR3_COND_NE
;
373 /* condition always goes in predicate register: */
374 cond
->regs
[0]->num
= regid(REG_P0
, 0);
379 static struct ir3_instruction
*
380 create_uniform(struct ir3_compile
*ctx
, unsigned n
)
382 struct ir3_instruction
*mov
;
384 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
385 /* TODO get types right? */
386 mov
->cat1
.src_type
= TYPE_F32
;
387 mov
->cat1
.dst_type
= TYPE_F32
;
388 ir3_reg_create(mov
, 0, 0);
389 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
394 static struct ir3_instruction
*
395 create_uniform_indirect(struct ir3_compile
*ctx
, int n
,
396 struct ir3_instruction
*address
)
398 struct ir3_instruction
*mov
;
400 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
401 mov
->cat1
.src_type
= TYPE_U32
;
402 mov
->cat1
.dst_type
= TYPE_U32
;
403 ir3_reg_create(mov
, 0, 0);
404 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
406 ir3_instr_set_address(mov
, address
);
411 static struct ir3_instruction
*
412 create_collect(struct ir3_block
*block
, struct ir3_instruction
**arr
,
415 struct ir3_instruction
*collect
;
420 collect
= ir3_instr_create2(block
, OPC_META_FI
, 1 + arrsz
);
421 ir3_reg_create(collect
, 0, 0); /* dst */
422 for (unsigned i
= 0; i
< arrsz
; i
++)
423 ir3_reg_create(collect
, 0, IR3_REG_SSA
)->instr
= arr
[i
];
428 static struct ir3_instruction
*
429 create_indirect_load(struct ir3_compile
*ctx
, unsigned arrsz
, int n
,
430 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
432 struct ir3_block
*block
= ctx
->block
;
433 struct ir3_instruction
*mov
;
434 struct ir3_register
*src
;
436 mov
= ir3_instr_create(block
, OPC_MOV
);
437 mov
->cat1
.src_type
= TYPE_U32
;
438 mov
->cat1
.dst_type
= TYPE_U32
;
439 ir3_reg_create(mov
, 0, 0);
440 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
441 src
->instr
= collect
;
443 src
->array
.offset
= n
;
445 ir3_instr_set_address(mov
, address
);
450 /* relative (indirect) if address!=NULL */
451 static struct ir3_instruction
*
452 create_var_load(struct ir3_compile
*ctx
, struct ir3_array
*arr
, int n
,
453 struct ir3_instruction
*address
)
455 struct ir3_block
*block
= ctx
->block
;
456 struct ir3_instruction
*mov
;
457 struct ir3_register
*src
;
459 mov
= ir3_instr_create(block
, OPC_MOV
);
460 mov
->cat1
.src_type
= TYPE_U32
;
461 mov
->cat1
.dst_type
= TYPE_U32
;
462 ir3_reg_create(mov
, 0, 0);
463 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
464 COND(address
, IR3_REG_RELATIV
));
465 src
->instr
= arr
->last_write
;
466 src
->size
= arr
->length
;
467 src
->array
.id
= arr
->id
;
468 src
->array
.offset
= n
;
471 ir3_instr_set_address(mov
, address
);
473 arr
->last_access
= mov
;
478 /* relative (indirect) if address!=NULL */
479 static struct ir3_instruction
*
480 create_var_store(struct ir3_compile
*ctx
, struct ir3_array
*arr
, int n
,
481 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
483 struct ir3_block
*block
= ctx
->block
;
484 struct ir3_instruction
*mov
;
485 struct ir3_register
*dst
;
487 mov
= ir3_instr_create(block
, OPC_MOV
);
488 mov
->cat1
.src_type
= TYPE_U32
;
489 mov
->cat1
.dst_type
= TYPE_U32
;
490 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
491 COND(address
, IR3_REG_RELATIV
));
492 dst
->instr
= arr
->last_access
;
493 dst
->size
= arr
->length
;
494 dst
->array
.id
= arr
->id
;
495 dst
->array
.offset
= n
;
496 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
498 ir3_instr_set_address(mov
, address
);
500 arr
->last_write
= arr
->last_access
= mov
;
505 static struct ir3_instruction
*
506 create_input(struct ir3_block
*block
, unsigned n
)
508 struct ir3_instruction
*in
;
510 in
= ir3_instr_create(block
, OPC_META_INPUT
);
511 in
->inout
.block
= block
;
512 ir3_reg_create(in
, n
, 0);
517 static struct ir3_instruction
*
518 create_frag_input(struct ir3_compile
*ctx
, bool use_ldlv
)
520 struct ir3_block
*block
= ctx
->block
;
521 struct ir3_instruction
*instr
;
522 /* actual inloc is assigned and fixed up later: */
523 struct ir3_instruction
*inloc
= create_immed(block
, 0);
526 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
527 instr
->cat6
.type
= TYPE_U32
;
528 instr
->cat6
.iim_val
= 1;
530 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_pos
, 0);
531 instr
->regs
[2]->wrmask
= 0x3;
537 static struct ir3_instruction
*
538 create_frag_coord(struct ir3_compile
*ctx
, unsigned comp
)
540 struct ir3_block
*block
= ctx
->block
;
541 struct ir3_instruction
*instr
;
543 compile_assert(ctx
, !ctx
->frag_coord
[comp
]);
545 ctx
->frag_coord
[comp
] = create_input(ctx
->block
, 0);
550 /* for frag_coord, we get unsigned values.. we need
551 * to subtract (integer) 8 and divide by 16 (right-
552 * shift by 4) then convert to float:
556 * mov.u32f32 dst, tmp
559 instr
= ir3_SUB_S(block
, ctx
->frag_coord
[comp
], 0,
560 create_immed(block
, 8), 0);
561 instr
= ir3_SHR_B(block
, instr
, 0,
562 create_immed(block
, 4), 0);
563 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
569 /* seems that we can use these as-is: */
570 return ctx
->frag_coord
[comp
];
574 /* NOTE: this creates the "TGSI" style fragface (ie. input slot
575 * VARYING_SLOT_FACE). For NIR style nir_intrinsic_load_front_face
576 * we can just use the value from hw directly (since it is boolean)
578 static struct ir3_instruction
*
579 create_frag_face(struct ir3_compile
*ctx
, unsigned comp
)
581 struct ir3_block
*block
= ctx
->block
;
582 struct ir3_instruction
*instr
;
586 compile_assert(ctx
, !ctx
->frag_face
);
588 ctx
->frag_face
= create_input(block
, 0);
589 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
591 /* for faceness, we always get -1 or 0 (int).. but TGSI expects
592 * positive vs negative float.. and piglit further seems to
593 * expect -1.0 or 1.0:
595 * mul.s tmp, hr0.x, 2
597 * mov.s32f32, dst, tmp
600 instr
= ir3_MUL_S(block
, ctx
->frag_face
, 0,
601 create_immed(block
, 2), 0);
602 instr
= ir3_ADD_S(block
, instr
, 0,
603 create_immed(block
, 1), 0);
604 instr
= ir3_COV(block
, instr
, TYPE_S32
, TYPE_F32
);
609 return create_immed(block
, fui(0.0));
612 return create_immed(block
, fui(1.0));
616 static struct ir3_instruction
*
617 create_driver_param(struct ir3_compile
*ctx
, enum ir3_driver_param dp
)
619 /* first four vec4 sysval's reserved for UBOs: */
620 /* NOTE: dp is in scalar, but there can be >4 dp components: */
621 unsigned n
= ctx
->so
->first_driver_param
+ IR3_DRIVER_PARAM_OFF
;
622 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
623 return create_uniform(ctx
, r
);
626 /* helper for instructions that produce multiple consecutive scalar
627 * outputs which need to have a split/fanout meta instruction inserted
630 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
631 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
633 struct ir3_instruction
*prev
= NULL
;
634 for (int i
= 0, j
= 0; i
< n
; i
++) {
635 struct ir3_instruction
*split
= ir3_instr_create(block
, OPC_META_FO
);
636 ir3_reg_create(split
, 0, IR3_REG_SSA
);
637 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
638 split
->fo
.off
= i
+ base
;
641 split
->cp
.left
= prev
;
642 split
->cp
.left_cnt
++;
643 prev
->cp
.right
= split
;
644 prev
->cp
.right_cnt
++;
648 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
654 * Adreno uses uint rather than having dedicated bool type,
655 * which (potentially) requires some conversion, in particular
656 * when using output of an bool instr to int input, or visa
660 * -------+---------+-------+-
664 * To convert from an adreno bool (uint) to nir, use:
666 * absneg.s dst, (neg)src
668 * To convert back in the other direction:
670 * absneg.s dst, (abs)arc
672 * The CP step can clean up the absneg.s that cancel each other
673 * out, and with a slight bit of extra cleverness (to recognize
674 * the instructions which produce either a 0 or 1) can eliminate
675 * the absneg.s's completely when an instruction that wants
676 * 0/1 consumes the result. For example, when a nir 'bcsel'
677 * consumes the result of 'feq'. So we should be able to get by
678 * without a boolean resolve step, and without incuring any
679 * extra penalty in instruction count.
682 /* NIR bool -> native (adreno): */
683 static struct ir3_instruction
*
684 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
686 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
689 /* native (adreno) -> NIR bool: */
690 static struct ir3_instruction
*
691 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
693 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
697 * alu/sfu instructions:
701 emit_alu(struct ir3_compile
*ctx
, nir_alu_instr
*alu
)
703 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
704 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
705 struct ir3_block
*b
= ctx
->block
;
707 dst
= get_dst(ctx
, &alu
->dest
.dest
, MAX2(info
->output_size
, 1));
709 /* Vectors are special in that they have non-scalarized writemasks,
710 * and just take the first swizzle channel for each argument in
711 * order into each writemask channel.
713 if ((alu
->op
== nir_op_vec2
) ||
714 (alu
->op
== nir_op_vec3
) ||
715 (alu
->op
== nir_op_vec4
)) {
717 for (int i
= 0; i
< info
->num_inputs
; i
++) {
718 nir_alu_src
*asrc
= &alu
->src
[i
];
720 compile_assert(ctx
, !asrc
->abs
);
721 compile_assert(ctx
, !asrc
->negate
);
723 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
725 src
[i
] = create_immed(ctx
->block
, 0);
726 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
732 /* General case: We can just grab the one used channel per src. */
733 for (int i
= 0; i
< info
->num_inputs
; i
++) {
734 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
735 nir_alu_src
*asrc
= &alu
->src
[i
];
737 compile_assert(ctx
, !asrc
->abs
);
738 compile_assert(ctx
, !asrc
->negate
);
740 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
742 compile_assert(ctx
, src
[i
]);
747 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_S32
);
750 dst
[0] = ir3_COV(b
, src
[0], TYPE_F32
, TYPE_U32
);
753 dst
[0] = ir3_COV(b
, src
[0], TYPE_S32
, TYPE_F32
);
756 dst
[0] = ir3_COV(b
, src
[0], TYPE_U32
, TYPE_F32
);
759 dst
[0] = ir3_MOV(b
, src
[0], TYPE_S32
);
762 dst
[0] = ir3_MOV(b
, src
[0], TYPE_F32
);
765 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
766 dst
[0]->cat2
.condition
= IR3_COND_NE
;
767 dst
[0] = ir3_n2b(b
, dst
[0]);
770 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
773 dst
[0] = ir3_b2n(b
, src
[0]);
776 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
777 dst
[0]->cat2
.condition
= IR3_COND_NE
;
778 dst
[0] = ir3_n2b(b
, dst
[0]);
782 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
785 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
788 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
791 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
794 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
797 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
800 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
803 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
806 dst
[0] = ir3_DSX(b
, src
[0], 0);
807 dst
[0]->cat5
.type
= TYPE_F32
;
810 dst
[0] = ir3_DSY(b
, src
[0], 0);
811 dst
[0]->cat5
.type
= TYPE_F32
;
815 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
816 dst
[0]->cat2
.condition
= IR3_COND_LT
;
817 dst
[0] = ir3_n2b(b
, dst
[0]);
820 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
821 dst
[0]->cat2
.condition
= IR3_COND_GE
;
822 dst
[0] = ir3_n2b(b
, dst
[0]);
825 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
826 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
827 dst
[0] = ir3_n2b(b
, dst
[0]);
830 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
831 dst
[0]->cat2
.condition
= IR3_COND_NE
;
832 dst
[0] = ir3_n2b(b
, dst
[0]);
835 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
838 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
841 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
843 case nir_op_fround_even
:
844 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
847 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
851 dst
[0] = ir3_SIN(b
, src
[0], 0);
854 dst
[0] = ir3_COS(b
, src
[0], 0);
857 dst
[0] = ir3_RSQ(b
, src
[0], 0);
860 dst
[0] = ir3_RCP(b
, src
[0], 0);
863 dst
[0] = ir3_LOG2(b
, src
[0], 0);
866 dst
[0] = ir3_EXP2(b
, src
[0], 0);
869 dst
[0] = ir3_SQRT(b
, src
[0], 0);
873 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
876 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
879 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
882 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
885 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
888 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
891 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
895 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
896 * mull.u tmp0, a, b ; mul low, i.e. al * bl
897 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
898 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
900 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
901 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
902 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
905 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
908 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
911 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
914 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
917 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
920 /* maybe this would be sane to lower in nir.. */
921 struct ir3_instruction
*neg
, *pos
;
923 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
924 neg
->cat2
.condition
= IR3_COND_LT
;
926 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
927 pos
->cat2
.condition
= IR3_COND_GT
;
929 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
934 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
937 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
940 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
943 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
944 dst
[0]->cat2
.condition
= IR3_COND_LT
;
945 dst
[0] = ir3_n2b(b
, dst
[0]);
948 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
949 dst
[0]->cat2
.condition
= IR3_COND_GE
;
950 dst
[0] = ir3_n2b(b
, dst
[0]);
953 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
954 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
955 dst
[0] = ir3_n2b(b
, dst
[0]);
958 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
959 dst
[0]->cat2
.condition
= IR3_COND_NE
;
960 dst
[0] = ir3_n2b(b
, dst
[0]);
963 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
964 dst
[0]->cat2
.condition
= IR3_COND_LT
;
965 dst
[0] = ir3_n2b(b
, dst
[0]);
968 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
969 dst
[0]->cat2
.condition
= IR3_COND_GE
;
970 dst
[0] = ir3_n2b(b
, dst
[0]);
974 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, ir3_b2n(b
, src
[0]), 0, src
[2], 0);
977 case nir_op_bit_count
:
978 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
980 case nir_op_ifind_msb
: {
981 struct ir3_instruction
*cmp
;
982 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
983 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
984 cmp
->cat2
.condition
= IR3_COND_GE
;
985 dst
[0] = ir3_SEL_B32(b
,
986 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
990 case nir_op_ufind_msb
:
991 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
992 dst
[0] = ir3_SEL_B32(b
,
993 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
994 src
[0], 0, dst
[0], 0);
996 case nir_op_find_lsb
:
997 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
998 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1000 case nir_op_bitfield_reverse
:
1001 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1005 compile_error(ctx
, "Unhandled ALU op: %s\n",
1006 nir_op_infos
[alu
->op
].name
);
1011 /* handles direct/indirect UBO reads: */
1013 emit_intrinsic_load_ubo(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1014 struct ir3_instruction
**dst
)
1016 struct ir3_block
*b
= ctx
->block
;
1017 struct ir3_instruction
*addr
, *src0
, *src1
;
1018 nir_const_value
*const_offset
;
1019 /* UBO addresses are the first driver params: */
1020 unsigned ubo
= regid(ctx
->so
->first_driver_param
+ IR3_UBOS_OFF
, 0);
1023 /* First src is ubo index, which could either be an immed or not: */
1024 src0
= get_src(ctx
, &intr
->src
[0])[0];
1025 if (is_same_type_mov(src0
) &&
1026 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1027 addr
= create_uniform(ctx
, ubo
+ src0
->regs
[1]->iim_val
);
1029 addr
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
));
1032 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1034 off
+= const_offset
->u32
[0];
1036 /* For load_ubo_indirect, second src is indirect offset: */
1037 src1
= get_src(ctx
, &intr
->src
[1])[0];
1039 /* and add offset to addr: */
1040 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1043 /* if offset is to large to encode in the ldg, split it out: */
1044 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1045 /* split out the minimal amount to improve the odds that
1046 * cp can fit the immediate in the add.s instruction:
1048 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1049 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1053 for (int i
= 0; i
< intr
->num_components
; i
++) {
1054 struct ir3_instruction
*load
=
1055 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1056 load
->cat6
.type
= TYPE_U32
;
1057 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1062 /* handles array reads: */
1064 emit_intrinsic_load_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
,
1065 struct ir3_instruction
**dst
)
1067 nir_deref_var
*dvar
= intr
->variables
[0];
1068 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1069 struct ir3_array
*arr
= get_var(ctx
, dvar
->var
);
1071 compile_assert(ctx
, dvar
->deref
.child
&&
1072 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1074 switch (darr
->deref_array_type
) {
1075 case nir_deref_array_type_direct
:
1076 /* direct access does not require anything special: */
1077 for (int i
= 0; i
< intr
->num_components
; i
++) {
1078 unsigned n
= darr
->base_offset
* 4 + i
;
1079 compile_assert(ctx
, n
< arr
->length
);
1080 dst
[i
] = create_var_load(ctx
, arr
, n
, NULL
);
1083 case nir_deref_array_type_indirect
: {
1084 /* for indirect, we need to collect all the array elements: */
1085 struct ir3_instruction
*addr
=
1086 get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1087 for (int i
= 0; i
< intr
->num_components
; i
++) {
1088 unsigned n
= darr
->base_offset
* 4 + i
;
1089 compile_assert(ctx
, n
< arr
->length
);
1090 dst
[i
] = create_var_load(ctx
, arr
, n
, addr
);
1095 compile_error(ctx
, "Unhandled load deref type: %u\n",
1096 darr
->deref_array_type
);
1101 /* handles array writes: */
1103 emit_intrinsic_store_var(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1105 nir_deref_var
*dvar
= intr
->variables
[0];
1106 nir_deref_array
*darr
= nir_deref_as_array(dvar
->deref
.child
);
1107 struct ir3_array
*arr
= get_var(ctx
, dvar
->var
);
1108 struct ir3_instruction
*addr
, **src
;
1109 unsigned wrmask
= nir_intrinsic_write_mask(intr
);
1111 compile_assert(ctx
, dvar
->deref
.child
&&
1112 (dvar
->deref
.child
->deref_type
== nir_deref_type_array
));
1114 src
= get_src(ctx
, &intr
->src
[0]);
1116 switch (darr
->deref_array_type
) {
1117 case nir_deref_array_type_direct
:
1120 case nir_deref_array_type_indirect
:
1121 addr
= get_addr(ctx
, get_src(ctx
, &darr
->indirect
)[0]);
1124 compile_error(ctx
, "Unhandled store deref type: %u\n",
1125 darr
->deref_array_type
);
1129 for (int i
= 0; i
< intr
->num_components
; i
++) {
1130 if (!(wrmask
& (1 << i
)))
1132 unsigned n
= darr
->base_offset
* 4 + i
;
1133 compile_assert(ctx
, n
< arr
->length
);
1134 create_var_store(ctx
, arr
, n
, src
[i
], addr
);
1138 static void add_sysval_input(struct ir3_compile
*ctx
, gl_system_value slot
,
1139 struct ir3_instruction
*instr
)
1141 struct ir3_shader_variant
*so
= ctx
->so
;
1142 unsigned r
= regid(so
->inputs_count
, 0);
1143 unsigned n
= so
->inputs_count
++;
1145 so
->inputs
[n
].sysval
= true;
1146 so
->inputs
[n
].slot
= slot
;
1147 so
->inputs
[n
].compmask
= 1;
1148 so
->inputs
[n
].regid
= r
;
1149 so
->inputs
[n
].interpolate
= INTERP_QUALIFIER_FLAT
;
1152 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1153 ctx
->ir
->inputs
[r
] = instr
;
1157 emit_intrinsic(struct ir3_compile
*ctx
, nir_intrinsic_instr
*intr
)
1159 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1160 struct ir3_instruction
**dst
, **src
;
1161 struct ir3_block
*b
= ctx
->block
;
1162 nir_const_value
*const_offset
;
1165 if (info
->has_dest
) {
1166 dst
= get_dst(ctx
, &intr
->dest
, intr
->num_components
);
1171 switch (intr
->intrinsic
) {
1172 case nir_intrinsic_load_uniform
:
1173 idx
= nir_intrinsic_base(intr
);
1174 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1176 idx
+= const_offset
->u32
[0];
1177 for (int i
= 0; i
< intr
->num_components
; i
++) {
1178 unsigned n
= idx
* 4 + i
;
1179 dst
[i
] = create_uniform(ctx
, n
);
1182 src
= get_src(ctx
, &intr
->src
[0]);
1183 for (int i
= 0; i
< intr
->num_components
; i
++) {
1184 int n
= idx
* 4 + i
;
1185 dst
[i
] = create_uniform_indirect(ctx
, n
,
1186 get_addr(ctx
, src
[0]));
1188 /* NOTE: if relative addressing is used, we set
1189 * constlen in the compiler (to worst-case value)
1190 * since we don't know in the assembler what the max
1191 * addr reg value can be:
1193 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
1196 case nir_intrinsic_load_ubo
:
1197 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1199 case nir_intrinsic_load_input
:
1200 idx
= nir_intrinsic_base(intr
);
1201 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1203 idx
+= const_offset
->u32
[0];
1204 for (int i
= 0; i
< intr
->num_components
; i
++) {
1205 unsigned n
= idx
* 4 + i
;
1206 dst
[i
] = ctx
->ir
->inputs
[n
];
1209 src
= get_src(ctx
, &intr
->src
[0]);
1210 struct ir3_instruction
*collect
=
1211 create_collect(b
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1212 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0]);
1213 for (int i
= 0; i
< intr
->num_components
; i
++) {
1214 unsigned n
= idx
* 4 + i
;
1215 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1220 case nir_intrinsic_load_var
:
1221 emit_intrinsic_load_var(ctx
, intr
, dst
);
1223 case nir_intrinsic_store_var
:
1224 emit_intrinsic_store_var(ctx
, intr
);
1226 case nir_intrinsic_store_output
:
1227 idx
= nir_intrinsic_base(intr
);
1228 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1229 compile_assert(ctx
, const_offset
!= NULL
);
1230 idx
+= const_offset
->u32
[0];
1232 src
= get_src(ctx
, &intr
->src
[0]);
1233 for (int i
= 0; i
< intr
->num_components
; i
++) {
1234 unsigned n
= idx
* 4 + i
;
1235 ctx
->ir
->outputs
[n
] = src
[i
];
1238 case nir_intrinsic_load_base_vertex
:
1239 if (!ctx
->basevertex
) {
1240 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1241 add_sysval_input(ctx
, SYSTEM_VALUE_BASE_VERTEX
,
1244 dst
[0] = ctx
->basevertex
;
1246 case nir_intrinsic_load_vertex_id_zero_base
:
1247 if (!ctx
->vertex_id
) {
1248 ctx
->vertex_id
= create_input(b
, 0);
1249 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
,
1252 dst
[0] = ctx
->vertex_id
;
1254 case nir_intrinsic_load_instance_id
:
1255 if (!ctx
->instance_id
) {
1256 ctx
->instance_id
= create_input(b
, 0);
1257 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
1260 dst
[0] = ctx
->instance_id
;
1262 case nir_intrinsic_load_user_clip_plane
:
1263 idx
= nir_intrinsic_ucp_id(intr
);
1264 for (int i
= 0; i
< intr
->num_components
; i
++) {
1265 unsigned n
= idx
* 4 + i
;
1266 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1269 case nir_intrinsic_load_front_face
:
1270 if (!ctx
->frag_face
) {
1271 ctx
->so
->frag_face
= true;
1272 ctx
->frag_face
= create_input(b
, 0);
1273 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
1275 /* for fragface, we always get -1 or 0, but that is inverse
1276 * of what nir expects (where ~0 is true). Unfortunately
1277 * trying to widen from half to full in add.s seems to do a
1278 * non-sign-extending widen (resulting in something that
1279 * gets interpreted as float Inf??)
1281 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
1282 dst
[0] = ir3_ADD_S(b
, dst
[0], 0, create_immed(b
, 1), 0);
1284 case nir_intrinsic_discard_if
:
1285 case nir_intrinsic_discard
: {
1286 struct ir3_instruction
*cond
, *kill
;
1288 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1289 /* conditional discard: */
1290 src
= get_src(ctx
, &intr
->src
[0]);
1291 cond
= ir3_b2n(b
, src
[0]);
1293 /* unconditional discard: */
1294 cond
= create_immed(b
, 1);
1297 /* NOTE: only cmps.*.* can write p0.x: */
1298 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1299 cond
->cat2
.condition
= IR3_COND_NE
;
1301 /* condition always goes in predicate register: */
1302 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1304 kill
= ir3_KILL(b
, cond
, 0);
1305 array_insert(ctx
->ir
->predicates
, kill
);
1307 array_insert(ctx
->ir
->keeps
, kill
);
1308 ctx
->so
->has_kill
= true;
1313 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
1314 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1320 emit_load_const(struct ir3_compile
*ctx
, nir_load_const_instr
*instr
)
1322 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
1323 instr
->def
.num_components
);
1324 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1325 dst
[i
] = create_immed(ctx
->block
, instr
->value
.u32
[i
]);
1329 emit_undef(struct ir3_compile
*ctx
, nir_ssa_undef_instr
*undef
)
1331 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
1332 undef
->def
.num_components
);
1333 /* backend doesn't want undefined instructions, so just plug
1336 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1337 dst
[i
] = create_immed(ctx
->block
, fui(0.0));
1341 * texture fetch/sample instructions:
1345 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1347 unsigned coords
, flags
= 0;
1349 /* note: would use tex->coord_components.. except txs.. also,
1350 * since array index goes after shadow ref, we don't want to
1353 switch (tex
->sampler_dim
) {
1354 case GLSL_SAMPLER_DIM_1D
:
1355 case GLSL_SAMPLER_DIM_BUF
:
1358 case GLSL_SAMPLER_DIM_2D
:
1359 case GLSL_SAMPLER_DIM_RECT
:
1360 case GLSL_SAMPLER_DIM_EXTERNAL
:
1361 case GLSL_SAMPLER_DIM_MS
:
1364 case GLSL_SAMPLER_DIM_3D
:
1365 case GLSL_SAMPLER_DIM_CUBE
:
1367 flags
|= IR3_INSTR_3D
;
1370 unreachable("bad sampler_dim");
1373 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1374 flags
|= IR3_INSTR_S
;
1376 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
1377 flags
|= IR3_INSTR_A
;
1384 emit_tex(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1386 struct ir3_block
*b
= ctx
->block
;
1387 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1388 struct ir3_instruction
**coord
, *lod
, *compare
, *proj
, **off
, **ddx
, **ddy
;
1389 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1390 unsigned i
, coords
, flags
;
1391 unsigned nsrc0
= 0, nsrc1
= 0;
1395 coord
= off
= ddx
= ddy
= NULL
;
1396 lod
= proj
= compare
= NULL
;
1398 /* TODO: might just be one component for gathers? */
1399 dst
= get_dst(ctx
, &tex
->dest
, 4);
1401 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1402 switch (tex
->src
[i
].src_type
) {
1403 case nir_tex_src_coord
:
1404 coord
= get_src(ctx
, &tex
->src
[i
].src
);
1406 case nir_tex_src_bias
:
1407 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1410 case nir_tex_src_lod
:
1411 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1414 case nir_tex_src_comparitor
: /* shadow comparator */
1415 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1417 case nir_tex_src_projector
:
1418 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
1421 case nir_tex_src_offset
:
1422 off
= get_src(ctx
, &tex
->src
[i
].src
);
1425 case nir_tex_src_ddx
:
1426 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
1428 case nir_tex_src_ddy
:
1429 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
1432 compile_error(ctx
, "Unhandled NIR tex src type: %d\n",
1433 tex
->src
[i
].src_type
);
1439 case nir_texop_tex
: opc
= OPC_SAM
; break;
1440 case nir_texop_txb
: opc
= OPC_SAMB
; break;
1441 case nir_texop_txl
: opc
= OPC_SAML
; break;
1442 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
1443 case nir_texop_txf
: opc
= OPC_ISAML
; break;
1444 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
1445 case nir_texop_txf_ms
:
1448 case nir_texop_query_levels
:
1449 case nir_texop_texture_samples
:
1450 case nir_texop_samples_identical
:
1451 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
1455 tex_info(tex
, &flags
, &coords
);
1457 /* scale up integer coords for TXF based on the LOD */
1458 if (ctx
->unminify_coords
&& (opc
== OPC_ISAML
)) {
1460 for (i
= 0; i
< coords
; i
++)
1461 coord
[i
] = ir3_SHL_B(b
, coord
[i
], 0, lod
, 0);
1464 /* the array coord for cube arrays needs 0.5 added to it */
1465 if (ctx
->array_index_add_half
&& tex
->is_array
&& (opc
!= OPC_ISAML
))
1466 coord
[coords
] = ir3_ADD_F(b
, coord
[coords
], 0, create_immed(b
, fui(0.5)), 0);
1469 * lay out the first argument in the proper order:
1470 * - actual coordinates first
1471 * - shadow reference
1474 * - starting at offset 4, dpdx.xy, dpdy.xy
1476 * bias/lod go into the second arg
1479 /* insert tex coords: */
1480 for (i
= 0; i
< coords
; i
++)
1481 src0
[nsrc0
++] = coord
[i
];
1484 /* hw doesn't do 1d, so we treat it as 2d with
1485 * height of 1, and patch up the y coord.
1486 * TODO: y coord should be (int)0 in some cases..
1488 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
1491 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1492 src0
[nsrc0
++] = compare
;
1494 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
1495 src0
[nsrc0
++] = coord
[coords
];
1498 src0
[nsrc0
++] = proj
;
1499 flags
|= IR3_INSTR_P
;
1502 /* pad to 4, then ddx/ddy: */
1503 if (tex
->op
== nir_texop_txd
) {
1505 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1506 for (i
= 0; i
< coords
; i
++)
1507 src0
[nsrc0
++] = ddx
[i
];
1509 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1510 for (i
= 0; i
< coords
; i
++)
1511 src0
[nsrc0
++] = ddy
[i
];
1513 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1517 * second argument (if applicable):
1522 if (has_off
| has_lod
| has_bias
) {
1524 for (i
= 0; i
< coords
; i
++)
1525 src1
[nsrc1
++] = off
[i
];
1527 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
1528 flags
|= IR3_INSTR_O
;
1531 if (has_lod
| has_bias
)
1532 src1
[nsrc1
++] = lod
;
1535 switch (tex
->dest_type
) {
1536 case nir_type_invalid
:
1537 case nir_type_float
:
1548 unreachable("bad dest_type");
1551 if (opc
== OPC_GETLOD
)
1554 unsigned tex_idx
= tex
->texture_index
;
1556 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex_idx
);
1558 struct ir3_instruction
*col0
= create_collect(b
, src0
, nsrc0
);
1559 struct ir3_instruction
*col1
= create_collect(b
, src1
, nsrc1
);
1561 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
, flags
,
1562 tex_idx
, tex_idx
, col0
, col1
);
1564 if ((ctx
->astc_srgb
& (1 << tex_idx
)) && !nir_tex_instr_is_query(tex
)) {
1565 /* only need first 3 components: */
1566 sam
->regs
[0]->wrmask
= 0x7;
1567 split_dest(b
, dst
, sam
, 0, 3);
1569 /* we need to sample the alpha separately with a non-ASTC
1572 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_W
, flags
,
1573 tex_idx
, tex_idx
, col0
, col1
);
1575 array_insert(ctx
->ir
->astc_srgb
, sam
);
1577 /* fixup .w component: */
1578 split_dest(b
, &dst
[3], sam
, 3, 1);
1580 /* normal (non-workaround) case: */
1581 split_dest(b
, dst
, sam
, 0, 4);
1584 /* GETLOD returns results in 4.8 fixed point */
1585 if (opc
== OPC_GETLOD
) {
1586 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
1588 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
1589 for (i
= 0; i
< 2; i
++) {
1590 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
1597 emit_tex_query_levels(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1599 struct ir3_block
*b
= ctx
->block
;
1600 struct ir3_instruction
**dst
, *sam
;
1602 dst
= get_dst(ctx
, &tex
->dest
, 1);
1604 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
1605 tex
->texture_index
, tex
->texture_index
, NULL
, NULL
);
1607 /* even though there is only one component, since it ends
1608 * up in .z rather than .x, we need a split_dest()
1610 split_dest(b
, dst
, sam
, 0, 3);
1612 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1613 * the value in TEX_CONST_0 is zero-based.
1615 if (ctx
->levels_add_one
)
1616 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
1620 emit_tex_txs(struct ir3_compile
*ctx
, nir_tex_instr
*tex
)
1622 struct ir3_block
*b
= ctx
->block
;
1623 struct ir3_instruction
**dst
, *sam
, *lod
;
1624 unsigned flags
, coords
;
1626 tex_info(tex
, &flags
, &coords
);
1628 /* Actually we want the number of dimensions, not coordinates. This
1629 * distinction only matters for cubes.
1631 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
1634 dst
= get_dst(ctx
, &tex
->dest
, 4);
1636 compile_assert(ctx
, tex
->num_srcs
== 1);
1637 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
1639 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
1641 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
1642 tex
->texture_index
, tex
->texture_index
, lod
, NULL
);
1644 split_dest(b
, dst
, sam
, 0, 4);
1646 /* Array size actually ends up in .w rather than .z. This doesn't
1647 * matter for miplevel 0, but for higher mips the value in z is
1648 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1649 * returned, which means that we have to add 1 to it for arrays.
1651 if (tex
->is_array
) {
1652 if (ctx
->levels_add_one
) {
1653 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
1655 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
1661 emit_phi(struct ir3_compile
*ctx
, nir_phi_instr
*nphi
)
1663 struct ir3_instruction
*phi
, **dst
;
1665 /* NOTE: phi's should be lowered to scalar at this point */
1666 compile_assert(ctx
, nphi
->dest
.ssa
.num_components
== 1);
1668 dst
= get_dst(ctx
, &nphi
->dest
, 1);
1670 phi
= ir3_instr_create2(ctx
->block
, OPC_META_PHI
,
1671 1 + exec_list_length(&nphi
->srcs
));
1672 ir3_reg_create(phi
, 0, 0); /* dst */
1673 phi
->phi
.nphi
= nphi
;
1678 /* phi instructions are left partially constructed. We don't resolve
1679 * their srcs until the end of the block, since (eg. loops) one of
1680 * the phi's srcs might be defined after the phi due to back edges in
1684 resolve_phis(struct ir3_compile
*ctx
, struct ir3_block
*block
)
1686 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
1687 nir_phi_instr
*nphi
;
1689 /* phi's only come at start of block: */
1690 if (instr
->opc
!= OPC_META_PHI
)
1693 if (!instr
->phi
.nphi
)
1696 nphi
= instr
->phi
.nphi
;
1697 instr
->phi
.nphi
= NULL
;
1699 foreach_list_typed(nir_phi_src
, nsrc
, node
, &nphi
->srcs
) {
1700 struct ir3_instruction
*src
= get_src(ctx
, &nsrc
->src
)[0];
1702 /* NOTE: src might not be in the same block as it comes from
1703 * according to the phi.. but in the end the backend assumes
1704 * it will be able to assign the same register to each (which
1705 * only works if it is assigned in the src block), so insert
1706 * an extra mov to make sure the phi src is assigned in the
1707 * block it comes from:
1709 src
= ir3_MOV(get_block(ctx
, nsrc
->pred
), src
, TYPE_U32
);
1711 ir3_reg_create(instr
, 0, IR3_REG_SSA
)->instr
= src
;
1717 emit_jump(struct ir3_compile
*ctx
, nir_jump_instr
*jump
)
1719 switch (jump
->type
) {
1720 case nir_jump_break
:
1721 case nir_jump_continue
:
1722 /* I *think* we can simply just ignore this, and use the
1723 * successor block link to figure out where we need to
1724 * jump to for break/continue
1728 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
1734 emit_instr(struct ir3_compile
*ctx
, nir_instr
*instr
)
1736 switch (instr
->type
) {
1737 case nir_instr_type_alu
:
1738 emit_alu(ctx
, nir_instr_as_alu(instr
));
1740 case nir_instr_type_intrinsic
:
1741 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1743 case nir_instr_type_load_const
:
1744 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1746 case nir_instr_type_ssa_undef
:
1747 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
1749 case nir_instr_type_tex
: {
1750 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
1751 /* couple tex instructions get special-cased:
1755 emit_tex_txs(ctx
, tex
);
1757 case nir_texop_query_levels
:
1758 emit_tex_query_levels(ctx
, tex
);
1766 case nir_instr_type_phi
:
1767 emit_phi(ctx
, nir_instr_as_phi(instr
));
1769 case nir_instr_type_jump
:
1770 emit_jump(ctx
, nir_instr_as_jump(instr
));
1772 case nir_instr_type_call
:
1773 case nir_instr_type_parallel_copy
:
1774 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
1779 static struct ir3_block
*
1780 get_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1782 struct ir3_block
*block
;
1783 struct hash_entry
*entry
;
1784 entry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
1788 block
= ir3_block_create(ctx
->ir
);
1789 block
->nblock
= nblock
;
1790 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
1796 emit_block(struct ir3_compile
*ctx
, nir_block
*nblock
)
1798 struct ir3_block
*block
= get_block(ctx
, nblock
);
1800 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
1801 if (nblock
->successors
[i
]) {
1802 block
->successors
[i
] =
1803 get_block(ctx
, nblock
->successors
[i
]);
1808 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
1810 /* re-emit addr register in each block if needed: */
1811 _mesa_hash_table_destroy(ctx
->addr_ht
, NULL
);
1812 ctx
->addr_ht
= NULL
;
1814 nir_foreach_instr(nblock
, instr
) {
1815 emit_instr(ctx
, instr
);
1821 static void emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
);
1824 emit_if(struct ir3_compile
*ctx
, nir_if
*nif
)
1826 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
1828 ctx
->block
->condition
=
1829 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
1831 emit_cf_list(ctx
, &nif
->then_list
);
1832 emit_cf_list(ctx
, &nif
->else_list
);
1836 emit_loop(struct ir3_compile
*ctx
, nir_loop
*nloop
)
1838 emit_cf_list(ctx
, &nloop
->body
);
1842 emit_cf_list(struct ir3_compile
*ctx
, struct exec_list
*list
)
1844 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
1845 switch (node
->type
) {
1846 case nir_cf_node_block
:
1847 emit_block(ctx
, nir_cf_node_as_block(node
));
1849 case nir_cf_node_if
:
1850 emit_if(ctx
, nir_cf_node_as_if(node
));
1852 case nir_cf_node_loop
:
1853 emit_loop(ctx
, nir_cf_node_as_loop(node
));
1855 case nir_cf_node_function
:
1856 compile_error(ctx
, "TODO\n");
1862 /* emit stream-out code. At this point, the current block is the original
1863 * (nir) end block, and nir ensures that all flow control paths terminate
1864 * into the end block. We re-purpose the original end block to generate
1865 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
1866 * block holding stream-out write instructions, followed by the new end
1870 * p0.x = (vtxcnt < maxvtxcnt)
1871 * // succs: blockStreamOut, blockNewEnd
1874 * ... stream-out instructions ...
1875 * // succs: blockNewEnd
1881 emit_stream_out(struct ir3_compile
*ctx
)
1883 struct ir3_shader_variant
*v
= ctx
->so
;
1884 struct ir3
*ir
= ctx
->ir
;
1885 struct pipe_stream_output_info
*strmout
=
1886 &ctx
->so
->shader
->stream_output
;
1887 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
1888 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
1889 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
1891 /* create vtxcnt input in input block at top of shader,
1892 * so that it is seen as live over the entire duration
1895 vtxcnt
= create_input(ctx
->in_block
, 0);
1896 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
1898 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
1900 /* at this point, we are at the original 'end' block,
1901 * re-purpose this block to stream-out condition, then
1902 * append stream-out block and new-end block
1904 orig_end_block
= ctx
->block
;
1906 stream_out_block
= ir3_block_create(ir
);
1907 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
1909 new_end_block
= ir3_block_create(ir
);
1910 list_addtail(&new_end_block
->node
, &ir
->block_list
);
1912 orig_end_block
->successors
[0] = stream_out_block
;
1913 orig_end_block
->successors
[1] = new_end_block
;
1914 stream_out_block
->successors
[0] = new_end_block
;
1916 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
1917 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
1918 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1919 cond
->cat2
.condition
= IR3_COND_LT
;
1921 /* condition goes on previous block to the conditional,
1922 * since it is used to pick which of the two successor
1925 orig_end_block
->condition
= cond
;
1927 /* switch to stream_out_block to generate the stream-out
1930 ctx
->block
= stream_out_block
;
1932 /* Calculate base addresses based on vtxcnt. Instructions
1933 * generated for bases not used in following loop will be
1934 * stripped out in the backend.
1936 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
1937 unsigned stride
= strmout
->stride
[i
];
1938 struct ir3_instruction
*base
, *off
;
1940 base
= create_uniform(ctx
, regid(v
->first_driver_param
+ IR3_TFBOS_OFF
, i
));
1942 /* 24-bit should be enough: */
1943 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
1944 create_immed(ctx
->block
, stride
* 4), 0);
1946 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
1949 /* Generate the per-output store instructions: */
1950 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
1951 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
1952 unsigned c
= j
+ strmout
->output
[i
].start_component
;
1953 struct ir3_instruction
*base
, *out
, *stg
;
1955 base
= bases
[strmout
->output
[i
].output_buffer
];
1956 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
1958 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
1959 create_immed(ctx
->block
, 1), 0);
1960 stg
->cat6
.type
= TYPE_U32
;
1961 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
1963 array_insert(ctx
->ir
->keeps
, stg
);
1967 /* and finally switch to the new_end_block: */
1968 ctx
->block
= new_end_block
;
1972 emit_function(struct ir3_compile
*ctx
, nir_function_impl
*impl
)
1974 nir_metadata_require(impl
, nir_metadata_block_index
);
1976 emit_cf_list(ctx
, &impl
->body
);
1977 emit_block(ctx
, impl
->end_block
);
1979 /* at this point, we should have a single empty block,
1980 * into which we emit the 'end' instruction.
1982 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
1984 /* If stream-out (aka transform-feedback) enabled, emit the
1985 * stream-out instructions, followed by a new empty block (into
1986 * which the 'end' instruction lands).
1988 * NOTE: it is done in this order, rather than inserting before
1989 * we emit end_block, because NIR guarantees that all blocks
1990 * flow into end_block, and that end_block has no successors.
1991 * So by re-purposing end_block as the first block of stream-
1992 * out, we guarantee that all exit paths flow into the stream-
1995 if ((ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
1996 !ctx
->so
->key
.binning_pass
) {
1997 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
1998 emit_stream_out(ctx
);
2001 ir3_END(ctx
->block
);
2005 setup_input(struct ir3_compile
*ctx
, nir_variable
*in
)
2007 struct ir3_shader_variant
*so
= ctx
->so
;
2008 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
2009 unsigned ncomp
= glsl_get_components(in
->type
);
2010 unsigned n
= in
->data
.driver_location
;
2011 unsigned slot
= in
->data
.location
;
2013 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
2014 slot
, array_len
, ncomp
, n
);
2016 so
->inputs
[n
].slot
= slot
;
2017 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
2018 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2019 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2021 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2022 for (int i
= 0; i
< ncomp
; i
++) {
2023 struct ir3_instruction
*instr
= NULL
;
2024 unsigned idx
= (n
* 4) + i
;
2026 if (slot
== VARYING_SLOT_POS
) {
2027 so
->inputs
[n
].bary
= false;
2028 so
->frag_coord
= true;
2029 instr
= create_frag_coord(ctx
, i
);
2030 } else if (slot
== VARYING_SLOT_FACE
) {
2031 so
->inputs
[n
].bary
= false;
2032 so
->frag_face
= true;
2033 instr
= create_frag_face(ctx
, i
);
2035 bool use_ldlv
= false;
2037 /* detect the special case for front/back colors where
2038 * we need to do flat vs smooth shading depending on
2041 if (in
->data
.interpolation
== INTERP_QUALIFIER_NONE
) {
2043 case VARYING_SLOT_COL0
:
2044 case VARYING_SLOT_COL1
:
2045 case VARYING_SLOT_BFC0
:
2046 case VARYING_SLOT_BFC1
:
2047 so
->inputs
[n
].rasterflat
= true;
2054 if (ctx
->flat_bypass
) {
2055 if ((so
->inputs
[n
].interpolate
== INTERP_QUALIFIER_FLAT
) ||
2056 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2060 so
->inputs
[n
].bary
= true;
2062 instr
= create_frag_input(ctx
, use_ldlv
);
2065 ctx
->ir
->inputs
[idx
] = instr
;
2067 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2068 for (int i
= 0; i
< ncomp
; i
++) {
2069 unsigned idx
= (n
* 4) + i
;
2070 ctx
->ir
->inputs
[idx
] = create_input(ctx
->block
, idx
);
2073 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2076 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
2077 so
->total_in
+= ncomp
;
2082 setup_output(struct ir3_compile
*ctx
, nir_variable
*out
)
2084 struct ir3_shader_variant
*so
= ctx
->so
;
2085 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
2086 unsigned ncomp
= glsl_get_components(out
->type
);
2087 unsigned n
= out
->data
.driver_location
;
2088 unsigned slot
= out
->data
.location
;
2091 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
2092 slot
, array_len
, ncomp
, n
);
2094 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2096 case FRAG_RESULT_DEPTH
:
2097 comp
= 2; /* tgsi will write to .z component */
2098 so
->writes_pos
= true;
2100 case FRAG_RESULT_COLOR
:
2104 if (slot
>= FRAG_RESULT_DATA0
)
2106 compile_error(ctx
, "unknown FS output name: %s\n",
2107 gl_frag_result_name(slot
));
2109 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
2111 case VARYING_SLOT_POS
:
2112 so
->writes_pos
= true;
2114 case VARYING_SLOT_PSIZ
:
2115 so
->writes_psize
= true;
2117 case VARYING_SLOT_COL0
:
2118 case VARYING_SLOT_COL1
:
2119 case VARYING_SLOT_BFC0
:
2120 case VARYING_SLOT_BFC1
:
2121 case VARYING_SLOT_FOGC
:
2122 case VARYING_SLOT_CLIP_DIST0
:
2123 case VARYING_SLOT_CLIP_DIST1
:
2125 case VARYING_SLOT_CLIP_VERTEX
:
2126 /* handled entirely in nir_lower_clip: */
2129 if (slot
>= VARYING_SLOT_VAR0
)
2131 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
2133 compile_error(ctx
, "unknown VS output name: %s\n",
2134 gl_varying_slot_name(slot
));
2137 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2140 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
2142 so
->outputs
[n
].slot
= slot
;
2143 so
->outputs
[n
].regid
= regid(n
, comp
);
2144 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
2146 for (int i
= 0; i
< ncomp
; i
++) {
2147 unsigned idx
= (n
* 4) + i
;
2149 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2154 emit_instructions(struct ir3_compile
*ctx
)
2156 unsigned ninputs
, noutputs
;
2157 nir_function_impl
*fxn
= NULL
;
2159 /* Find the main function: */
2160 nir_foreach_function(ctx
->s
, function
) {
2161 compile_assert(ctx
, strcmp(function
->name
, "main") == 0);
2162 compile_assert(ctx
, function
->impl
);
2163 fxn
= function
->impl
;
2167 ninputs
= exec_list_length(&ctx
->s
->inputs
) * 4;
2168 noutputs
= exec_list_length(&ctx
->s
->outputs
) * 4;
2170 /* or vtx shaders, we need to leave room for sysvals:
2172 if (ctx
->so
->type
== SHADER_VERTEX
) {
2176 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
2178 /* Create inputs in first block: */
2179 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
2180 ctx
->in_block
= ctx
->block
;
2181 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
2183 if (ctx
->so
->type
== SHADER_VERTEX
) {
2184 ctx
->ir
->ninputs
-= 8;
2187 /* for fragment shader, we have a single input register (usually
2188 * r0.xy) which is used as the base for bary.f varying fetch instrs:
2190 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
2191 // TODO maybe a helper for fi since we need it a few places..
2192 struct ir3_instruction
*instr
;
2193 instr
= ir3_instr_create(ctx
->block
, OPC_META_FI
);
2194 ir3_reg_create(instr
, 0, 0);
2195 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.x */
2196 ir3_reg_create(instr
, 0, IR3_REG_SSA
); /* r0.y */
2197 ctx
->frag_pos
= instr
;
2201 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
2202 setup_input(ctx
, var
);
2205 /* Setup outputs: */
2206 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
2207 setup_output(ctx
, var
);
2210 /* Setup global variables (which should only be arrays): */
2211 nir_foreach_variable(var
, &ctx
->s
->globals
) {
2212 declare_var(ctx
, var
);
2215 /* Setup local variables (which should only be arrays): */
2216 /* NOTE: need to do something more clever when we support >1 fxn */
2217 nir_foreach_variable(var
, &fxn
->locals
) {
2218 declare_var(ctx
, var
);
2221 /* And emit the body: */
2223 emit_function(ctx
, fxn
);
2225 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2226 resolve_phis(ctx
, block
);
2230 /* from NIR perspective, we actually have inputs. But most of the "inputs"
2231 * for a fragment shader are just bary.f instructions. The *actual* inputs
2232 * from the hw perspective are the frag_pos and optionally frag_coord and
2236 fixup_frag_inputs(struct ir3_compile
*ctx
)
2238 struct ir3_shader_variant
*so
= ctx
->so
;
2239 struct ir3
*ir
= ctx
->ir
;
2240 struct ir3_instruction
**inputs
;
2241 struct ir3_instruction
*instr
;
2246 n
= 4; /* always have frag_pos */
2247 n
+= COND(so
->frag_face
, 4);
2248 n
+= COND(so
->frag_coord
, 4);
2250 inputs
= ir3_alloc(ctx
->ir
, n
* (sizeof(struct ir3_instruction
*)));
2252 if (so
->frag_face
) {
2253 /* this ultimately gets assigned to hr0.x so doesn't conflict
2254 * with frag_coord/frag_pos..
2256 inputs
[ir
->ninputs
++] = ctx
->frag_face
;
2257 ctx
->frag_face
->regs
[0]->num
= 0;
2259 /* remaining channels not used, but let's avoid confusing
2260 * other parts that expect inputs to come in groups of vec4
2262 inputs
[ir
->ninputs
++] = NULL
;
2263 inputs
[ir
->ninputs
++] = NULL
;
2264 inputs
[ir
->ninputs
++] = NULL
;
2267 /* since we don't know where to set the regid for frag_coord,
2268 * we have to use r0.x for it. But we don't want to *always*
2269 * use r1.x for frag_pos as that could increase the register
2270 * footprint on simple shaders:
2272 if (so
->frag_coord
) {
2273 ctx
->frag_coord
[0]->regs
[0]->num
= regid
++;
2274 ctx
->frag_coord
[1]->regs
[0]->num
= regid
++;
2275 ctx
->frag_coord
[2]->regs
[0]->num
= regid
++;
2276 ctx
->frag_coord
[3]->regs
[0]->num
= regid
++;
2278 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[0];
2279 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[1];
2280 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[2];
2281 inputs
[ir
->ninputs
++] = ctx
->frag_coord
[3];
2284 /* we always have frag_pos: */
2285 so
->pos_regid
= regid
;
2288 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2289 instr
->regs
[0]->num
= regid
++;
2290 inputs
[ir
->ninputs
++] = instr
;
2291 ctx
->frag_pos
->regs
[1]->instr
= instr
;
2294 instr
= create_input(ctx
->in_block
, ir
->ninputs
);
2295 instr
->regs
[0]->num
= regid
++;
2296 inputs
[ir
->ninputs
++] = instr
;
2297 ctx
->frag_pos
->regs
[2]->instr
= instr
;
2299 ir
->inputs
= inputs
;
2302 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2303 * need to assign the tex state indexes for these after we know the
2307 fixup_astc_srgb(struct ir3_compile
*ctx
)
2309 struct ir3_shader_variant
*so
= ctx
->so
;
2310 /* indexed by original tex idx, value is newly assigned alpha sampler
2311 * state tex idx. Zero is invalid since there is at least one sampler
2314 unsigned alt_tex_state
[16] = {0};
2315 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
2318 so
->astc_srgb
.base
= tex_idx
;
2320 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
2321 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
2323 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
2325 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
2326 /* assign new alternate/alpha tex state slot: */
2327 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
2328 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
2329 so
->astc_srgb
.count
++;
2332 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
2337 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
2338 struct ir3_shader_variant
*so
)
2340 struct ir3_compile
*ctx
;
2342 struct ir3_instruction
**inputs
;
2343 unsigned i
, j
, actual_in
, inloc
;
2344 int ret
= 0, max_bary
;
2348 ctx
= compile_init(compiler
, so
);
2350 DBG("INIT failed!");
2355 emit_instructions(ctx
);
2358 DBG("EMIT failed!");
2363 ir
= so
->ir
= ctx
->ir
;
2365 /* keep track of the inputs from TGSI perspective.. */
2366 inputs
= ir
->inputs
;
2368 /* but fixup actual inputs for frag shader: */
2369 if (so
->type
== SHADER_FRAGMENT
)
2370 fixup_frag_inputs(ctx
);
2372 /* at this point, for binning pass, throw away unneeded outputs: */
2373 if (so
->key
.binning_pass
) {
2374 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
2375 unsigned slot
= so
->outputs
[i
].slot
;
2377 /* throw away everything but first position/psize */
2378 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
2380 so
->outputs
[j
] = so
->outputs
[i
];
2381 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
2382 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
2383 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
2384 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
2389 so
->outputs_count
= j
;
2390 ir
->noutputs
= j
* 4;
2393 /* if we want half-precision outputs, mark the output registers
2396 if (so
->key
.half_precision
) {
2397 for (i
= 0; i
< ir
->noutputs
; i
++) {
2398 struct ir3_instruction
*out
= ir
->outputs
[i
];
2401 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2402 /* output could be a fanout (ie. texture fetch output)
2403 * in which case we need to propagate the half-reg flag
2404 * up to the definer so that RA sees it:
2406 if (out
->opc
== OPC_META_FO
) {
2407 out
= out
->regs
[1]->instr
;
2408 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2411 if (out
->opc
== OPC_MOV
) {
2412 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
2417 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2418 printf("BEFORE CP:\n");
2424 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2425 printf("BEFORE GROUPING:\n");
2429 /* Group left/right neighbors, inserting mov's where needed to
2436 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2437 printf("AFTER DEPTH:\n");
2441 ret
= ir3_sched(ir
);
2443 DBG("SCHED failed!");
2447 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2448 printf("AFTER SCHED:\n");
2452 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
2458 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2459 printf("AFTER RA:\n");
2463 /* fixup input/outputs: */
2464 for (i
= 0; i
< so
->outputs_count
; i
++) {
2465 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
2466 /* preserve hack for depth output.. tgsi writes depth to .z,
2467 * but what we give the hw is the scalar register:
2469 if ((so
->type
== SHADER_FRAGMENT
) &&
2470 (so
->outputs
[i
].slot
== FRAG_RESULT_DEPTH
))
2471 so
->outputs
[i
].regid
+= 2;
2474 /* Note that some or all channels of an input may be unused: */
2477 for (i
= 0; i
< so
->inputs_count
; i
++) {
2478 unsigned j
, regid
= ~0, compmask
= 0;
2479 so
->inputs
[i
].ncomp
= 0;
2480 so
->inputs
[i
].inloc
= inloc
+ 8;
2481 for (j
= 0; j
< 4; j
++) {
2482 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
2483 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
2484 compmask
|= (1 << j
);
2485 regid
= in
->regs
[0]->num
- j
;
2487 so
->inputs
[i
].ncomp
++;
2488 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
2490 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
2491 in
->regs
[1]->iim_val
= inloc
++;
2495 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
)
2497 so
->inputs
[i
].regid
= regid
;
2498 so
->inputs
[i
].compmask
= compmask
;
2502 fixup_astc_srgb(ctx
);
2504 /* We need to do legalize after (for frag shader's) the "bary.f"
2505 * offsets (inloc) have been assigned.
2507 ir3_legalize(ir
, &so
->has_samp
, &max_bary
);
2509 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
2510 printf("AFTER LEGALIZE:\n");
2514 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
2515 if (so
->type
== SHADER_VERTEX
)
2516 so
->total_in
= actual_in
;
2518 so
->total_in
= max_bary
+ 1;
2523 ir3_destroy(so
->ir
);