1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
31 #include "pipe/p_state.h"
32 #include "util/u_string.h"
33 #include "util/u_memory.h"
34 #include "util/u_inlines.h"
36 #include "freedreno_util.h"
38 #include "ir3_compiler.h"
39 #include "ir3_shader.h"
42 #include "instr-a3xx.h"
47 struct ir3_compiler
*compiler
;
52 struct ir3_shader_variant
*so
;
54 struct ir3_block
*block
; /* the current block */
55 struct ir3_block
*in_block
; /* block created for shader inputs */
57 nir_function_impl
*impl
;
59 /* For fragment shaders, varyings are not actual shader inputs,
60 * instead the hw passes a varying-coord which is used with
63 * But NIR doesn't know that, it still declares varyings as
64 * inputs. So we do all the input tracking normally and fix
65 * things up after compile_instructions()
67 * NOTE that frag_vcoord is the hardware position (possibly it
68 * is actually an index or tag or some such.. it is *not*
69 * values that can be directly used for gl_FragCoord..)
71 struct ir3_instruction
*frag_vcoord
;
73 /* for fragment shaders, for gl_FrontFacing and gl_FragCoord: */
74 struct ir3_instruction
*frag_face
, *frag_coord
;
76 /* For vertex shaders, keep track of the system values sources */
77 struct ir3_instruction
*vertex_id
, *basevertex
, *instance_id
;
79 /* For fragment shaders: */
80 struct ir3_instruction
*samp_id
, *samp_mask_in
;
82 /* Compute shader inputs: */
83 struct ir3_instruction
*local_invocation_id
, *work_group_id
;
85 /* mapping from nir_register to defining instruction: */
86 struct hash_table
*def_ht
;
90 /* a common pattern for indirect addressing is to request the
91 * same address register multiple times. To avoid generating
92 * duplicate instruction sequences (which our backend does not
93 * try to clean up, since that should be done as the NIR stage)
94 * we cache the address value generated for a given src value:
96 * Note that we have to cache these per alignment, since same
97 * src used for an array of vec1 cannot be also used for an
100 struct hash_table
*addr_ht
[4];
102 /* last dst array, for indirect we need to insert a var-store.
104 struct ir3_instruction
**last_dst
;
107 /* maps nir_block to ir3_block, mostly for the purposes of
108 * figuring out the blocks successors
110 struct hash_table
*block_ht
;
112 /* on a4xx, bitmask of samplers which need astc+srgb workaround: */
115 unsigned samples
; /* bitmask of x,y sample shifts */
117 unsigned max_texture_index
;
119 /* set if we encounter something we can't handle yet, so we
120 * can bail cleanly and fallback to TGSI compiler f/e
125 /* gpu pointer size in units of 32bit registers/slots */
126 static unsigned pointer_size(struct ir3_context
*ctx
)
128 return (ctx
->compiler
->gpu_id
>= 500) ? 2 : 1;
131 static struct ir3_instruction
* create_immed(struct ir3_block
*block
, uint32_t val
);
132 static struct ir3_block
* get_block(struct ir3_context
*ctx
, const nir_block
*nblock
);
135 static struct ir3_context
*
136 compile_init(struct ir3_compiler
*compiler
,
137 struct ir3_shader_variant
*so
)
139 struct ir3_context
*ctx
= rzalloc(NULL
, struct ir3_context
);
141 if (compiler
->gpu_id
>= 400) {
142 if (so
->type
== SHADER_VERTEX
) {
143 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
144 } else if (so
->type
== SHADER_FRAGMENT
) {
145 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
149 if (so
->type
== SHADER_VERTEX
) {
150 ctx
->samples
= so
->key
.vsamples
;
151 } else if (so
->type
== SHADER_FRAGMENT
) {
152 ctx
->samples
= so
->key
.fsamples
;
156 ctx
->compiler
= compiler
;
158 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
159 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
160 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
161 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
163 /* TODO: maybe generate some sort of bitmask of what key
164 * lowers vs what shader has (ie. no need to lower
165 * texture clamp lowering if no texture sample instrs)..
166 * although should be done further up the stack to avoid
167 * creating duplicate variants..
170 if (ir3_key_lowers_nir(&so
->key
)) {
171 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
172 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
174 /* fast-path for shader key that lowers nothing in NIR: */
175 ctx
->s
= so
->shader
->nir
;
178 /* this needs to be the last pass run, so do this here instead of
179 * in ir3_optimize_nir():
181 NIR_PASS_V(ctx
->s
, nir_lower_locals_to_regs
);
182 NIR_PASS_V(ctx
->s
, nir_convert_from_ssa
, true);
184 if (fd_mesa_debug
& FD_DBG_DISASM
) {
185 DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
186 so
->shader
->id
, so
->id
, so
->type
,
187 so
->key
.binning_pass
, so
->key
.color_two_side
,
188 so
->key
.half_precision
);
189 nir_print_shader(ctx
->s
, stdout
);
192 if (shader_debug_enabled(so
->type
)) {
193 fprintf(stderr
, "NIR (final form) for %s shader:\n",
194 shader_stage_name(so
->type
));
195 nir_print_shader(ctx
->s
, stderr
);
198 ir3_nir_scan_driver_consts(ctx
->s
, &so
->const_layout
);
200 so
->num_uniforms
= ctx
->s
->num_uniforms
;
201 so
->num_ubos
= ctx
->s
->info
.num_ubos
;
203 /* Layout of constant registers, each section aligned to vec4. Note
204 * that pointer size (ubo, etc) changes depending on generation.
209 * if (vertex shader) {
210 * driver params (IR3_DP_*)
211 * if (stream_output.num_outputs > 0)
212 * stream-out addresses
216 * Immediates go last mostly because they are inserted in the CP pass
217 * after the nir -> ir3 frontend.
219 unsigned constoff
= align(ctx
->s
->num_uniforms
, 4);
220 unsigned ptrsz
= pointer_size(ctx
);
222 memset(&so
->constbase
, ~0, sizeof(so
->constbase
));
224 if (so
->num_ubos
> 0) {
225 so
->constbase
.ubo
= constoff
;
226 constoff
+= align(ctx
->s
->info
.num_ubos
* ptrsz
, 4) / 4;
229 if (so
->const_layout
.ssbo_size
.count
> 0) {
230 unsigned cnt
= so
->const_layout
.ssbo_size
.count
;
231 so
->constbase
.ssbo_sizes
= constoff
;
232 constoff
+= align(cnt
, 4) / 4;
235 if (so
->const_layout
.image_dims
.count
> 0) {
236 unsigned cnt
= so
->const_layout
.image_dims
.count
;
237 so
->constbase
.image_dims
= constoff
;
238 constoff
+= align(cnt
, 4) / 4;
241 unsigned num_driver_params
= 0;
242 if (so
->type
== SHADER_VERTEX
) {
243 num_driver_params
= IR3_DP_VS_COUNT
;
244 } else if (so
->type
== SHADER_COMPUTE
) {
245 num_driver_params
= IR3_DP_CS_COUNT
;
248 so
->constbase
.driver_param
= constoff
;
249 constoff
+= align(num_driver_params
, 4) / 4;
251 if ((so
->type
== SHADER_VERTEX
) &&
252 (compiler
->gpu_id
< 500) &&
253 so
->shader
->stream_output
.num_outputs
> 0) {
254 so
->constbase
.tfbo
= constoff
;
255 constoff
+= align(PIPE_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
258 so
->constbase
.immediate
= constoff
;
264 compile_error(struct ir3_context
*ctx
, const char *format
, ...)
267 va_start(ap
, format
);
268 _debug_vprintf(format
, ap
);
270 nir_print_shader(ctx
->s
, stdout
);
275 #define compile_assert(ctx, cond) do { \
276 if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
280 compile_free(struct ir3_context
*ctx
)
286 declare_array(struct ir3_context
*ctx
, nir_register
*reg
)
288 struct ir3_array
*arr
= rzalloc(ctx
, struct ir3_array
);
289 arr
->id
= ++ctx
->num_arrays
;
290 /* NOTE: sometimes we get non array regs, for example for arrays of
291 * length 1. See fs-const-array-of-struct-of-array.shader_test. So
292 * treat a non-array as if it was an array of length 1.
294 * It would be nice if there was a nir pass to convert arrays of
297 arr
->length
= reg
->num_components
* MAX2(1, reg
->num_array_elems
);
298 compile_assert(ctx
, arr
->length
> 0);
300 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
303 static struct ir3_array
*
304 get_array(struct ir3_context
*ctx
, nir_register
*reg
)
306 list_for_each_entry (struct ir3_array
, arr
, &ctx
->ir
->array_list
, node
) {
310 compile_error(ctx
, "bogus reg: %s\n", reg
->name
);
314 /* relative (indirect) if address!=NULL */
315 static struct ir3_instruction
*
316 create_array_load(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
317 struct ir3_instruction
*address
)
319 struct ir3_block
*block
= ctx
->block
;
320 struct ir3_instruction
*mov
;
321 struct ir3_register
*src
;
323 mov
= ir3_instr_create(block
, OPC_MOV
);
324 mov
->cat1
.src_type
= TYPE_U32
;
325 mov
->cat1
.dst_type
= TYPE_U32
;
326 mov
->barrier_class
= IR3_BARRIER_ARRAY_R
;
327 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_W
;
328 ir3_reg_create(mov
, 0, 0);
329 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
330 COND(address
, IR3_REG_RELATIV
));
331 src
->instr
= arr
->last_write
;
332 src
->size
= arr
->length
;
333 src
->array
.id
= arr
->id
;
334 src
->array
.offset
= n
;
337 ir3_instr_set_address(mov
, address
);
342 /* relative (indirect) if address!=NULL */
344 create_array_store(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
345 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
347 struct ir3_block
*block
= ctx
->block
;
348 struct ir3_instruction
*mov
;
349 struct ir3_register
*dst
;
351 /* if not relative store, don't create an extra mov, since that
352 * ends up being difficult for cp to remove.
357 src
->barrier_class
|= IR3_BARRIER_ARRAY_W
;
358 src
->barrier_conflict
|= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
360 dst
->flags
|= IR3_REG_ARRAY
;
361 dst
->instr
= arr
->last_write
;
362 dst
->size
= arr
->length
;
363 dst
->array
.id
= arr
->id
;
364 dst
->array
.offset
= n
;
366 arr
->last_write
= src
;
368 array_insert(block
, block
->keeps
, src
);
373 mov
= ir3_instr_create(block
, OPC_MOV
);
374 mov
->cat1
.src_type
= TYPE_U32
;
375 mov
->cat1
.dst_type
= TYPE_U32
;
376 mov
->barrier_class
= IR3_BARRIER_ARRAY_W
;
377 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
378 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
379 COND(address
, IR3_REG_RELATIV
));
380 dst
->instr
= arr
->last_write
;
381 dst
->size
= arr
->length
;
382 dst
->array
.id
= arr
->id
;
383 dst
->array
.offset
= n
;
384 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
387 ir3_instr_set_address(mov
, address
);
389 arr
->last_write
= mov
;
391 /* the array store may only matter to something in an earlier
392 * block (ie. loops), but since arrays are not in SSA, depth
393 * pass won't know this.. so keep all array stores:
395 array_insert(block
, block
->keeps
, mov
);
398 static inline type_t
utype_for_size(unsigned bit_size
)
401 case 32: return TYPE_U32
;
402 case 16: return TYPE_U16
;
403 case 8: return TYPE_U8
;
404 default: unreachable("bad bitsize"); return ~0;
408 static inline type_t
utype_src(nir_src src
)
409 { return utype_for_size(nir_src_bit_size(src
)); }
411 static inline type_t
utype_dst(nir_dest dst
)
412 { return utype_for_size(nir_dest_bit_size(dst
)); }
414 /* allocate a n element value array (to be populated by caller) and
417 static struct ir3_instruction
**
418 get_dst_ssa(struct ir3_context
*ctx
, nir_ssa_def
*dst
, unsigned n
)
420 struct ir3_instruction
**value
=
421 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
422 _mesa_hash_table_insert(ctx
->def_ht
, dst
, value
);
426 static struct ir3_instruction
**
427 get_dst(struct ir3_context
*ctx
, nir_dest
*dst
, unsigned n
)
429 struct ir3_instruction
**value
;
432 value
= get_dst_ssa(ctx
, &dst
->ssa
, n
);
434 value
= ralloc_array(ctx
, struct ir3_instruction
*, n
);
437 /* NOTE: in non-ssa case, we don't really need to store last_dst
438 * but this helps us catch cases where put_dst() call is forgotten
440 compile_assert(ctx
, !ctx
->last_dst
);
441 ctx
->last_dst
= value
;
447 static struct ir3_instruction
* get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
);
449 static struct ir3_instruction
* const *
450 get_src(struct ir3_context
*ctx
, nir_src
*src
)
453 struct hash_entry
*entry
;
454 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
455 compile_assert(ctx
, entry
);
458 nir_register
*reg
= src
->reg
.reg
;
459 struct ir3_array
*arr
= get_array(ctx
, reg
);
460 unsigned num_components
= arr
->r
->num_components
;
461 struct ir3_instruction
*addr
= NULL
;
462 struct ir3_instruction
**value
=
463 ralloc_array(ctx
, struct ir3_instruction
*, num_components
);
465 if (src
->reg
.indirect
)
466 addr
= get_addr(ctx
, get_src(ctx
, src
->reg
.indirect
)[0],
467 reg
->num_components
);
469 for (unsigned i
= 0; i
< num_components
; i
++) {
470 unsigned n
= src
->reg
.base_offset
* reg
->num_components
+ i
;
471 compile_assert(ctx
, n
< arr
->length
);
472 value
[i
] = create_array_load(ctx
, arr
, n
, addr
);
480 put_dst(struct ir3_context
*ctx
, nir_dest
*dst
)
482 unsigned bit_size
= nir_dest_bit_size(*dst
);
485 for (unsigned i
= 0; i
< ctx
->last_dst_n
; i
++) {
486 struct ir3_instruction
*dst
= ctx
->last_dst
[i
];
487 dst
->regs
[0]->flags
|= IR3_REG_HALF
;
488 if (ctx
->last_dst
[i
]->opc
== OPC_META_FO
)
489 dst
->regs
[1]->instr
->regs
[0]->flags
|= IR3_REG_HALF
;
494 nir_register
*reg
= dst
->reg
.reg
;
495 struct ir3_array
*arr
= get_array(ctx
, reg
);
496 unsigned num_components
= ctx
->last_dst_n
;
497 struct ir3_instruction
*addr
= NULL
;
499 if (dst
->reg
.indirect
)
500 addr
= get_addr(ctx
, get_src(ctx
, dst
->reg
.indirect
)[0],
501 reg
->num_components
);
503 for (unsigned i
= 0; i
< num_components
; i
++) {
504 unsigned n
= dst
->reg
.base_offset
* reg
->num_components
+ i
;
505 compile_assert(ctx
, n
< arr
->length
);
506 if (!ctx
->last_dst
[i
])
508 create_array_store(ctx
, arr
, n
, ctx
->last_dst
[i
], addr
);
511 ralloc_free(ctx
->last_dst
);
513 ctx
->last_dst
= NULL
;
517 static struct ir3_instruction
*
518 create_immed_typed(struct ir3_block
*block
, uint32_t val
, type_t type
)
520 struct ir3_instruction
*mov
;
521 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
523 mov
= ir3_instr_create(block
, OPC_MOV
);
524 mov
->cat1
.src_type
= type
;
525 mov
->cat1
.dst_type
= type
;
526 ir3_reg_create(mov
, 0, flags
);
527 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
532 static struct ir3_instruction
*
533 create_immed(struct ir3_block
*block
, uint32_t val
)
535 return create_immed_typed(block
, val
, TYPE_U32
);
538 static struct ir3_instruction
*
539 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
, int align
)
541 struct ir3_instruction
*instr
, *immed
;
543 /* TODO in at least some cases, the backend could probably be
544 * made clever enough to propagate IR3_REG_HALF..
546 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
547 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
554 /* src *= 2 => src <<= 1: */
555 immed
= create_immed(block
, 1);
556 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
558 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
559 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
560 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
564 immed
= create_immed(block
, 3);
565 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
567 instr
= ir3_MULL_U(block
, instr
, 0, immed
, 0);
568 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
569 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
572 /* src *= 4 => src <<= 2: */
573 immed
= create_immed(block
, 2);
574 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
576 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
577 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
578 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
581 unreachable("bad align");
585 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
586 instr
->regs
[0]->num
= regid(REG_A0
, 0);
587 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
588 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
593 /* caches addr values to avoid generating multiple cov/shl/mova
594 * sequences for each use of a given NIR level src as address
596 static struct ir3_instruction
*
597 get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
)
599 struct ir3_instruction
*addr
;
600 unsigned idx
= align
- 1;
602 compile_assert(ctx
, idx
< ARRAY_SIZE(ctx
->addr_ht
));
604 if (!ctx
->addr_ht
[idx
]) {
605 ctx
->addr_ht
[idx
] = _mesa_hash_table_create(ctx
,
606 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
608 struct hash_entry
*entry
;
609 entry
= _mesa_hash_table_search(ctx
->addr_ht
[idx
], src
);
614 addr
= create_addr(ctx
->block
, src
, align
);
615 _mesa_hash_table_insert(ctx
->addr_ht
[idx
], src
, addr
);
620 static struct ir3_instruction
*
621 get_predicate(struct ir3_context
*ctx
, struct ir3_instruction
*src
)
623 struct ir3_block
*b
= ctx
->block
;
624 struct ir3_instruction
*cond
;
626 /* NOTE: only cmps.*.* can write p0.x: */
627 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
628 cond
->cat2
.condition
= IR3_COND_NE
;
630 /* condition always goes in predicate register: */
631 cond
->regs
[0]->num
= regid(REG_P0
, 0);
636 static struct ir3_instruction
*
637 create_uniform(struct ir3_context
*ctx
, unsigned n
)
639 struct ir3_instruction
*mov
;
641 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
642 /* TODO get types right? */
643 mov
->cat1
.src_type
= TYPE_F32
;
644 mov
->cat1
.dst_type
= TYPE_F32
;
645 ir3_reg_create(mov
, 0, 0);
646 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
651 static struct ir3_instruction
*
652 create_uniform_indirect(struct ir3_context
*ctx
, int n
,
653 struct ir3_instruction
*address
)
655 struct ir3_instruction
*mov
;
657 mov
= ir3_instr_create(ctx
->block
, OPC_MOV
);
658 mov
->cat1
.src_type
= TYPE_U32
;
659 mov
->cat1
.dst_type
= TYPE_U32
;
660 ir3_reg_create(mov
, 0, 0);
661 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
663 ir3_instr_set_address(mov
, address
);
668 static struct ir3_instruction
*
669 create_collect(struct ir3_context
*ctx
, struct ir3_instruction
*const *arr
,
672 struct ir3_block
*block
= ctx
->block
;
673 struct ir3_instruction
*collect
;
678 unsigned flags
= arr
[0]->regs
[0]->flags
& IR3_REG_HALF
;
680 collect
= ir3_instr_create2(block
, OPC_META_FI
, 1 + arrsz
);
681 ir3_reg_create(collect
, 0, flags
); /* dst */
682 for (unsigned i
= 0; i
< arrsz
; i
++) {
683 struct ir3_instruction
*elem
= arr
[i
];
685 /* Since arrays are pre-colored in RA, we can't assume that
686 * things will end up in the right place. (Ie. if a collect
687 * joins elements from two different arrays.) So insert an
690 * We could possibly skip this if all the collected elements
691 * are contiguous elements in a single array.. not sure how
692 * likely that is to happen.
694 * Fixes a problem with glamor shaders, that in effect do
701 * color = texture2D(tex, texcoord);
703 * In this case, texcoord will end up as nir registers (which
704 * translate to ir3 array's of length 1. And we can't assume
705 * the two (or more) arrays will get allocated in consecutive
709 if (elem
->regs
[0]->flags
& IR3_REG_ARRAY
) {
710 type_t type
= (flags
& IR3_REG_HALF
) ? TYPE_U16
: TYPE_U32
;
711 elem
= ir3_MOV(block
, elem
, type
);
714 compile_assert(ctx
, (elem
->regs
[0]->flags
& IR3_REG_HALF
) == flags
);
715 ir3_reg_create(collect
, 0, IR3_REG_SSA
| flags
)->instr
= elem
;
721 static struct ir3_instruction
*
722 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
723 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
725 struct ir3_block
*block
= ctx
->block
;
726 struct ir3_instruction
*mov
;
727 struct ir3_register
*src
;
729 mov
= ir3_instr_create(block
, OPC_MOV
);
730 mov
->cat1
.src_type
= TYPE_U32
;
731 mov
->cat1
.dst_type
= TYPE_U32
;
732 ir3_reg_create(mov
, 0, 0);
733 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
734 src
->instr
= collect
;
736 src
->array
.offset
= n
;
738 ir3_instr_set_address(mov
, address
);
743 static struct ir3_instruction
*
744 create_input_compmask(struct ir3_context
*ctx
, unsigned n
, unsigned compmask
)
746 struct ir3_instruction
*in
;
748 in
= ir3_instr_create(ctx
->in_block
, OPC_META_INPUT
);
749 in
->inout
.block
= ctx
->in_block
;
750 ir3_reg_create(in
, n
, 0);
752 in
->regs
[0]->wrmask
= compmask
;
757 static struct ir3_instruction
*
758 create_input(struct ir3_context
*ctx
, unsigned n
)
760 return create_input_compmask(ctx
, n
, 0x1);
763 static struct ir3_instruction
*
764 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
)
766 struct ir3_block
*block
= ctx
->block
;
767 struct ir3_instruction
*instr
;
768 /* actual inloc is assigned and fixed up later: */
769 struct ir3_instruction
*inloc
= create_immed(block
, 0);
772 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
773 instr
->cat6
.type
= TYPE_U32
;
774 instr
->cat6
.iim_val
= 1;
776 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->frag_vcoord
, 0);
777 instr
->regs
[2]->wrmask
= 0x3;
783 static struct ir3_instruction
*
784 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
786 /* first four vec4 sysval's reserved for UBOs: */
787 /* NOTE: dp is in scalar, but there can be >4 dp components: */
788 unsigned n
= ctx
->so
->constbase
.driver_param
;
789 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
790 return create_uniform(ctx
, r
);
793 /* helper for instructions that produce multiple consecutive scalar
794 * outputs which need to have a split/fanout meta instruction inserted
797 split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
798 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
800 struct ir3_instruction
*prev
= NULL
;
802 if ((n
== 1) && (src
->regs
[0]->wrmask
== 0x1)) {
807 for (int i
= 0, j
= 0; i
< n
; i
++) {
808 struct ir3_instruction
*split
= ir3_instr_create(block
, OPC_META_FO
);
809 ir3_reg_create(split
, 0, IR3_REG_SSA
);
810 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
811 split
->fo
.off
= i
+ base
;
814 split
->cp
.left
= prev
;
815 split
->cp
.left_cnt
++;
816 prev
->cp
.right
= split
;
817 prev
->cp
.right_cnt
++;
821 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
827 * Adreno uses uint rather than having dedicated bool type,
828 * which (potentially) requires some conversion, in particular
829 * when using output of an bool instr to int input, or visa
833 * -------+---------+-------+-
837 * To convert from an adreno bool (uint) to nir, use:
839 * absneg.s dst, (neg)src
841 * To convert back in the other direction:
843 * absneg.s dst, (abs)arc
845 * The CP step can clean up the absneg.s that cancel each other
846 * out, and with a slight bit of extra cleverness (to recognize
847 * the instructions which produce either a 0 or 1) can eliminate
848 * the absneg.s's completely when an instruction that wants
849 * 0/1 consumes the result. For example, when a nir 'bcsel'
850 * consumes the result of 'feq'. So we should be able to get by
851 * without a boolean resolve step, and without incuring any
852 * extra penalty in instruction count.
855 /* NIR bool -> native (adreno): */
856 static struct ir3_instruction
*
857 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
859 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
862 /* native (adreno) -> NIR bool: */
863 static struct ir3_instruction
*
864 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
866 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
870 * alu/sfu instructions:
873 static struct ir3_instruction
*
874 create_cov(struct ir3_context
*ctx
, struct ir3_instruction
*src
,
875 unsigned src_bitsize
, nir_op op
)
877 type_t src_type
, dst_type
;
881 case nir_op_f2f16_rtne
:
882 case nir_op_f2f16_rtz
:
890 switch (src_bitsize
) {
898 compile_error(ctx
, "invalid src bit size: %u", src_bitsize
);
907 switch (src_bitsize
) {
918 compile_error(ctx
, "invalid src bit size: %u", src_bitsize
);
927 switch (src_bitsize
) {
938 compile_error(ctx
, "invalid src bit size: %u", src_bitsize
);
943 compile_error(ctx
, "invalid conversion op: %u", op
);
953 case nir_op_f2f16_rtne
:
954 case nir_op_f2f16_rtz
:
956 /* TODO how to handle rounding mode? */
993 compile_error(ctx
, "invalid conversion op: %u", op
);
996 return ir3_COV(ctx
->block
, src
, src_type
, dst_type
);
1000 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
1002 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
1003 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
1004 unsigned bs
[info
->num_inputs
]; /* bit size */
1005 struct ir3_block
*b
= ctx
->block
;
1006 unsigned dst_sz
, wrmask
;
1008 if (alu
->dest
.dest
.is_ssa
) {
1009 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
1010 wrmask
= (1 << dst_sz
) - 1;
1012 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
1013 wrmask
= alu
->dest
.write_mask
;
1016 dst
= get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
1018 /* Vectors are special in that they have non-scalarized writemasks,
1019 * and just take the first swizzle channel for each argument in
1020 * order into each writemask channel.
1022 if ((alu
->op
== nir_op_vec2
) ||
1023 (alu
->op
== nir_op_vec3
) ||
1024 (alu
->op
== nir_op_vec4
)) {
1026 for (int i
= 0; i
< info
->num_inputs
; i
++) {
1027 nir_alu_src
*asrc
= &alu
->src
[i
];
1029 compile_assert(ctx
, !asrc
->abs
);
1030 compile_assert(ctx
, !asrc
->negate
);
1032 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
1034 src
[i
] = create_immed(ctx
->block
, 0);
1035 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
1038 put_dst(ctx
, &alu
->dest
.dest
);
1042 /* We also get mov's with more than one component for mov's so
1043 * handle those specially:
1045 if ((alu
->op
== nir_op_imov
) || (alu
->op
== nir_op_fmov
)) {
1046 type_t type
= (alu
->op
== nir_op_imov
) ? TYPE_U32
: TYPE_F32
;
1047 nir_alu_src
*asrc
= &alu
->src
[0];
1048 struct ir3_instruction
*const *src0
= get_src(ctx
, &asrc
->src
);
1050 for (unsigned i
= 0; i
< dst_sz
; i
++) {
1051 if (wrmask
& (1 << i
)) {
1052 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], type
);
1058 put_dst(ctx
, &alu
->dest
.dest
);
1062 /* General case: We can just grab the one used channel per src. */
1063 for (int i
= 0; i
< info
->num_inputs
; i
++) {
1064 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
1065 nir_alu_src
*asrc
= &alu
->src
[i
];
1067 compile_assert(ctx
, !asrc
->abs
);
1068 compile_assert(ctx
, !asrc
->negate
);
1070 src
[i
] = get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
1071 bs
[i
] = nir_src_bit_size(asrc
->src
);
1073 compile_assert(ctx
, src
[i
]);
1078 case nir_op_f2f16_rtne
:
1079 case nir_op_f2f16_rtz
:
1097 dst
[0] = create_cov(ctx
, src
[0], bs
[0], alu
->op
);
1100 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
1101 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1102 dst
[0] = ir3_n2b(b
, dst
[0]);
1105 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
1108 dst
[0] = ir3_b2n(b
, src
[0]);
1111 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1112 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1113 dst
[0] = ir3_n2b(b
, dst
[0]);
1117 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
1120 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
1123 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
1126 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
1129 /* if there is just a single use of the src, and it supports
1130 * (sat) bit, we can just fold the (sat) flag back to the
1131 * src instruction and create a mov. This is easier for cp
1134 * TODO probably opc_cat==4 is ok too
1136 if (alu
->src
[0].src
.is_ssa
&&
1137 (list_length(&alu
->src
[0].src
.ssa
->uses
) == 1) &&
1138 ((opc_cat(src
[0]->opc
) == 2) || (opc_cat(src
[0]->opc
) == 3))) {
1139 src
[0]->flags
|= IR3_INSTR_SAT
;
1140 dst
[0] = ir3_MOV(b
, src
[0], TYPE_U32
);
1142 /* otherwise generate a max.f that saturates.. blob does
1143 * similar (generating a cat2 mov using max.f)
1145 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[0], 0);
1146 dst
[0]->flags
|= IR3_INSTR_SAT
;
1150 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
1153 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
1156 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
1159 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
1162 dst
[0] = ir3_DSX(b
, src
[0], 0);
1163 dst
[0]->cat5
.type
= TYPE_F32
;
1166 dst
[0] = ir3_DSY(b
, src
[0], 0);
1167 dst
[0]->cat5
.type
= TYPE_F32
;
1171 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1172 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1173 dst
[0] = ir3_n2b(b
, dst
[0]);
1176 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1177 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1178 dst
[0] = ir3_n2b(b
, dst
[0]);
1181 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1182 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1183 dst
[0] = ir3_n2b(b
, dst
[0]);
1186 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
1187 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1188 dst
[0] = ir3_n2b(b
, dst
[0]);
1191 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
1194 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
1197 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
1199 case nir_op_fround_even
:
1200 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
1203 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
1207 dst
[0] = ir3_SIN(b
, src
[0], 0);
1210 dst
[0] = ir3_COS(b
, src
[0], 0);
1213 dst
[0] = ir3_RSQ(b
, src
[0], 0);
1216 dst
[0] = ir3_RCP(b
, src
[0], 0);
1219 dst
[0] = ir3_LOG2(b
, src
[0], 0);
1222 dst
[0] = ir3_EXP2(b
, src
[0], 0);
1225 dst
[0] = ir3_SQRT(b
, src
[0], 0);
1229 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
1232 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
1235 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
1238 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
1241 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
1244 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
1247 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
1251 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
1252 * mull.u tmp0, a, b ; mul low, i.e. al * bl
1253 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
1254 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
1256 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
1257 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
1258 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
1261 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
1264 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
1267 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
1270 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
1273 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
1275 case nir_op_isign
: {
1276 /* maybe this would be sane to lower in nir.. */
1277 struct ir3_instruction
*neg
, *pos
;
1279 neg
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1280 neg
->cat2
.condition
= IR3_COND_LT
;
1282 pos
= ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
1283 pos
->cat2
.condition
= IR3_COND_GT
;
1285 dst
[0] = ir3_SUB_U(b
, pos
, 0, neg
, 0);
1290 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
1293 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
1296 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
1299 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1300 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1301 dst
[0] = ir3_n2b(b
, dst
[0]);
1304 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1305 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1306 dst
[0] = ir3_n2b(b
, dst
[0]);
1309 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1310 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1311 dst
[0] = ir3_n2b(b
, dst
[0]);
1314 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
1315 dst
[0]->cat2
.condition
= IR3_COND_NE
;
1316 dst
[0] = ir3_n2b(b
, dst
[0]);
1319 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1320 dst
[0]->cat2
.condition
= IR3_COND_LT
;
1321 dst
[0] = ir3_n2b(b
, dst
[0]);
1324 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
1325 dst
[0]->cat2
.condition
= IR3_COND_GE
;
1326 dst
[0] = ir3_n2b(b
, dst
[0]);
1329 case nir_op_bcsel
: {
1330 struct ir3_instruction
*cond
= ir3_b2n(b
, src
[0]);
1331 compile_assert(ctx
, bs
[1] == bs
[2]);
1332 /* the boolean condition is 32b even if src[1] and src[2] are
1333 * half-precision, but sel.b16 wants all three src's to be the
1337 cond
= ir3_COV(b
, cond
, TYPE_U32
, TYPE_U16
);
1338 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, cond
, 0, src
[2], 0);
1341 case nir_op_bit_count
:
1342 dst
[0] = ir3_CBITS_B(b
, src
[0], 0);
1344 case nir_op_ifind_msb
: {
1345 struct ir3_instruction
*cmp
;
1346 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
1347 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
1348 cmp
->cat2
.condition
= IR3_COND_GE
;
1349 dst
[0] = ir3_SEL_B32(b
,
1350 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1354 case nir_op_ufind_msb
:
1355 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
1356 dst
[0] = ir3_SEL_B32(b
,
1357 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
1358 src
[0], 0, dst
[0], 0);
1360 case nir_op_find_lsb
:
1361 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1362 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
1364 case nir_op_bitfield_reverse
:
1365 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
1369 compile_error(ctx
, "Unhandled ALU op: %s\n",
1370 nir_op_infos
[alu
->op
].name
);
1374 put_dst(ctx
, &alu
->dest
.dest
);
1377 /* handles direct/indirect UBO reads: */
1379 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1380 struct ir3_instruction
**dst
)
1382 struct ir3_block
*b
= ctx
->block
;
1383 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
1384 nir_const_value
*const_offset
;
1385 /* UBO addresses are the first driver params: */
1386 unsigned ubo
= regid(ctx
->so
->constbase
.ubo
, 0);
1387 const unsigned ptrsz
= pointer_size(ctx
);
1391 /* First src is ubo index, which could either be an immed or not: */
1392 src0
= get_src(ctx
, &intr
->src
[0])[0];
1393 if (is_same_type_mov(src0
) &&
1394 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
1395 base_lo
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
1396 base_hi
= create_uniform(ctx
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
1398 base_lo
= create_uniform_indirect(ctx
, ubo
, get_addr(ctx
, src0
, 4));
1399 base_hi
= create_uniform_indirect(ctx
, ubo
+ 1, get_addr(ctx
, src0
, 4));
1402 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
1405 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1407 off
+= const_offset
->u32
[0];
1409 /* For load_ubo_indirect, second src is indirect offset: */
1410 src1
= get_src(ctx
, &intr
->src
[1])[0];
1412 /* and add offset to addr: */
1413 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
1416 /* if offset is to large to encode in the ldg, split it out: */
1417 if ((off
+ (intr
->num_components
* 4)) > 1024) {
1418 /* split out the minimal amount to improve the odds that
1419 * cp can fit the immediate in the add.s instruction:
1421 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
1422 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
1427 struct ir3_instruction
*carry
;
1429 /* handle 32b rollover, ie:
1430 * if (addr < base_lo)
1433 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
1434 carry
->cat2
.condition
= IR3_COND_LT
;
1435 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
1437 addr
= create_collect(ctx
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
1440 for (int i
= 0; i
< intr
->num_components
; i
++) {
1441 struct ir3_instruction
*load
=
1442 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
1443 load
->cat6
.type
= TYPE_U32
;
1444 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
1449 /* src[] = { buffer_index, offset }. No const_index */
1451 emit_intrinsic_load_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1452 struct ir3_instruction
**dst
)
1454 struct ir3_block
*b
= ctx
->block
;
1455 struct ir3_instruction
*ldgb
, *src0
, *src1
, *offset
;
1456 nir_const_value
*const_offset
;
1458 /* can this be non-const buffer_index? how do we handle that? */
1459 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1460 compile_assert(ctx
, const_offset
);
1462 offset
= get_src(ctx
, &intr
->src
[1])[0];
1464 /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
1465 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
1469 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1471 ldgb
= ir3_LDGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1473 ldgb
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1474 ldgb
->cat6
.iim_val
= intr
->num_components
;
1476 ldgb
->cat6
.type
= TYPE_U32
;
1477 ldgb
->barrier_class
= IR3_BARRIER_BUFFER_R
;
1478 ldgb
->barrier_conflict
= IR3_BARRIER_BUFFER_W
;
1480 split_dest(b
, dst
, ldgb
, 0, intr
->num_components
);
1483 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
1485 emit_intrinsic_store_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1487 struct ir3_block
*b
= ctx
->block
;
1488 struct ir3_instruction
*stgb
, *src0
, *src1
, *src2
, *offset
;
1489 nir_const_value
*const_offset
;
1490 /* TODO handle wrmask properly, see _store_shared().. but I think
1491 * it is more a PITA than that, since blob ends up loading the
1492 * masked components and writing them back out.
1494 unsigned wrmask
= intr
->const_index
[0];
1495 unsigned ncomp
= ffs(~wrmask
) - 1;
1497 /* can this be non-const buffer_index? how do we handle that? */
1498 const_offset
= nir_src_as_const_value(intr
->src
[1]);
1499 compile_assert(ctx
, const_offset
);
1501 offset
= get_src(ctx
, &intr
->src
[2])[0];
1503 /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
1506 src0
= create_collect(ctx
, get_src(ctx
, &intr
->src
[0]), ncomp
);
1507 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1508 src2
= create_collect(ctx
, (struct ir3_instruction
*[]){
1513 stgb
= ir3_STGB(b
, create_immed(b
, const_offset
->u32
[0]), 0,
1514 src0
, 0, src1
, 0, src2
, 0);
1515 stgb
->cat6
.iim_val
= ncomp
;
1517 stgb
->cat6
.type
= TYPE_U32
;
1518 stgb
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1519 stgb
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1521 array_insert(b
, b
->keeps
, stgb
);
1524 /* src[] = { block_index } */
1526 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1527 struct ir3_instruction
**dst
)
1529 /* SSBO size stored as a const starting at ssbo_sizes: */
1530 unsigned blk_idx
= nir_src_as_const_value(intr
->src
[0])->u32
[0];
1531 unsigned idx
= regid(ctx
->so
->constbase
.ssbo_sizes
, 0) +
1532 ctx
->so
->const_layout
.ssbo_size
.off
[blk_idx
];
1534 debug_assert(ctx
->so
->const_layout
.ssbo_size
.mask
& (1 << blk_idx
));
1536 dst
[0] = create_uniform(ctx
, idx
);
1540 * SSBO atomic intrinsics
1542 * All of the SSBO atomic memory operations read a value from memory,
1543 * compute a new value using one of the operations below, write the new
1544 * value to memory, and return the original value read.
1546 * All operations take 3 sources except CompSwap that takes 4. These
1547 * sources represent:
1549 * 0: The SSBO buffer index.
1550 * 1: The offset into the SSBO buffer of the variable that the atomic
1551 * operation will operate on.
1552 * 2: The data parameter to the atomic function (i.e. the value to add
1553 * in ssbo_atomic_add, etc).
1554 * 3: For CompSwap only: the second data parameter.
1556 static struct ir3_instruction
*
1557 emit_intrinsic_atomic_ssbo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1559 struct ir3_block
*b
= ctx
->block
;
1560 struct ir3_instruction
*atomic
, *ssbo
, *src0
, *src1
, *src2
, *offset
;
1561 nir_const_value
*const_offset
;
1562 type_t type
= TYPE_U32
;
1564 /* can this be non-const buffer_index? how do we handle that? */
1565 const_offset
= nir_src_as_const_value(intr
->src
[0]);
1566 compile_assert(ctx
, const_offset
);
1567 ssbo
= create_immed(b
, const_offset
->u32
[0]);
1569 offset
= get_src(ctx
, &intr
->src
[1])[0];
1571 /* src0 is data (or uvec2(data, compare))
1573 * src2 is uvec2(offset*4, 0) (appears to be 64b byte offset)
1575 * Note that nir already multiplies the offset by four
1577 src0
= get_src(ctx
, &intr
->src
[2])[0];
1578 src1
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1579 src2
= create_collect(ctx
, (struct ir3_instruction
*[]){
1584 switch (intr
->intrinsic
) {
1585 case nir_intrinsic_ssbo_atomic_add
:
1586 atomic
= ir3_ATOMIC_ADD_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1588 case nir_intrinsic_ssbo_atomic_imin
:
1589 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1592 case nir_intrinsic_ssbo_atomic_umin
:
1593 atomic
= ir3_ATOMIC_MIN_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1595 case nir_intrinsic_ssbo_atomic_imax
:
1596 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1599 case nir_intrinsic_ssbo_atomic_umax
:
1600 atomic
= ir3_ATOMIC_MAX_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1602 case nir_intrinsic_ssbo_atomic_and
:
1603 atomic
= ir3_ATOMIC_AND_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1605 case nir_intrinsic_ssbo_atomic_or
:
1606 atomic
= ir3_ATOMIC_OR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1608 case nir_intrinsic_ssbo_atomic_xor
:
1609 atomic
= ir3_ATOMIC_XOR_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1611 case nir_intrinsic_ssbo_atomic_exchange
:
1612 atomic
= ir3_ATOMIC_XCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1614 case nir_intrinsic_ssbo_atomic_comp_swap
:
1615 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1616 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
1618 get_src(ctx
, &intr
->src
[3])[0],
1620 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, ssbo
, 0, src0
, 0, src1
, 0, src2
, 0);
1626 atomic
->cat6
.iim_val
= 1;
1628 atomic
->cat6
.type
= type
;
1629 atomic
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1630 atomic
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1632 /* even if nothing consume the result, we can't DCE the instruction: */
1633 array_insert(b
, b
->keeps
, atomic
);
1638 /* src[] = { offset }. const_index[] = { base } */
1640 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1641 struct ir3_instruction
**dst
)
1643 struct ir3_block
*b
= ctx
->block
;
1644 struct ir3_instruction
*ldl
, *offset
;
1647 offset
= get_src(ctx
, &intr
->src
[0])[0];
1648 base
= nir_intrinsic_base(intr
);
1650 ldl
= ir3_LDL(b
, offset
, 0, create_immed(b
, intr
->num_components
), 0);
1651 ldl
->cat6
.src_offset
= base
;
1652 ldl
->cat6
.type
= utype_dst(intr
->dest
);
1653 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1655 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
1656 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
1658 split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
1661 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
1663 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1665 struct ir3_block
*b
= ctx
->block
;
1666 struct ir3_instruction
*stl
, *offset
;
1667 struct ir3_instruction
* const *value
;
1668 unsigned base
, wrmask
;
1670 value
= get_src(ctx
, &intr
->src
[0]);
1671 offset
= get_src(ctx
, &intr
->src
[1])[0];
1673 base
= nir_intrinsic_base(intr
);
1674 wrmask
= nir_intrinsic_write_mask(intr
);
1676 /* Combine groups of consecutive enabled channels in one write
1677 * message. We use ffs to find the first enabled channel and then ffs on
1678 * the bit-inverse, down-shifted writemask to determine the length of
1679 * the block of enabled bits.
1681 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
1684 unsigned first_component
= ffs(wrmask
) - 1;
1685 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
1687 stl
= ir3_STL(b
, offset
, 0,
1688 create_collect(ctx
, &value
[first_component
], length
), 0,
1689 create_immed(b
, length
), 0);
1690 stl
->cat6
.dst_offset
= first_component
+ base
;
1691 stl
->cat6
.type
= utype_src(intr
->src
[0]);
1692 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
1693 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1695 array_insert(b
, b
->keeps
, stl
);
1697 /* Clear the bits in the writemask that we just wrote, then try
1698 * again to see if more channels are left.
1700 wrmask
&= (15 << (first_component
+ length
));
1705 * CS shared variable atomic intrinsics
1707 * All of the shared variable atomic memory operations read a value from
1708 * memory, compute a new value using one of the operations below, write the
1709 * new value to memory, and return the original value read.
1711 * All operations take 2 sources except CompSwap that takes 3. These
1712 * sources represent:
1714 * 0: The offset into the shared variable storage region that the atomic
1715 * operation will operate on.
1716 * 1: The data parameter to the atomic function (i.e. the value to add
1717 * in shared_atomic_add, etc).
1718 * 2: For CompSwap only: the second data parameter.
1720 static struct ir3_instruction
*
1721 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1723 struct ir3_block
*b
= ctx
->block
;
1724 struct ir3_instruction
*atomic
, *src0
, *src1
;
1725 type_t type
= TYPE_U32
;
1727 src0
= get_src(ctx
, &intr
->src
[0])[0]; /* offset */
1728 src1
= get_src(ctx
, &intr
->src
[1])[0]; /* value */
1730 switch (intr
->intrinsic
) {
1731 case nir_intrinsic_shared_atomic_add
:
1732 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
1734 case nir_intrinsic_shared_atomic_imin
:
1735 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1738 case nir_intrinsic_shared_atomic_umin
:
1739 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1741 case nir_intrinsic_shared_atomic_imax
:
1742 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1745 case nir_intrinsic_shared_atomic_umax
:
1746 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1748 case nir_intrinsic_shared_atomic_and
:
1749 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
1751 case nir_intrinsic_shared_atomic_or
:
1752 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
1754 case nir_intrinsic_shared_atomic_xor
:
1755 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
1757 case nir_intrinsic_shared_atomic_exchange
:
1758 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
1760 case nir_intrinsic_shared_atomic_comp_swap
:
1761 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1762 src1
= create_collect(ctx
, (struct ir3_instruction
*[]){
1763 get_src(ctx
, &intr
->src
[2])[0],
1766 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
1772 atomic
->cat6
.iim_val
= 1;
1774 atomic
->cat6
.type
= type
;
1775 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
1776 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1778 /* even if nothing consume the result, we can't DCE the instruction: */
1779 array_insert(b
, b
->keeps
, atomic
);
1784 /* Images get mapped into SSBO/image state (for store/atomic) and texture
1785 * state block (for load). To simplify things, invert the image id and
1786 * map it from end of state block, ie. image 0 becomes num-1, image 1
1787 * becomes num-2, etc. This potentially avoids needing to re-emit texture
1788 * state when switching shaders.
1790 * TODO is max # of samplers and SSBOs the same. This shouldn't be hard-
1791 * coded. Also, since all the gl shader stages (ie. everything but CS)
1792 * share the same SSBO/image state block, this might require some more
1793 * logic if we supported images in anything other than FS..
1796 get_image_slot(struct ir3_context
*ctx
, nir_deref_instr
*deref
)
1798 unsigned int loc
= 0;
1799 unsigned inner_size
= 1;
1801 while (deref
->deref_type
!= nir_deref_type_var
) {
1802 assert(deref
->deref_type
== nir_deref_type_array
);
1803 nir_const_value
*const_index
= nir_src_as_const_value(deref
->arr
.index
);
1804 assert(const_index
);
1806 /* Go to the next instruction */
1807 deref
= nir_deref_instr_parent(deref
);
1809 assert(glsl_type_is_array(deref
->type
));
1810 const unsigned array_len
= glsl_get_length(deref
->type
);
1811 loc
+= MIN2(const_index
->u32
[0], array_len
- 1) * inner_size
;
1813 /* Update the inner size */
1814 inner_size
*= array_len
;
1817 loc
+= deref
->var
->data
.driver_location
;
1819 /* TODO figure out real limit per generation, and don't hardcode: */
1820 const unsigned max_samplers
= 16;
1821 return max_samplers
- loc
- 1;
1824 /* see tex_info() for equiv logic for texture instructions.. it would be
1825 * nice if this could be better unified..
1828 get_image_coords(const nir_variable
*var
, unsigned *flagsp
)
1830 const struct glsl_type
*type
= glsl_without_array(var
->type
);
1831 unsigned coords
, flags
= 0;
1833 switch (glsl_get_sampler_dim(type
)) {
1834 case GLSL_SAMPLER_DIM_1D
:
1835 case GLSL_SAMPLER_DIM_BUF
:
1838 case GLSL_SAMPLER_DIM_2D
:
1839 case GLSL_SAMPLER_DIM_RECT
:
1840 case GLSL_SAMPLER_DIM_EXTERNAL
:
1841 case GLSL_SAMPLER_DIM_MS
:
1844 case GLSL_SAMPLER_DIM_3D
:
1845 case GLSL_SAMPLER_DIM_CUBE
:
1846 flags
|= IR3_INSTR_3D
;
1850 unreachable("bad sampler dim");
1854 if (glsl_sampler_type_is_array(type
)) {
1855 /* note: unlike tex_info(), adjust # of coords to include array idx: */
1857 flags
|= IR3_INSTR_A
;
1867 get_image_type(const nir_variable
*var
)
1869 switch (glsl_get_sampler_result_type(glsl_without_array(var
->type
))) {
1870 case GLSL_TYPE_UINT
:
1874 case GLSL_TYPE_FLOAT
:
1877 unreachable("bad sampler type.");
1882 static struct ir3_instruction
*
1883 get_image_offset(struct ir3_context
*ctx
, const nir_variable
*var
,
1884 struct ir3_instruction
* const *coords
, bool byteoff
)
1886 struct ir3_block
*b
= ctx
->block
;
1887 struct ir3_instruction
*offset
;
1888 unsigned ncoords
= get_image_coords(var
, NULL
);
1890 /* to calculate the byte offset (yes, uggg) we need (up to) three
1891 * const values to know the bytes per pixel, and y and z stride:
1893 unsigned cb
= regid(ctx
->so
->constbase
.image_dims
, 0) +
1894 ctx
->so
->const_layout
.image_dims
.off
[var
->data
.driver_location
];
1896 debug_assert(ctx
->so
->const_layout
.image_dims
.mask
&
1897 (1 << var
->data
.driver_location
));
1899 /* offset = coords.x * bytes_per_pixel: */
1900 offset
= ir3_MUL_S(b
, coords
[0], 0, create_uniform(ctx
, cb
+ 0), 0);
1902 /* offset += coords.y * y_pitch: */
1903 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 1), 0,
1904 coords
[1], 0, offset
, 0);
1907 /* offset += coords.z * z_pitch: */
1908 offset
= ir3_MAD_S24(b
, create_uniform(ctx
, cb
+ 2), 0,
1909 coords
[2], 0, offset
, 0);
1913 /* Some cases, like atomics, seem to use dword offset instead
1914 * of byte offsets.. blob just puts an extra shr.b in there
1917 offset
= ir3_SHR_B(b
, offset
, 0, create_immed(b
, 2), 0);
1920 return create_collect(ctx
, (struct ir3_instruction
*[]){
1926 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1928 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1929 struct ir3_instruction
**dst
)
1931 struct ir3_block
*b
= ctx
->block
;
1932 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
1933 struct ir3_instruction
*sam
;
1934 struct ir3_instruction
* const *src0
= get_src(ctx
, &intr
->src
[1]);
1935 struct ir3_instruction
*coords
[4];
1936 unsigned flags
, ncoords
= get_image_coords(var
, &flags
);
1937 unsigned tex_idx
= get_image_slot(ctx
, nir_src_as_deref(intr
->src
[0]));
1938 type_t type
= get_image_type(var
);
1940 /* hmm, this seems a bit odd, but it is what blob does and (at least
1941 * a5xx) just faults on bogus addresses otherwise:
1943 if (flags
& IR3_INSTR_3D
) {
1944 flags
&= ~IR3_INSTR_3D
;
1945 flags
|= IR3_INSTR_A
;
1948 for (unsigned i
= 0; i
< ncoords
; i
++)
1949 coords
[i
] = src0
[i
];
1952 coords
[ncoords
++] = create_immed(b
, 0);
1954 sam
= ir3_SAM(b
, OPC_ISAM
, type
, TGSI_WRITEMASK_XYZW
, flags
,
1955 tex_idx
, tex_idx
, create_collect(ctx
, coords
, ncoords
), NULL
);
1957 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
1958 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
1960 split_dest(b
, dst
, sam
, 0, 4);
1963 /* src[] = { deref, coord, sample_index, value }. const_index[] = {} */
1965 emit_intrinsic_store_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1967 struct ir3_block
*b
= ctx
->block
;
1968 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
1969 struct ir3_instruction
*stib
, *offset
;
1970 struct ir3_instruction
* const *value
= get_src(ctx
, &intr
->src
[3]);
1971 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[1]);
1972 unsigned ncoords
= get_image_coords(var
, NULL
);
1973 unsigned tex_idx
= get_image_slot(ctx
, nir_src_as_deref(intr
->src
[0]));
1977 * src2 is 64b byte offset
1980 offset
= get_image_offset(ctx
, var
, coords
, true);
1982 /* NOTE: stib seems to take byte offset, but stgb.typed can be used
1983 * too and takes a dword offset.. not quite sure yet why blob uses
1984 * one over the other in various cases.
1987 stib
= ir3_STIB(b
, create_immed(b
, tex_idx
), 0,
1988 create_collect(ctx
, value
, 4), 0,
1989 create_collect(ctx
, coords
, ncoords
), 0,
1991 stib
->cat6
.iim_val
= 4;
1992 stib
->cat6
.d
= ncoords
;
1993 stib
->cat6
.type
= get_image_type(var
);
1994 stib
->cat6
.typed
= true;
1995 stib
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1996 stib
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
1998 array_insert(b
, b
->keeps
, stib
);
2002 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
2003 struct ir3_instruction
**dst
)
2005 struct ir3_block
*b
= ctx
->block
;
2006 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
2007 unsigned tex_idx
= get_image_slot(ctx
, nir_src_as_deref(intr
->src
[0]));
2008 struct ir3_instruction
*sam
, *lod
;
2009 unsigned flags
, ncoords
= get_image_coords(var
, &flags
);
2011 lod
= create_immed(b
, 0);
2012 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
2013 tex_idx
, tex_idx
, lod
, NULL
);
2015 /* Array size actually ends up in .w rather than .z. This doesn't
2016 * matter for miplevel 0, but for higher mips the value in z is
2017 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2018 * returned, which means that we have to add 1 to it for arrays for
2021 * Note use a temporary dst and then copy, since the size of the dst
2022 * array that is passed in is based on nir's understanding of the
2023 * result size, not the hardware's
2025 struct ir3_instruction
*tmp
[4];
2027 split_dest(b
, tmp
, sam
, 0, 4);
2029 for (unsigned i
= 0; i
< ncoords
; i
++)
2032 if (flags
& IR3_INSTR_A
) {
2033 if (ctx
->compiler
->levels_add_one
) {
2034 dst
[ncoords
-1] = ir3_ADD_U(b
, tmp
[3], 0, create_immed(b
, 1), 0);
2036 dst
[ncoords
-1] = ir3_MOV(b
, tmp
[3], TYPE_U32
);
2041 /* src[] = { deref, coord, sample_index, value, compare }. const_index[] = {} */
2042 static struct ir3_instruction
*
2043 emit_intrinsic_atomic_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2045 struct ir3_block
*b
= ctx
->block
;
2046 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
2047 struct ir3_instruction
*atomic
, *image
, *src0
, *src1
, *src2
;
2048 struct ir3_instruction
* const *coords
= get_src(ctx
, &intr
->src
[1]);
2049 unsigned ncoords
= get_image_coords(var
, NULL
);
2051 image
= create_immed(b
, get_image_slot(ctx
, nir_src_as_deref(intr
->src
[0])));
2053 /* src0 is value (or uvec2(value, compare))
2055 * src2 is 64b byte offset
2057 src0
= get_src(ctx
, &intr
->src
[3])[0];
2058 src1
= create_collect(ctx
, coords
, ncoords
);
2059 src2
= get_image_offset(ctx
, var
, coords
, false);
2061 switch (intr
->intrinsic
) {
2062 case nir_intrinsic_image_deref_atomic_add
:
2063 atomic
= ir3_ATOMIC_ADD_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2065 case nir_intrinsic_image_deref_atomic_min
:
2066 atomic
= ir3_ATOMIC_MIN_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2068 case nir_intrinsic_image_deref_atomic_max
:
2069 atomic
= ir3_ATOMIC_MAX_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2071 case nir_intrinsic_image_deref_atomic_and
:
2072 atomic
= ir3_ATOMIC_AND_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2074 case nir_intrinsic_image_deref_atomic_or
:
2075 atomic
= ir3_ATOMIC_OR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2077 case nir_intrinsic_image_deref_atomic_xor
:
2078 atomic
= ir3_ATOMIC_XOR_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2080 case nir_intrinsic_image_deref_atomic_exchange
:
2081 atomic
= ir3_ATOMIC_XCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2083 case nir_intrinsic_image_deref_atomic_comp_swap
:
2084 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
2085 src0
= create_collect(ctx
, (struct ir3_instruction
*[]){
2087 get_src(ctx
, &intr
->src
[4])[0],
2089 atomic
= ir3_ATOMIC_CMPXCHG_G(b
, image
, 0, src0
, 0, src1
, 0, src2
, 0);
2095 atomic
->cat6
.iim_val
= 1;
2096 atomic
->cat6
.d
= ncoords
;
2097 atomic
->cat6
.type
= get_image_type(var
);
2098 atomic
->cat6
.typed
= true;
2099 atomic
->barrier_class
= IR3_BARRIER_IMAGE_W
;
2100 atomic
->barrier_conflict
= IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
;
2102 /* even if nothing consume the result, we can't DCE the instruction: */
2103 array_insert(b
, b
->keeps
, atomic
);
2109 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2111 struct ir3_block
*b
= ctx
->block
;
2112 struct ir3_instruction
*barrier
;
2114 switch (intr
->intrinsic
) {
2115 case nir_intrinsic_barrier
:
2116 barrier
= ir3_BAR(b
);
2117 barrier
->cat7
.g
= true;
2118 barrier
->cat7
.l
= true;
2119 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
2120 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2122 case nir_intrinsic_memory_barrier
:
2123 barrier
= ir3_FENCE(b
);
2124 barrier
->cat7
.g
= true;
2125 barrier
->cat7
.r
= true;
2126 barrier
->cat7
.w
= true;
2127 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
2128 IR3_BARRIER_BUFFER_W
;
2129 barrier
->barrier_conflict
=
2130 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
2131 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
2133 case nir_intrinsic_memory_barrier_atomic_counter
:
2134 case nir_intrinsic_memory_barrier_buffer
:
2135 barrier
= ir3_FENCE(b
);
2136 barrier
->cat7
.g
= true;
2137 barrier
->cat7
.r
= true;
2138 barrier
->cat7
.w
= true;
2139 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
2140 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
2141 IR3_BARRIER_BUFFER_W
;
2143 case nir_intrinsic_memory_barrier_image
:
2144 // TODO double check if this should have .g set
2145 barrier
= ir3_FENCE(b
);
2146 barrier
->cat7
.g
= true;
2147 barrier
->cat7
.r
= true;
2148 barrier
->cat7
.w
= true;
2149 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
2150 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
2151 IR3_BARRIER_IMAGE_W
;
2153 case nir_intrinsic_memory_barrier_shared
:
2154 barrier
= ir3_FENCE(b
);
2155 barrier
->cat7
.g
= true;
2156 barrier
->cat7
.l
= true;
2157 barrier
->cat7
.r
= true;
2158 barrier
->cat7
.w
= true;
2159 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
2160 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
2161 IR3_BARRIER_SHARED_W
;
2163 case nir_intrinsic_group_memory_barrier
:
2164 barrier
= ir3_FENCE(b
);
2165 barrier
->cat7
.g
= true;
2166 barrier
->cat7
.l
= true;
2167 barrier
->cat7
.r
= true;
2168 barrier
->cat7
.w
= true;
2169 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
2170 IR3_BARRIER_IMAGE_W
|
2171 IR3_BARRIER_BUFFER_W
;
2172 barrier
->barrier_conflict
=
2173 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
2174 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
2175 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
2181 /* make sure barrier doesn't get DCE'd */
2182 array_insert(b
, b
->keeps
, barrier
);
2185 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
2186 gl_system_value slot
, unsigned compmask
,
2187 struct ir3_instruction
*instr
)
2189 struct ir3_shader_variant
*so
= ctx
->so
;
2190 unsigned r
= regid(so
->inputs_count
, 0);
2191 unsigned n
= so
->inputs_count
++;
2193 so
->inputs
[n
].sysval
= true;
2194 so
->inputs
[n
].slot
= slot
;
2195 so
->inputs
[n
].compmask
= compmask
;
2196 so
->inputs
[n
].regid
= r
;
2197 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
2200 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
2201 ctx
->ir
->inputs
[r
] = instr
;
2204 static void add_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
2205 struct ir3_instruction
*instr
)
2207 add_sysval_input_compmask(ctx
, slot
, 0x1, instr
);
2211 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
2213 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
2214 struct ir3_instruction
**dst
;
2215 struct ir3_instruction
* const *src
;
2216 struct ir3_block
*b
= ctx
->block
;
2217 nir_const_value
*const_offset
;
2220 if (info
->has_dest
) {
2221 unsigned n
= nir_intrinsic_dest_components(intr
);
2222 dst
= get_dst(ctx
, &intr
->dest
, n
);
2227 switch (intr
->intrinsic
) {
2228 case nir_intrinsic_load_uniform
:
2229 idx
= nir_intrinsic_base(intr
);
2230 const_offset
= nir_src_as_const_value(intr
->src
[0]);
2232 idx
+= const_offset
->u32
[0];
2233 for (int i
= 0; i
< intr
->num_components
; i
++) {
2234 unsigned n
= idx
* 4 + i
;
2235 dst
[i
] = create_uniform(ctx
, n
);
2238 src
= get_src(ctx
, &intr
->src
[0]);
2239 for (int i
= 0; i
< intr
->num_components
; i
++) {
2240 int n
= idx
* 4 + i
;
2241 dst
[i
] = create_uniform_indirect(ctx
, n
,
2242 get_addr(ctx
, src
[0], 4));
2244 /* NOTE: if relative addressing is used, we set
2245 * constlen in the compiler (to worst-case value)
2246 * since we don't know in the assembler what the max
2247 * addr reg value can be:
2249 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
2252 case nir_intrinsic_load_ubo
:
2253 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
2255 case nir_intrinsic_load_input
:
2256 idx
= nir_intrinsic_base(intr
);
2257 comp
= nir_intrinsic_component(intr
);
2258 const_offset
= nir_src_as_const_value(intr
->src
[0]);
2260 idx
+= const_offset
->u32
[0];
2261 for (int i
= 0; i
< intr
->num_components
; i
++) {
2262 unsigned n
= idx
* 4 + i
+ comp
;
2263 dst
[i
] = ctx
->ir
->inputs
[n
];
2266 src
= get_src(ctx
, &intr
->src
[0]);
2267 struct ir3_instruction
*collect
=
2268 create_collect(ctx
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
2269 struct ir3_instruction
*addr
= get_addr(ctx
, src
[0], 4);
2270 for (int i
= 0; i
< intr
->num_components
; i
++) {
2271 unsigned n
= idx
* 4 + i
+ comp
;
2272 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
2277 case nir_intrinsic_load_ssbo
:
2278 emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
2280 case nir_intrinsic_store_ssbo
:
2281 emit_intrinsic_store_ssbo(ctx
, intr
);
2283 case nir_intrinsic_get_buffer_size
:
2284 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
2286 case nir_intrinsic_ssbo_atomic_add
:
2287 case nir_intrinsic_ssbo_atomic_imin
:
2288 case nir_intrinsic_ssbo_atomic_umin
:
2289 case nir_intrinsic_ssbo_atomic_imax
:
2290 case nir_intrinsic_ssbo_atomic_umax
:
2291 case nir_intrinsic_ssbo_atomic_and
:
2292 case nir_intrinsic_ssbo_atomic_or
:
2293 case nir_intrinsic_ssbo_atomic_xor
:
2294 case nir_intrinsic_ssbo_atomic_exchange
:
2295 case nir_intrinsic_ssbo_atomic_comp_swap
:
2296 dst
[0] = emit_intrinsic_atomic_ssbo(ctx
, intr
);
2298 case nir_intrinsic_load_shared
:
2299 emit_intrinsic_load_shared(ctx
, intr
, dst
);
2301 case nir_intrinsic_store_shared
:
2302 emit_intrinsic_store_shared(ctx
, intr
);
2304 case nir_intrinsic_shared_atomic_add
:
2305 case nir_intrinsic_shared_atomic_imin
:
2306 case nir_intrinsic_shared_atomic_umin
:
2307 case nir_intrinsic_shared_atomic_imax
:
2308 case nir_intrinsic_shared_atomic_umax
:
2309 case nir_intrinsic_shared_atomic_and
:
2310 case nir_intrinsic_shared_atomic_or
:
2311 case nir_intrinsic_shared_atomic_xor
:
2312 case nir_intrinsic_shared_atomic_exchange
:
2313 case nir_intrinsic_shared_atomic_comp_swap
:
2314 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
2316 case nir_intrinsic_image_deref_load
:
2317 emit_intrinsic_load_image(ctx
, intr
, dst
);
2319 case nir_intrinsic_image_deref_store
:
2320 emit_intrinsic_store_image(ctx
, intr
);
2322 case nir_intrinsic_image_deref_size
:
2323 emit_intrinsic_image_size(ctx
, intr
, dst
);
2325 case nir_intrinsic_image_deref_atomic_add
:
2326 case nir_intrinsic_image_deref_atomic_min
:
2327 case nir_intrinsic_image_deref_atomic_max
:
2328 case nir_intrinsic_image_deref_atomic_and
:
2329 case nir_intrinsic_image_deref_atomic_or
:
2330 case nir_intrinsic_image_deref_atomic_xor
:
2331 case nir_intrinsic_image_deref_atomic_exchange
:
2332 case nir_intrinsic_image_deref_atomic_comp_swap
:
2333 dst
[0] = emit_intrinsic_atomic_image(ctx
, intr
);
2335 case nir_intrinsic_barrier
:
2336 case nir_intrinsic_memory_barrier
:
2337 case nir_intrinsic_group_memory_barrier
:
2338 case nir_intrinsic_memory_barrier_atomic_counter
:
2339 case nir_intrinsic_memory_barrier_buffer
:
2340 case nir_intrinsic_memory_barrier_image
:
2341 case nir_intrinsic_memory_barrier_shared
:
2342 emit_intrinsic_barrier(ctx
, intr
);
2343 /* note that blk ptr no longer valid, make that obvious: */
2346 case nir_intrinsic_store_output
:
2347 idx
= nir_intrinsic_base(intr
);
2348 comp
= nir_intrinsic_component(intr
);
2349 const_offset
= nir_src_as_const_value(intr
->src
[1]);
2350 compile_assert(ctx
, const_offset
!= NULL
);
2351 idx
+= const_offset
->u32
[0];
2353 src
= get_src(ctx
, &intr
->src
[0]);
2354 for (int i
= 0; i
< intr
->num_components
; i
++) {
2355 unsigned n
= idx
* 4 + i
+ comp
;
2356 ctx
->ir
->outputs
[n
] = src
[i
];
2359 case nir_intrinsic_load_base_vertex
:
2360 case nir_intrinsic_load_first_vertex
:
2361 if (!ctx
->basevertex
) {
2362 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
2363 add_sysval_input(ctx
, SYSTEM_VALUE_FIRST_VERTEX
, ctx
->basevertex
);
2365 dst
[0] = ctx
->basevertex
;
2367 case nir_intrinsic_load_vertex_id_zero_base
:
2368 case nir_intrinsic_load_vertex_id
:
2369 if (!ctx
->vertex_id
) {
2370 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
2371 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
2372 ctx
->vertex_id
= create_input(ctx
, 0);
2373 add_sysval_input(ctx
, sv
, ctx
->vertex_id
);
2375 dst
[0] = ctx
->vertex_id
;
2377 case nir_intrinsic_load_instance_id
:
2378 if (!ctx
->instance_id
) {
2379 ctx
->instance_id
= create_input(ctx
, 0);
2380 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
2383 dst
[0] = ctx
->instance_id
;
2385 case nir_intrinsic_load_sample_id
:
2386 case nir_intrinsic_load_sample_id_no_per_sample
:
2387 if (!ctx
->samp_id
) {
2388 ctx
->samp_id
= create_input(ctx
, 0);
2389 ctx
->samp_id
->regs
[0]->flags
|= IR3_REG_HALF
;
2390 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_ID
,
2393 dst
[0] = ir3_COV(b
, ctx
->samp_id
, TYPE_U16
, TYPE_U32
);
2395 case nir_intrinsic_load_sample_mask_in
:
2396 if (!ctx
->samp_mask_in
) {
2397 ctx
->samp_mask_in
= create_input(ctx
, 0);
2398 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_MASK_IN
,
2401 dst
[0] = ctx
->samp_mask_in
;
2403 case nir_intrinsic_load_user_clip_plane
:
2404 idx
= nir_intrinsic_ucp_id(intr
);
2405 for (int i
= 0; i
< intr
->num_components
; i
++) {
2406 unsigned n
= idx
* 4 + i
;
2407 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
2410 case nir_intrinsic_load_front_face
:
2411 if (!ctx
->frag_face
) {
2412 ctx
->so
->frag_face
= true;
2413 ctx
->frag_face
= create_input(ctx
, 0);
2414 add_sysval_input(ctx
, SYSTEM_VALUE_FRONT_FACE
, ctx
->frag_face
);
2415 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
2417 /* for fragface, we get -1 for back and 0 for front. However this is
2418 * the inverse of what nir expects (where ~0 is true).
2420 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
2421 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
2423 case nir_intrinsic_load_local_invocation_id
:
2424 if (!ctx
->local_invocation_id
) {
2425 ctx
->local_invocation_id
= create_input_compmask(ctx
, 0, 0x7);
2426 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
,
2427 0x7, ctx
->local_invocation_id
);
2429 split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
2431 case nir_intrinsic_load_work_group_id
:
2432 if (!ctx
->work_group_id
) {
2433 ctx
->work_group_id
= create_input_compmask(ctx
, 0, 0x7);
2434 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
,
2435 0x7, ctx
->work_group_id
);
2436 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
2438 split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
2440 case nir_intrinsic_load_num_work_groups
:
2441 for (int i
= 0; i
< intr
->num_components
; i
++) {
2442 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
2445 case nir_intrinsic_load_local_group_size
:
2446 for (int i
= 0; i
< intr
->num_components
; i
++) {
2447 dst
[i
] = create_driver_param(ctx
, IR3_DP_LOCAL_GROUP_SIZE_X
+ i
);
2450 case nir_intrinsic_discard_if
:
2451 case nir_intrinsic_discard
: {
2452 struct ir3_instruction
*cond
, *kill
;
2454 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
2455 /* conditional discard: */
2456 src
= get_src(ctx
, &intr
->src
[0]);
2457 cond
= ir3_b2n(b
, src
[0]);
2459 /* unconditional discard: */
2460 cond
= create_immed(b
, 1);
2463 /* NOTE: only cmps.*.* can write p0.x: */
2464 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
2465 cond
->cat2
.condition
= IR3_COND_NE
;
2467 /* condition always goes in predicate register: */
2468 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2470 kill
= ir3_KILL(b
, cond
, 0);
2471 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
2473 array_insert(b
, b
->keeps
, kill
);
2474 ctx
->so
->has_kill
= true;
2479 compile_error(ctx
, "Unhandled intrinsic type: %s\n",
2480 nir_intrinsic_infos
[intr
->intrinsic
].name
);
2485 put_dst(ctx
, &intr
->dest
);
2489 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
2491 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &instr
->def
,
2492 instr
->def
.num_components
);
2493 type_t type
= (instr
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
2495 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
2496 dst
[i
] = create_immed_typed(ctx
->block
, instr
->value
.u32
[i
], type
);
2500 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
2502 struct ir3_instruction
**dst
= get_dst_ssa(ctx
, &undef
->def
,
2503 undef
->def
.num_components
);
2504 type_t type
= (undef
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
2506 /* backend doesn't want undefined instructions, so just plug
2509 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
2510 dst
[i
] = create_immed_typed(ctx
->block
, fui(0.0), type
);
2514 * texture fetch/sample instructions:
2518 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
2520 unsigned coords
, flags
= 0;
2522 /* note: would use tex->coord_components.. except txs.. also,
2523 * since array index goes after shadow ref, we don't want to
2526 switch (tex
->sampler_dim
) {
2527 case GLSL_SAMPLER_DIM_1D
:
2528 case GLSL_SAMPLER_DIM_BUF
:
2531 case GLSL_SAMPLER_DIM_2D
:
2532 case GLSL_SAMPLER_DIM_RECT
:
2533 case GLSL_SAMPLER_DIM_EXTERNAL
:
2534 case GLSL_SAMPLER_DIM_MS
:
2537 case GLSL_SAMPLER_DIM_3D
:
2538 case GLSL_SAMPLER_DIM_CUBE
:
2540 flags
|= IR3_INSTR_3D
;
2543 unreachable("bad sampler_dim");
2546 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2547 flags
|= IR3_INSTR_S
;
2549 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
2550 flags
|= IR3_INSTR_A
;
2557 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2559 struct ir3_block
*b
= ctx
->block
;
2560 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
2561 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
2562 struct ir3_instruction
*lod
, *compare
, *proj
, *sample_index
;
2563 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
2564 unsigned i
, coords
, flags
;
2565 unsigned nsrc0
= 0, nsrc1
= 0;
2569 coord
= off
= ddx
= ddy
= NULL
;
2570 lod
= proj
= compare
= sample_index
= NULL
;
2572 /* TODO: might just be one component for gathers? */
2573 dst
= get_dst(ctx
, &tex
->dest
, 4);
2575 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
2576 switch (tex
->src
[i
].src_type
) {
2577 case nir_tex_src_coord
:
2578 coord
= get_src(ctx
, &tex
->src
[i
].src
);
2580 case nir_tex_src_bias
:
2581 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2584 case nir_tex_src_lod
:
2585 lod
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2588 case nir_tex_src_comparator
: /* shadow comparator */
2589 compare
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2591 case nir_tex_src_projector
:
2592 proj
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2595 case nir_tex_src_offset
:
2596 off
= get_src(ctx
, &tex
->src
[i
].src
);
2599 case nir_tex_src_ddx
:
2600 ddx
= get_src(ctx
, &tex
->src
[i
].src
);
2602 case nir_tex_src_ddy
:
2603 ddy
= get_src(ctx
, &tex
->src
[i
].src
);
2605 case nir_tex_src_ms_index
:
2606 sample_index
= get_src(ctx
, &tex
->src
[i
].src
)[0];
2609 compile_error(ctx
, "Unhandled NIR tex src type: %d\n",
2610 tex
->src
[i
].src_type
);
2616 case nir_texop_tex
: opc
= has_lod
? OPC_SAML
: OPC_SAM
; break;
2617 case nir_texop_txb
: opc
= OPC_SAMB
; break;
2618 case nir_texop_txl
: opc
= OPC_SAML
; break;
2619 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
2620 case nir_texop_txf
: opc
= OPC_ISAML
; break;
2621 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
2623 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2624 * what blob does, seems gather is broken?), and a3xx did
2625 * not support it (but probably could also emulate).
2627 switch (tex
->component
) {
2628 case 0: opc
= OPC_GATHER4R
; break;
2629 case 1: opc
= OPC_GATHER4G
; break;
2630 case 2: opc
= OPC_GATHER4B
; break;
2631 case 3: opc
= OPC_GATHER4A
; break;
2634 case nir_texop_txf_ms
: opc
= OPC_ISAMM
; break;
2636 case nir_texop_query_levels
:
2637 case nir_texop_texture_samples
:
2638 case nir_texop_samples_identical
:
2639 case nir_texop_txf_ms_mcs
:
2640 compile_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
2644 tex_info(tex
, &flags
, &coords
);
2647 * lay out the first argument in the proper order:
2648 * - actual coordinates first
2649 * - shadow reference
2652 * - starting at offset 4, dpdx.xy, dpdy.xy
2654 * bias/lod go into the second arg
2657 /* insert tex coords: */
2658 for (i
= 0; i
< coords
; i
++)
2663 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2664 * with scaled x coord according to requested sample:
2666 if (tex
->op
== nir_texop_txf_ms
) {
2667 if (ctx
->compiler
->txf_ms_with_isaml
) {
2668 /* the samples are laid out in x dimension as
2670 * x_ms = (x << ms) + sample_index;
2672 struct ir3_instruction
*ms
;
2673 ms
= create_immed(b
, (ctx
->samples
>> (2 * tex
->texture_index
)) & 3);
2675 src0
[0] = ir3_SHL_B(b
, src0
[0], 0, ms
, 0);
2676 src0
[0] = ir3_ADD_U(b
, src0
[0], 0, sample_index
, 0);
2680 src0
[nsrc0
++] = sample_index
;
2684 /* scale up integer coords for TXF based on the LOD */
2685 if (ctx
->compiler
->unminify_coords
&& (opc
== OPC_ISAML
)) {
2687 for (i
= 0; i
< coords
; i
++)
2688 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
2692 /* hw doesn't do 1d, so we treat it as 2d with
2693 * height of 1, and patch up the y coord.
2694 * TODO: y coord should be (int)0 in some cases..
2696 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
2699 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2700 src0
[nsrc0
++] = compare
;
2702 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
2703 struct ir3_instruction
*idx
= coord
[coords
];
2705 /* the array coord for cube arrays needs 0.5 added to it */
2706 if (ctx
->compiler
->array_index_add_half
&& (opc
!= OPC_ISAML
))
2707 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
2709 src0
[nsrc0
++] = idx
;
2713 src0
[nsrc0
++] = proj
;
2714 flags
|= IR3_INSTR_P
;
2717 /* pad to 4, then ddx/ddy: */
2718 if (tex
->op
== nir_texop_txd
) {
2720 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2721 for (i
= 0; i
< coords
; i
++)
2722 src0
[nsrc0
++] = ddx
[i
];
2724 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2725 for (i
= 0; i
< coords
; i
++)
2726 src0
[nsrc0
++] = ddy
[i
];
2728 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2732 * second argument (if applicable):
2737 if (has_off
| has_lod
| has_bias
) {
2739 unsigned off_coords
= coords
;
2740 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2742 for (i
= 0; i
< off_coords
; i
++)
2743 src1
[nsrc1
++] = off
[i
];
2745 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
2746 flags
|= IR3_INSTR_O
;
2749 if (has_lod
| has_bias
)
2750 src1
[nsrc1
++] = lod
;
2753 switch (tex
->dest_type
) {
2754 case nir_type_invalid
:
2755 case nir_type_float
:
2766 unreachable("bad dest_type");
2769 if (opc
== OPC_GETLOD
)
2772 unsigned tex_idx
= tex
->texture_index
;
2774 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex_idx
);
2776 struct ir3_instruction
*col0
= create_collect(ctx
, src0
, nsrc0
);
2777 struct ir3_instruction
*col1
= create_collect(ctx
, src1
, nsrc1
);
2779 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_XYZW
, flags
,
2780 tex_idx
, tex_idx
, col0
, col1
);
2782 if ((ctx
->astc_srgb
& (1 << tex_idx
)) && !nir_tex_instr_is_query(tex
)) {
2783 /* only need first 3 components: */
2784 sam
->regs
[0]->wrmask
= 0x7;
2785 split_dest(b
, dst
, sam
, 0, 3);
2787 /* we need to sample the alpha separately with a non-ASTC
2790 sam
= ir3_SAM(b
, opc
, type
, TGSI_WRITEMASK_W
, flags
,
2791 tex_idx
, tex_idx
, col0
, col1
);
2793 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2795 /* fixup .w component: */
2796 split_dest(b
, &dst
[3], sam
, 3, 1);
2798 /* normal (non-workaround) case: */
2799 split_dest(b
, dst
, sam
, 0, 4);
2802 /* GETLOD returns results in 4.8 fixed point */
2803 if (opc
== OPC_GETLOD
) {
2804 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2806 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2807 for (i
= 0; i
< 2; i
++) {
2808 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
2813 put_dst(ctx
, &tex
->dest
);
2817 emit_tex_query_levels(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2819 struct ir3_block
*b
= ctx
->block
;
2820 struct ir3_instruction
**dst
, *sam
;
2822 dst
= get_dst(ctx
, &tex
->dest
, 1);
2824 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, TGSI_WRITEMASK_Z
, 0,
2825 tex
->texture_index
, tex
->texture_index
, NULL
, NULL
);
2827 /* even though there is only one component, since it ends
2828 * up in .z rather than .x, we need a split_dest()
2830 split_dest(b
, dst
, sam
, 0, 3);
2832 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2833 * the value in TEX_CONST_0 is zero-based.
2835 if (ctx
->compiler
->levels_add_one
)
2836 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2838 put_dst(ctx
, &tex
->dest
);
2842 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2844 struct ir3_block
*b
= ctx
->block
;
2845 struct ir3_instruction
**dst
, *sam
;
2846 struct ir3_instruction
*lod
;
2847 unsigned flags
, coords
;
2849 tex_info(tex
, &flags
, &coords
);
2851 /* Actually we want the number of dimensions, not coordinates. This
2852 * distinction only matters for cubes.
2854 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2857 dst
= get_dst(ctx
, &tex
->dest
, 4);
2859 compile_assert(ctx
, tex
->num_srcs
== 1);
2860 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
2862 lod
= get_src(ctx
, &tex
->src
[0].src
)[0];
2864 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, TGSI_WRITEMASK_XYZW
, flags
,
2865 tex
->texture_index
, tex
->texture_index
, lod
, NULL
);
2867 split_dest(b
, dst
, sam
, 0, 4);
2869 /* Array size actually ends up in .w rather than .z. This doesn't
2870 * matter for miplevel 0, but for higher mips the value in z is
2871 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2872 * returned, which means that we have to add 1 to it for arrays.
2874 if (tex
->is_array
) {
2875 if (ctx
->compiler
->levels_add_one
) {
2876 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2878 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2882 put_dst(ctx
, &tex
->dest
);
2886 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2888 switch (jump
->type
) {
2889 case nir_jump_break
:
2890 case nir_jump_continue
:
2891 case nir_jump_return
:
2892 /* I *think* we can simply just ignore this, and use the
2893 * successor block link to figure out where we need to
2894 * jump to for break/continue
2898 compile_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2904 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2906 switch (instr
->type
) {
2907 case nir_instr_type_alu
:
2908 emit_alu(ctx
, nir_instr_as_alu(instr
));
2910 case nir_instr_type_deref
:
2911 /* ignored, handled as part of the intrinsic they are src to */
2913 case nir_instr_type_intrinsic
:
2914 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2916 case nir_instr_type_load_const
:
2917 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2919 case nir_instr_type_ssa_undef
:
2920 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2922 case nir_instr_type_tex
: {
2923 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2924 /* couple tex instructions get special-cased:
2928 emit_tex_txs(ctx
, tex
);
2930 case nir_texop_query_levels
:
2931 emit_tex_query_levels(ctx
, tex
);
2939 case nir_instr_type_jump
:
2940 emit_jump(ctx
, nir_instr_as_jump(instr
));
2942 case nir_instr_type_phi
:
2943 /* we have converted phi webs to regs in NIR by now */
2944 compile_error(ctx
, "Unexpected NIR instruction type: %d\n", instr
->type
);
2946 case nir_instr_type_call
:
2947 case nir_instr_type_parallel_copy
:
2948 compile_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2953 static struct ir3_block
*
2954 get_block(struct ir3_context
*ctx
, const nir_block
*nblock
)
2956 struct ir3_block
*block
;
2957 struct hash_entry
*hentry
;
2958 struct set_entry
*sentry
;
2961 hentry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2963 return hentry
->data
;
2965 block
= ir3_block_create(ctx
->ir
);
2966 block
->nblock
= nblock
;
2967 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2969 block
->predecessors_count
= nblock
->predecessors
->entries
;
2970 block
->predecessors
= ralloc_array_size(block
,
2971 sizeof(block
->predecessors
[0]), block
->predecessors_count
);
2973 set_foreach(nblock
->predecessors
, sentry
) {
2974 block
->predecessors
[i
++] = get_block(ctx
, sentry
->key
);
2981 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2983 struct ir3_block
*block
= get_block(ctx
, nblock
);
2985 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2986 if (nblock
->successors
[i
]) {
2987 block
->successors
[i
] =
2988 get_block(ctx
, nblock
->successors
[i
]);
2993 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2995 /* re-emit addr register in each block if needed: */
2996 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr_ht
); i
++) {
2997 _mesa_hash_table_destroy(ctx
->addr_ht
[i
], NULL
);
2998 ctx
->addr_ht
[i
] = NULL
;
3001 nir_foreach_instr(instr
, nblock
) {
3002 emit_instr(ctx
, instr
);
3008 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
3011 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
3013 struct ir3_instruction
*condition
= get_src(ctx
, &nif
->condition
)[0];
3015 ctx
->block
->condition
=
3016 get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
3018 emit_cf_list(ctx
, &nif
->then_list
);
3019 emit_cf_list(ctx
, &nif
->else_list
);
3023 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
3025 emit_cf_list(ctx
, &nloop
->body
);
3029 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
3031 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3032 switch (node
->type
) {
3033 case nir_cf_node_block
:
3034 emit_block(ctx
, nir_cf_node_as_block(node
));
3036 case nir_cf_node_if
:
3037 emit_if(ctx
, nir_cf_node_as_if(node
));
3039 case nir_cf_node_loop
:
3040 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3042 case nir_cf_node_function
:
3043 compile_error(ctx
, "TODO\n");
3049 /* emit stream-out code. At this point, the current block is the original
3050 * (nir) end block, and nir ensures that all flow control paths terminate
3051 * into the end block. We re-purpose the original end block to generate
3052 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
3053 * block holding stream-out write instructions, followed by the new end
3057 * p0.x = (vtxcnt < maxvtxcnt)
3058 * // succs: blockStreamOut, blockNewEnd
3061 * ... stream-out instructions ...
3062 * // succs: blockNewEnd
3068 emit_stream_out(struct ir3_context
*ctx
)
3070 struct ir3_shader_variant
*v
= ctx
->so
;
3071 struct ir3
*ir
= ctx
->ir
;
3072 struct pipe_stream_output_info
*strmout
=
3073 &ctx
->so
->shader
->stream_output
;
3074 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
3075 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
3076 struct ir3_instruction
*bases
[PIPE_MAX_SO_BUFFERS
];
3078 /* create vtxcnt input in input block at top of shader,
3079 * so that it is seen as live over the entire duration
3082 vtxcnt
= create_input(ctx
, 0);
3083 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
3085 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
3087 /* at this point, we are at the original 'end' block,
3088 * re-purpose this block to stream-out condition, then
3089 * append stream-out block and new-end block
3091 orig_end_block
= ctx
->block
;
3093 // TODO these blocks need to update predecessors..
3094 // maybe w/ store_global intrinsic, we could do this
3095 // stuff in nir->nir pass
3097 stream_out_block
= ir3_block_create(ir
);
3098 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
3100 new_end_block
= ir3_block_create(ir
);
3101 list_addtail(&new_end_block
->node
, &ir
->block_list
);
3103 orig_end_block
->successors
[0] = stream_out_block
;
3104 orig_end_block
->successors
[1] = new_end_block
;
3105 stream_out_block
->successors
[0] = new_end_block
;
3107 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
3108 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
3109 cond
->regs
[0]->num
= regid(REG_P0
, 0);
3110 cond
->cat2
.condition
= IR3_COND_LT
;
3112 /* condition goes on previous block to the conditional,
3113 * since it is used to pick which of the two successor
3116 orig_end_block
->condition
= cond
;
3118 /* switch to stream_out_block to generate the stream-out
3121 ctx
->block
= stream_out_block
;
3123 /* Calculate base addresses based on vtxcnt. Instructions
3124 * generated for bases not used in following loop will be
3125 * stripped out in the backend.
3127 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
3128 unsigned stride
= strmout
->stride
[i
];
3129 struct ir3_instruction
*base
, *off
;
3131 base
= create_uniform(ctx
, regid(v
->constbase
.tfbo
, i
));
3133 /* 24-bit should be enough: */
3134 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
3135 create_immed(ctx
->block
, stride
* 4), 0);
3137 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
3140 /* Generate the per-output store instructions: */
3141 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
3142 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
3143 unsigned c
= j
+ strmout
->output
[i
].start_component
;
3144 struct ir3_instruction
*base
, *out
, *stg
;
3146 base
= bases
[strmout
->output
[i
].output_buffer
];
3147 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
3149 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
3150 create_immed(ctx
->block
, 1), 0);
3151 stg
->cat6
.type
= TYPE_U32
;
3152 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
3154 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
3158 /* and finally switch to the new_end_block: */
3159 ctx
->block
= new_end_block
;
3163 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
3165 nir_metadata_require(impl
, nir_metadata_block_index
);
3167 emit_cf_list(ctx
, &impl
->body
);
3168 emit_block(ctx
, impl
->end_block
);
3170 /* at this point, we should have a single empty block,
3171 * into which we emit the 'end' instruction.
3173 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
3175 /* If stream-out (aka transform-feedback) enabled, emit the
3176 * stream-out instructions, followed by a new empty block (into
3177 * which the 'end' instruction lands).
3179 * NOTE: it is done in this order, rather than inserting before
3180 * we emit end_block, because NIR guarantees that all blocks
3181 * flow into end_block, and that end_block has no successors.
3182 * So by re-purposing end_block as the first block of stream-
3183 * out, we guarantee that all exit paths flow into the stream-
3186 if ((ctx
->compiler
->gpu_id
< 500) &&
3187 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
3188 !ctx
->so
->key
.binning_pass
) {
3189 debug_assert(ctx
->so
->type
== SHADER_VERTEX
);
3190 emit_stream_out(ctx
);
3193 ir3_END(ctx
->block
);
3196 static struct ir3_instruction
*
3197 create_frag_coord(struct ir3_context
*ctx
, unsigned comp
)
3199 struct ir3_block
*block
= ctx
->block
;
3200 struct ir3_instruction
*instr
;
3202 if (!ctx
->frag_coord
) {
3203 ctx
->frag_coord
= create_input_compmask(ctx
, 0, 0xf);
3204 /* defer add_sysval_input() until after all inputs created */
3207 split_dest(block
, &instr
, ctx
->frag_coord
, comp
, 1);
3212 /* for frag_coord, we get unsigned values.. we need
3213 * to subtract (integer) 8 and divide by 16 (right-
3214 * shift by 4) then convert to float:
3218 * mov.u32f32 dst, tmp
3221 instr
= ir3_SUB_S(block
, instr
, 0,
3222 create_immed(block
, 8), 0);
3223 instr
= ir3_SHR_B(block
, instr
, 0,
3224 create_immed(block
, 4), 0);
3225 instr
= ir3_COV(block
, instr
, TYPE_U32
, TYPE_F32
);
3231 /* seems that we can use these as-is: */
3237 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
3239 struct ir3_shader_variant
*so
= ctx
->so
;
3240 unsigned array_len
= MAX2(glsl_get_length(in
->type
), 1);
3241 unsigned ncomp
= glsl_get_components(in
->type
);
3242 unsigned n
= in
->data
.driver_location
;
3243 unsigned slot
= in
->data
.location
;
3245 DBG("; in: slot=%u, len=%ux%u, drvloc=%u",
3246 slot
, array_len
, ncomp
, n
);
3248 /* let's pretend things other than vec4 don't exist: */
3249 ncomp
= MAX2(ncomp
, 4);
3250 compile_assert(ctx
, ncomp
== 4);
3252 so
->inputs
[n
].slot
= slot
;
3253 so
->inputs
[n
].compmask
= (1 << ncomp
) - 1;
3254 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
3255 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
3257 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3258 for (int i
= 0; i
< ncomp
; i
++) {
3259 struct ir3_instruction
*instr
= NULL
;
3260 unsigned idx
= (n
* 4) + i
;
3262 if (slot
== VARYING_SLOT_POS
) {
3263 so
->inputs
[n
].bary
= false;
3264 so
->frag_coord
= true;
3265 instr
= create_frag_coord(ctx
, i
);
3266 } else if (slot
== VARYING_SLOT_PNTC
) {
3267 /* see for example st_get_generic_varying_index().. this is
3268 * maybe a bit mesa/st specific. But we need things to line
3269 * up for this in fdN_program:
3270 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
3271 * if (emit->sprite_coord_enable & texmask) {
3275 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
3276 so
->inputs
[n
].bary
= true;
3277 instr
= create_frag_input(ctx
, false);
3279 bool use_ldlv
= false;
3281 /* detect the special case for front/back colors where
3282 * we need to do flat vs smooth shading depending on
3285 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
3287 case VARYING_SLOT_COL0
:
3288 case VARYING_SLOT_COL1
:
3289 case VARYING_SLOT_BFC0
:
3290 case VARYING_SLOT_BFC1
:
3291 so
->inputs
[n
].rasterflat
= true;
3298 if (ctx
->compiler
->flat_bypass
) {
3299 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
3300 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
3304 so
->inputs
[n
].bary
= true;
3306 instr
= create_frag_input(ctx
, use_ldlv
);
3309 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
3311 ctx
->ir
->inputs
[idx
] = instr
;
3313 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
3314 for (int i
= 0; i
< ncomp
; i
++) {
3315 unsigned idx
= (n
* 4) + i
;
3316 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
3317 ctx
->ir
->inputs
[idx
] = create_input(ctx
, idx
);
3320 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3323 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== SHADER_VERTEX
)) {
3324 so
->total_in
+= ncomp
;
3329 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
3331 struct ir3_shader_variant
*so
= ctx
->so
;
3332 unsigned array_len
= MAX2(glsl_get_length(out
->type
), 1);
3333 unsigned ncomp
= glsl_get_components(out
->type
);
3334 unsigned n
= out
->data
.driver_location
;
3335 unsigned slot
= out
->data
.location
;
3338 DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
3339 slot
, array_len
, ncomp
, n
);
3341 /* let's pretend things other than vec4 don't exist: */
3342 ncomp
= MAX2(ncomp
, 4);
3343 compile_assert(ctx
, ncomp
== 4);
3345 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3347 case FRAG_RESULT_DEPTH
:
3348 comp
= 2; /* tgsi will write to .z component */
3349 so
->writes_pos
= true;
3351 case FRAG_RESULT_COLOR
:
3355 if (slot
>= FRAG_RESULT_DATA0
)
3357 compile_error(ctx
, "unknown FS output name: %s\n",
3358 gl_frag_result_name(slot
));
3360 } else if (ctx
->so
->type
== SHADER_VERTEX
) {
3362 case VARYING_SLOT_POS
:
3363 so
->writes_pos
= true;
3365 case VARYING_SLOT_PSIZ
:
3366 so
->writes_psize
= true;
3368 case VARYING_SLOT_COL0
:
3369 case VARYING_SLOT_COL1
:
3370 case VARYING_SLOT_BFC0
:
3371 case VARYING_SLOT_BFC1
:
3372 case VARYING_SLOT_FOGC
:
3373 case VARYING_SLOT_CLIP_DIST0
:
3374 case VARYING_SLOT_CLIP_DIST1
:
3375 case VARYING_SLOT_CLIP_VERTEX
:
3378 if (slot
>= VARYING_SLOT_VAR0
)
3380 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
3382 compile_error(ctx
, "unknown VS output name: %s\n",
3383 gl_varying_slot_name(slot
));
3386 compile_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3389 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
3391 so
->outputs
[n
].slot
= slot
;
3392 so
->outputs
[n
].regid
= regid(n
, comp
);
3393 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
3395 for (int i
= 0; i
< ncomp
; i
++) {
3396 unsigned idx
= (n
* 4) + i
;
3397 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
3398 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3403 max_drvloc(struct exec_list
*vars
)
3406 nir_foreach_variable(var
, vars
) {
3407 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
3412 static const unsigned max_sysvals
[SHADER_MAX
] = {
3413 [SHADER_FRAGMENT
] = 24, // TODO
3414 [SHADER_VERTEX
] = 16,
3415 [SHADER_COMPUTE
] = 16, // TODO how many do we actually need?
3419 emit_instructions(struct ir3_context
*ctx
)
3421 unsigned ninputs
, noutputs
;
3422 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
3424 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
3425 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
3427 /* we need to leave room for sysvals:
3429 ninputs
+= max_sysvals
[ctx
->so
->type
];
3431 ctx
->ir
= ir3_create(ctx
->compiler
, ninputs
, noutputs
);
3433 /* Create inputs in first block: */
3434 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
3435 ctx
->in_block
= ctx
->block
;
3436 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
3438 ninputs
-= max_sysvals
[ctx
->so
->type
];
3440 /* for fragment shader, the vcoord input register is used as the
3441 * base for bary.f varying fetch instrs:
3443 struct ir3_instruction
*vcoord
= NULL
;
3444 if (ctx
->so
->type
== SHADER_FRAGMENT
) {
3445 struct ir3_instruction
*xy
[2];
3447 vcoord
= create_input_compmask(ctx
, 0, 0x3);
3448 split_dest(ctx
->block
, xy
, vcoord
, 0, 2);
3450 ctx
->frag_vcoord
= create_collect(ctx
, xy
, 2);
3454 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
3455 setup_input(ctx
, var
);
3458 /* Defer add_sysval_input() stuff until after setup_inputs(),
3459 * because sysvals need to be appended after varyings:
3462 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_VARYING_COORD
,
3466 if (ctx
->frag_coord
) {
3467 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_FRAG_COORD
,
3468 0xf, ctx
->frag_coord
);
3471 /* Setup outputs: */
3472 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
3473 setup_output(ctx
, var
);
3476 /* Setup registers (which should only be arrays): */
3477 nir_foreach_register(reg
, &ctx
->s
->registers
) {
3478 declare_array(ctx
, reg
);
3481 /* NOTE: need to do something more clever when we support >1 fxn */
3482 nir_foreach_register(reg
, &fxn
->registers
) {
3483 declare_array(ctx
, reg
);
3485 /* And emit the body: */
3487 emit_function(ctx
, fxn
);
3490 /* from NIR perspective, we actually have varying inputs. But the varying
3491 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
3492 * only actual inputs are the sysvals.
3495 fixup_frag_inputs(struct ir3_context
*ctx
)
3497 struct ir3_shader_variant
*so
= ctx
->so
;
3498 struct ir3
*ir
= ctx
->ir
;
3501 /* sysvals should appear at the end of the inputs, drop everything else: */
3502 while ((i
< so
->inputs_count
) && !so
->inputs
[i
].sysval
)
3505 /* at IR level, inputs are always blocks of 4 scalars: */
3508 ir
->inputs
= &ir
->inputs
[i
];
3512 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3513 * need to assign the tex state indexes for these after we know the
3517 fixup_astc_srgb(struct ir3_context
*ctx
)
3519 struct ir3_shader_variant
*so
= ctx
->so
;
3520 /* indexed by original tex idx, value is newly assigned alpha sampler
3521 * state tex idx. Zero is invalid since there is at least one sampler
3524 unsigned alt_tex_state
[16] = {0};
3525 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
3528 so
->astc_srgb
.base
= tex_idx
;
3530 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
3531 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
3533 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
3535 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
3536 /* assign new alternate/alpha tex state slot: */
3537 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
3538 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
3539 so
->astc_srgb
.count
++;
3542 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
3547 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
3548 struct ir3_shader_variant
*so
)
3550 struct ir3_context
*ctx
;
3552 struct ir3_instruction
**inputs
;
3553 unsigned i
, j
, actual_in
, inloc
;
3554 int ret
= 0, max_bary
;
3558 ctx
= compile_init(compiler
, so
);
3560 DBG("INIT failed!");
3565 emit_instructions(ctx
);
3568 DBG("EMIT failed!");
3573 ir
= so
->ir
= ctx
->ir
;
3575 /* keep track of the inputs from TGSI perspective.. */
3576 inputs
= ir
->inputs
;
3578 /* but fixup actual inputs for frag shader: */
3579 if (so
->type
== SHADER_FRAGMENT
)
3580 fixup_frag_inputs(ctx
);
3582 /* at this point, for binning pass, throw away unneeded outputs: */
3583 if (so
->key
.binning_pass
) {
3584 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
3585 unsigned slot
= so
->outputs
[i
].slot
;
3587 /* throw away everything but first position/psize */
3588 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3590 so
->outputs
[j
] = so
->outputs
[i
];
3591 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
3592 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
3593 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
3594 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
3599 so
->outputs_count
= j
;
3600 ir
->noutputs
= j
* 4;
3603 /* if we want half-precision outputs, mark the output registers
3606 if (so
->key
.half_precision
) {
3607 for (i
= 0; i
< ir
->noutputs
; i
++) {
3608 struct ir3_instruction
*out
= ir
->outputs
[i
];
3613 /* if frag shader writes z, that needs to be full precision: */
3614 if (so
->outputs
[i
/4].slot
== FRAG_RESULT_DEPTH
)
3617 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3618 /* output could be a fanout (ie. texture fetch output)
3619 * in which case we need to propagate the half-reg flag
3620 * up to the definer so that RA sees it:
3622 if (out
->opc
== OPC_META_FO
) {
3623 out
= out
->regs
[1]->instr
;
3624 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3627 if (out
->opc
== OPC_MOV
) {
3628 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
3633 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3634 printf("BEFORE CP:\n");
3640 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3641 printf("BEFORE GROUPING:\n");
3645 ir3_sched_add_deps(ir
);
3647 /* Group left/right neighbors, inserting mov's where needed to
3652 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3653 printf("AFTER GROUPING:\n");
3659 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3660 printf("AFTER DEPTH:\n");
3664 ret
= ir3_sched(ir
);
3666 DBG("SCHED failed!");
3670 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3671 printf("AFTER SCHED:\n");
3675 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
3681 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3682 printf("AFTER RA:\n");
3686 /* fixup input/outputs: */
3687 for (i
= 0; i
< so
->outputs_count
; i
++) {
3688 so
->outputs
[i
].regid
= ir
->outputs
[i
*4]->regs
[0]->num
;
3691 /* Note that some or all channels of an input may be unused: */
3694 for (i
= 0; i
< so
->inputs_count
; i
++) {
3695 unsigned j
, reg
= regid(63,0), compmask
= 0, maxcomp
= 0;
3696 so
->inputs
[i
].ncomp
= 0;
3697 so
->inputs
[i
].inloc
= inloc
;
3698 for (j
= 0; j
< 4; j
++) {
3699 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
3700 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
3701 compmask
|= (1 << j
);
3702 reg
= in
->regs
[0]->num
- j
;
3704 so
->inputs
[i
].ncomp
++;
3705 if ((so
->type
== SHADER_FRAGMENT
) && so
->inputs
[i
].bary
) {
3707 assert(in
->regs
[1]->flags
& IR3_REG_IMMED
);
3708 in
->regs
[1]->iim_val
= inloc
+ j
;
3713 if ((so
->type
== SHADER_FRAGMENT
) && compmask
&& so
->inputs
[i
].bary
) {
3715 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
3717 } else if (!so
->inputs
[i
].sysval
) {
3718 so
->inputs
[i
].compmask
= compmask
;
3720 so
->inputs
[i
].regid
= reg
;
3724 fixup_astc_srgb(ctx
);
3726 /* We need to do legalize after (for frag shader's) the "bary.f"
3727 * offsets (inloc) have been assigned.
3729 ir3_legalize(ir
, &so
->has_samp
, &so
->has_ssbo
, &max_bary
);
3731 if (fd_mesa_debug
& FD_DBG_OPTMSGS
) {
3732 printf("AFTER LEGALIZE:\n");
3736 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3737 if (so
->type
== SHADER_VERTEX
)
3738 so
->total_in
= actual_in
;
3740 so
->total_in
= max_bary
+ 1;
3745 ir3_destroy(so
->ir
);