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i915: Swap meanings of KIL and KILP.
[mesa.git] / src / gallium / drivers / i915simple / i915_fpc_translate.c
1 /**************************************************************************
2 *
3 * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29 #include <stdarg.h>
30
31 #include "i915_reg.h"
32 #include "i915_context.h"
33 #include "i915_fpc.h"
34
35 #include "pipe/p_shader_tokens.h"
36 #include "util/u_string.h"
37 #include "tgsi/tgsi_parse.h"
38 #include "tgsi/tgsi_dump.h"
39
40 #include "draw/draw_vertex.h"
41
42
43 /**
44 * Simple pass-through fragment shader to use when we don't have
45 * a real shader (or it fails to compile for some reason).
46 */
47 static unsigned passthrough[] =
48 {
49 _3DSTATE_PIXEL_SHADER_PROGRAM | ((2*3)-1),
50
51 /* declare input color:
52 */
53 (D0_DCL |
54 (REG_TYPE_T << D0_TYPE_SHIFT) |
55 (T_DIFFUSE << D0_NR_SHIFT) |
56 D0_CHANNEL_ALL),
57 0,
58 0,
59
60 /* move to output color:
61 */
62 (A0_MOV |
63 (REG_TYPE_OC << A0_DEST_TYPE_SHIFT) |
64 A0_DEST_CHANNEL_ALL |
65 (REG_TYPE_T << A0_SRC0_TYPE_SHIFT) |
66 (T_DIFFUSE << A0_SRC0_NR_SHIFT)),
67 0x01230000, /* .xyzw */
68 0
69 };
70
71
72 /* 1, -1/3!, 1/5!, -1/7! */
73 static const float sin_constants[4] = { 1.0,
74 -1.0f / (3 * 2 * 1),
75 1.0f / (5 * 4 * 3 * 2 * 1),
76 -1.0f / (7 * 6 * 5 * 4 * 3 * 2 * 1)
77 };
78
79 /* 1, -1/2!, 1/4!, -1/6! */
80 static const float cos_constants[4] = { 1.0,
81 -1.0f / (2 * 1),
82 1.0f / (4 * 3 * 2 * 1),
83 -1.0f / (6 * 5 * 4 * 3 * 2 * 1)
84 };
85
86
87
88 /**
89 * component-wise negation of ureg
90 */
91 static INLINE int
92 negate(int reg, int x, int y, int z, int w)
93 {
94 /* Another neat thing about the UREG representation */
95 return reg ^ (((x & 1) << UREG_CHANNEL_X_NEGATE_SHIFT) |
96 ((y & 1) << UREG_CHANNEL_Y_NEGATE_SHIFT) |
97 ((z & 1) << UREG_CHANNEL_Z_NEGATE_SHIFT) |
98 ((w & 1) << UREG_CHANNEL_W_NEGATE_SHIFT));
99 }
100
101
102 /**
103 * In the event of a translation failure, we'll generate a simple color
104 * pass-through program.
105 */
106 static void
107 i915_use_passthrough_shader(struct i915_fragment_shader *fs)
108 {
109 fs->program = (uint *) MALLOC(sizeof(passthrough));
110 if (fs->program) {
111 memcpy(fs->program, passthrough, sizeof(passthrough));
112 fs->program_len = Elements(passthrough);
113 }
114 fs->num_constants = 0;
115 }
116
117
118 void
119 i915_program_error(struct i915_fp_compile *p, const char *msg, ...)
120 {
121 va_list args;
122 char buffer[1024];
123
124 debug_printf("i915_program_error: ");
125 va_start( args, msg );
126 util_vsnprintf( buffer, sizeof(buffer), msg, args );
127 va_end( args );
128 debug_printf(buffer);
129 debug_printf("\n");
130
131 p->error = 1;
132 }
133
134
135
136 /**
137 * Construct a ureg for the given source register. Will emit
138 * constants, apply swizzling and negation as needed.
139 */
140 static uint
141 src_vector(struct i915_fp_compile *p,
142 const struct tgsi_full_src_register *source)
143 {
144 uint index = source->SrcRegister.Index;
145 uint src, sem_name, sem_ind;
146
147 switch (source->SrcRegister.File) {
148 case TGSI_FILE_TEMPORARY:
149 if (source->SrcRegister.Index >= I915_MAX_TEMPORARY) {
150 i915_program_error(p, "Exceeded max temporary reg");
151 return 0;
152 }
153 src = UREG(REG_TYPE_R, index);
154 break;
155 case TGSI_FILE_INPUT:
156 /* XXX: Packing COL1, FOGC into a single attribute works for
157 * texenv programs, but will fail for real fragment programs
158 * that use these attributes and expect them to be a full 4
159 * components wide. Could use a texcoord to pass these
160 * attributes if necessary, but that won't work in the general
161 * case.
162 *
163 * We also use a texture coordinate to pass wpos when possible.
164 */
165
166 sem_name = p->shader->info.input_semantic_name[index];
167 sem_ind = p->shader->info.input_semantic_index[index];
168
169 switch (sem_name) {
170 case TGSI_SEMANTIC_POSITION:
171 debug_printf("SKIP SEM POS\n");
172 /*
173 assert(p->wpos_tex != -1);
174 src = i915_emit_decl(p, REG_TYPE_T, p->wpos_tex, D0_CHANNEL_ALL);
175 */
176 break;
177 case TGSI_SEMANTIC_COLOR:
178 if (sem_ind == 0) {
179 src = i915_emit_decl(p, REG_TYPE_T, T_DIFFUSE, D0_CHANNEL_ALL);
180 }
181 else {
182 /* secondary color */
183 assert(sem_ind == 1);
184 src = i915_emit_decl(p, REG_TYPE_T, T_SPECULAR, D0_CHANNEL_XYZ);
185 src = swizzle(src, X, Y, Z, ONE);
186 }
187 break;
188 case TGSI_SEMANTIC_FOG:
189 src = i915_emit_decl(p, REG_TYPE_T, T_FOG_W, D0_CHANNEL_W);
190 src = swizzle(src, W, W, W, W);
191 break;
192 case TGSI_SEMANTIC_GENERIC:
193 /* usually a texcoord */
194 src = i915_emit_decl(p, REG_TYPE_T, T_TEX0 + sem_ind, D0_CHANNEL_ALL);
195 break;
196 default:
197 i915_program_error(p, "Bad source->Index");
198 return 0;
199 }
200 break;
201
202 case TGSI_FILE_IMMEDIATE:
203 assert(index < p->num_immediates);
204 index = p->immediates_map[index];
205 /* fall-through */
206 case TGSI_FILE_CONSTANT:
207 src = UREG(REG_TYPE_CONST, index);
208 break;
209
210 default:
211 i915_program_error(p, "Bad source->File");
212 return 0;
213 }
214
215 if (source->SrcRegister.Extended) {
216 src = swizzle(src,
217 source->SrcRegisterExtSwz.ExtSwizzleX,
218 source->SrcRegisterExtSwz.ExtSwizzleY,
219 source->SrcRegisterExtSwz.ExtSwizzleZ,
220 source->SrcRegisterExtSwz.ExtSwizzleW);
221 }
222 else {
223 src = swizzle(src,
224 source->SrcRegister.SwizzleX,
225 source->SrcRegister.SwizzleY,
226 source->SrcRegister.SwizzleZ,
227 source->SrcRegister.SwizzleW);
228 }
229
230
231 /* There's both negate-all-components and per-component negation.
232 * Try to handle both here.
233 */
234 {
235 int nx = source->SrcRegisterExtSwz.NegateX;
236 int ny = source->SrcRegisterExtSwz.NegateY;
237 int nz = source->SrcRegisterExtSwz.NegateZ;
238 int nw = source->SrcRegisterExtSwz.NegateW;
239 if (source->SrcRegister.Negate) {
240 nx = !nx;
241 ny = !ny;
242 nz = !nz;
243 nw = !nw;
244 }
245 src = negate(src, nx, ny, nz, nw);
246 }
247
248 /* no abs() or post-abs negation */
249 #if 0
250 /* XXX assertions disabled to allow arbfplight.c to run */
251 /* XXX enable these assertions, or fix things */
252 assert(!source->SrcRegisterExtMod.Absolute);
253 assert(!source->SrcRegisterExtMod.Negate);
254 #endif
255 return src;
256 }
257
258
259 /**
260 * Construct a ureg for a destination register.
261 */
262 static uint
263 get_result_vector(struct i915_fp_compile *p,
264 const struct tgsi_full_dst_register *dest)
265 {
266 switch (dest->DstRegister.File) {
267 case TGSI_FILE_OUTPUT:
268 {
269 uint sem_name = p->shader->info.output_semantic_name[dest->DstRegister.Index];
270 switch (sem_name) {
271 case TGSI_SEMANTIC_POSITION:
272 return UREG(REG_TYPE_OD, 0);
273 case TGSI_SEMANTIC_COLOR:
274 return UREG(REG_TYPE_OC, 0);
275 default:
276 i915_program_error(p, "Bad inst->DstReg.Index/semantics");
277 return 0;
278 }
279 }
280 case TGSI_FILE_TEMPORARY:
281 return UREG(REG_TYPE_R, dest->DstRegister.Index);
282 default:
283 i915_program_error(p, "Bad inst->DstReg.File");
284 return 0;
285 }
286 }
287
288
289 /**
290 * Compute flags for saturation and writemask.
291 */
292 static uint
293 get_result_flags(const struct tgsi_full_instruction *inst)
294 {
295 const uint writeMask
296 = inst->FullDstRegisters[0].DstRegister.WriteMask;
297 uint flags = 0x0;
298
299 if (inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE)
300 flags |= A0_DEST_SATURATE;
301
302 if (writeMask & TGSI_WRITEMASK_X)
303 flags |= A0_DEST_CHANNEL_X;
304 if (writeMask & TGSI_WRITEMASK_Y)
305 flags |= A0_DEST_CHANNEL_Y;
306 if (writeMask & TGSI_WRITEMASK_Z)
307 flags |= A0_DEST_CHANNEL_Z;
308 if (writeMask & TGSI_WRITEMASK_W)
309 flags |= A0_DEST_CHANNEL_W;
310
311 return flags;
312 }
313
314
315 /**
316 * Convert TGSI_TEXTURE_x token to DO_SAMPLE_TYPE_x token
317 */
318 static uint
319 translate_tex_src_target(struct i915_fp_compile *p, uint tex)
320 {
321 switch (tex) {
322 case TGSI_TEXTURE_1D:
323 return D0_SAMPLE_TYPE_2D;
324 case TGSI_TEXTURE_2D:
325 return D0_SAMPLE_TYPE_2D;
326 case TGSI_TEXTURE_RECT:
327 return D0_SAMPLE_TYPE_2D;
328 case TGSI_TEXTURE_3D:
329 return D0_SAMPLE_TYPE_VOLUME;
330 case TGSI_TEXTURE_CUBE:
331 return D0_SAMPLE_TYPE_CUBE;
332 default:
333 i915_program_error(p, "TexSrc type");
334 return 0;
335 }
336 }
337
338
339 /**
340 * Generate texel lookup instruction.
341 */
342 static void
343 emit_tex(struct i915_fp_compile *p,
344 const struct tgsi_full_instruction *inst,
345 uint opcode)
346 {
347 uint texture = inst->InstructionExtTexture.Texture;
348 uint unit = inst->FullSrcRegisters[1].SrcRegister.Index;
349 uint tex = translate_tex_src_target( p, texture );
350 uint sampler = i915_emit_decl(p, REG_TYPE_S, unit, tex);
351 uint coord = src_vector( p, &inst->FullSrcRegisters[0]);
352
353 i915_emit_texld( p,
354 get_result_vector( p, &inst->FullDstRegisters[0] ),
355 get_result_flags( inst ),
356 sampler,
357 coord,
358 opcode);
359 }
360
361
362 /**
363 * Generate a simple arithmetic instruction
364 * \param opcode the i915 opcode
365 * \param numArgs the number of input/src arguments
366 */
367 static void
368 emit_simple_arith(struct i915_fp_compile *p,
369 const struct tgsi_full_instruction *inst,
370 uint opcode, uint numArgs)
371 {
372 uint arg1, arg2, arg3;
373
374 assert(numArgs <= 3);
375
376 arg1 = (numArgs < 1) ? 0 : src_vector( p, &inst->FullSrcRegisters[0] );
377 arg2 = (numArgs < 2) ? 0 : src_vector( p, &inst->FullSrcRegisters[1] );
378 arg3 = (numArgs < 3) ? 0 : src_vector( p, &inst->FullSrcRegisters[2] );
379
380 i915_emit_arith( p,
381 opcode,
382 get_result_vector( p, &inst->FullDstRegisters[0]),
383 get_result_flags( inst ), 0,
384 arg1,
385 arg2,
386 arg3 );
387 }
388
389
390 /** As above, but swap the first two src regs */
391 static void
392 emit_simple_arith_swap2(struct i915_fp_compile *p,
393 const struct tgsi_full_instruction *inst,
394 uint opcode, uint numArgs)
395 {
396 struct tgsi_full_instruction inst2;
397
398 assert(numArgs == 2);
399
400 /* transpose first two registers */
401 inst2 = *inst;
402 inst2.FullSrcRegisters[0] = inst->FullSrcRegisters[1];
403 inst2.FullSrcRegisters[1] = inst->FullSrcRegisters[0];
404
405 emit_simple_arith(p, &inst2, opcode, numArgs);
406 }
407
408
409 #ifndef M_PI
410 #define M_PI 3.14159265358979323846
411 #endif
412
413 /*
414 * Translate TGSI instruction to i915 instruction.
415 *
416 * Possible concerns:
417 *
418 * SIN, COS -- could use another taylor step?
419 * LIT -- results seem a little different to sw mesa
420 * LOG -- different to mesa on negative numbers, but this is conformant.
421 */
422 static void
423 i915_translate_instruction(struct i915_fp_compile *p,
424 const struct tgsi_full_instruction *inst)
425 {
426 uint writemask;
427 uint src0, src1, src2, flags;
428 uint tmp = 0;
429
430 switch (inst->Instruction.Opcode) {
431 case TGSI_OPCODE_ABS:
432 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
433 i915_emit_arith(p,
434 A0_MAX,
435 get_result_vector(p, &inst->FullDstRegisters[0]),
436 get_result_flags(inst), 0,
437 src0, negate(src0, 1, 1, 1, 1), 0);
438 break;
439
440 case TGSI_OPCODE_ADD:
441 emit_simple_arith(p, inst, A0_ADD, 2);
442 break;
443
444 case TGSI_OPCODE_CMP:
445 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
446 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
447 src2 = src_vector(p, &inst->FullSrcRegisters[2]);
448 i915_emit_arith(p, A0_CMP,
449 get_result_vector(p, &inst->FullDstRegisters[0]),
450 get_result_flags(inst),
451 0, src0, src2, src1); /* NOTE: order of src2, src1 */
452 break;
453
454 case TGSI_OPCODE_COS:
455 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
456 tmp = i915_get_utemp(p);
457
458 i915_emit_arith(p,
459 A0_MUL,
460 tmp, A0_DEST_CHANNEL_X, 0,
461 src0, i915_emit_const1f(p, 1.0f / (float) (M_PI * 2.0)), 0);
462
463 i915_emit_arith(p, A0_MOD, tmp, A0_DEST_CHANNEL_X, 0, tmp, 0, 0);
464
465 /* By choosing different taylor constants, could get rid of this mul:
466 */
467 i915_emit_arith(p,
468 A0_MUL,
469 tmp, A0_DEST_CHANNEL_X, 0,
470 tmp, i915_emit_const1f(p, (float) (M_PI * 2.0)), 0);
471
472 /*
473 * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1
474 * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, 1
475 * t0 = MUL t0.xxz1 t0.z111 ; x^6 x^4 x^2 1
476 * result = DP4 t0, cos_constants
477 */
478 i915_emit_arith(p,
479 A0_MUL,
480 tmp, A0_DEST_CHANNEL_XY, 0,
481 swizzle(tmp, X, X, ONE, ONE),
482 swizzle(tmp, X, ONE, ONE, ONE), 0);
483
484 i915_emit_arith(p,
485 A0_MUL,
486 tmp, A0_DEST_CHANNEL_XYZ, 0,
487 swizzle(tmp, X, Y, X, ONE),
488 swizzle(tmp, X, X, ONE, ONE), 0);
489
490 i915_emit_arith(p,
491 A0_MUL,
492 tmp, A0_DEST_CHANNEL_XYZ, 0,
493 swizzle(tmp, X, X, Z, ONE),
494 swizzle(tmp, Z, ONE, ONE, ONE), 0);
495
496 i915_emit_arith(p,
497 A0_DP4,
498 get_result_vector(p, &inst->FullDstRegisters[0]),
499 get_result_flags(inst), 0,
500 swizzle(tmp, ONE, Z, Y, X),
501 i915_emit_const4fv(p, cos_constants), 0);
502 break;
503
504 case TGSI_OPCODE_DP3:
505 emit_simple_arith(p, inst, A0_DP3, 2);
506 break;
507
508 case TGSI_OPCODE_DP4:
509 emit_simple_arith(p, inst, A0_DP4, 2);
510 break;
511
512 case TGSI_OPCODE_DPH:
513 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
514 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
515
516 i915_emit_arith(p,
517 A0_DP4,
518 get_result_vector(p, &inst->FullDstRegisters[0]),
519 get_result_flags(inst), 0,
520 swizzle(src0, X, Y, Z, ONE), src1, 0);
521 break;
522
523 case TGSI_OPCODE_DST:
524 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
525 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
526
527 /* result[0] = 1 * 1;
528 * result[1] = a[1] * b[1];
529 * result[2] = a[2] * 1;
530 * result[3] = 1 * b[3];
531 */
532 i915_emit_arith(p,
533 A0_MUL,
534 get_result_vector(p, &inst->FullDstRegisters[0]),
535 get_result_flags(inst), 0,
536 swizzle(src0, ONE, Y, Z, ONE),
537 swizzle(src1, ONE, Y, ONE, W), 0);
538 break;
539
540 case TGSI_OPCODE_END:
541 /* no-op */
542 break;
543
544 case TGSI_OPCODE_EX2:
545 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
546
547 i915_emit_arith(p,
548 A0_EXP,
549 get_result_vector(p, &inst->FullDstRegisters[0]),
550 get_result_flags(inst), 0,
551 swizzle(src0, X, X, X, X), 0, 0);
552 break;
553
554 case TGSI_OPCODE_FLR:
555 emit_simple_arith(p, inst, A0_FLR, 1);
556 break;
557
558 case TGSI_OPCODE_FRC:
559 emit_simple_arith(p, inst, A0_FRC, 1);
560 break;
561
562 case TGSI_OPCODE_KIL:
563 /* kill if src[0].x < 0 || src[0].y < 0 ... */
564 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
565 tmp = i915_get_utemp(p);
566
567 i915_emit_texld(p,
568 tmp, /* dest reg: a dummy reg */
569 A0_DEST_CHANNEL_ALL, /* dest writemask */
570 0, /* sampler */
571 src0, /* coord*/
572 T0_TEXKILL); /* opcode */
573 break;
574
575 case TGSI_OPCODE_KILP:
576 assert(0); /* not tested yet */
577 break;
578
579 case TGSI_OPCODE_LG2:
580 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
581
582 i915_emit_arith(p,
583 A0_LOG,
584 get_result_vector(p, &inst->FullDstRegisters[0]),
585 get_result_flags(inst), 0,
586 swizzle(src0, X, X, X, X), 0, 0);
587 break;
588
589 case TGSI_OPCODE_LIT:
590 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
591 tmp = i915_get_utemp(p);
592
593 /* tmp = max( a.xyzw, a.00zw )
594 * XXX: Clamp tmp.w to -128..128
595 * tmp.y = log(tmp.y)
596 * tmp.y = tmp.w * tmp.y
597 * tmp.y = exp(tmp.y)
598 * result = cmp (a.11-x1, a.1x01, a.1xy1 )
599 */
600 i915_emit_arith(p, A0_MAX, tmp, A0_DEST_CHANNEL_ALL, 0,
601 src0, swizzle(src0, ZERO, ZERO, Z, W), 0);
602
603 i915_emit_arith(p, A0_LOG, tmp, A0_DEST_CHANNEL_Y, 0,
604 swizzle(tmp, Y, Y, Y, Y), 0, 0);
605
606 i915_emit_arith(p, A0_MUL, tmp, A0_DEST_CHANNEL_Y, 0,
607 swizzle(tmp, ZERO, Y, ZERO, ZERO),
608 swizzle(tmp, ZERO, W, ZERO, ZERO), 0);
609
610 i915_emit_arith(p, A0_EXP, tmp, A0_DEST_CHANNEL_Y, 0,
611 swizzle(tmp, Y, Y, Y, Y), 0, 0);
612
613 i915_emit_arith(p, A0_CMP,
614 get_result_vector(p, &inst->FullDstRegisters[0]),
615 get_result_flags(inst), 0,
616 negate(swizzle(tmp, ONE, ONE, X, ONE), 0, 0, 1, 0),
617 swizzle(tmp, ONE, X, ZERO, ONE),
618 swizzle(tmp, ONE, X, Y, ONE));
619
620 break;
621
622 case TGSI_OPCODE_LRP:
623 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
624 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
625 src2 = src_vector(p, &inst->FullSrcRegisters[2]);
626 flags = get_result_flags(inst);
627 tmp = i915_get_utemp(p);
628
629 /* b*a + c*(1-a)
630 *
631 * b*a + c - ca
632 *
633 * tmp = b*a + c,
634 * result = (-c)*a + tmp
635 */
636 i915_emit_arith(p, A0_MAD, tmp,
637 flags & A0_DEST_CHANNEL_ALL, 0, src1, src0, src2);
638
639 i915_emit_arith(p, A0_MAD,
640 get_result_vector(p, &inst->FullDstRegisters[0]),
641 flags, 0, negate(src2, 1, 1, 1, 1), src0, tmp);
642 break;
643
644 case TGSI_OPCODE_MAD:
645 emit_simple_arith(p, inst, A0_MAD, 3);
646 break;
647
648 case TGSI_OPCODE_MAX:
649 emit_simple_arith(p, inst, A0_MAX, 2);
650 break;
651
652 case TGSI_OPCODE_MIN:
653 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
654 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
655 tmp = i915_get_utemp(p);
656 flags = get_result_flags(inst);
657
658 i915_emit_arith(p,
659 A0_MAX,
660 tmp, flags & A0_DEST_CHANNEL_ALL, 0,
661 negate(src0, 1, 1, 1, 1),
662 negate(src1, 1, 1, 1, 1), 0);
663
664 i915_emit_arith(p,
665 A0_MOV,
666 get_result_vector(p, &inst->FullDstRegisters[0]),
667 flags, 0, negate(tmp, 1, 1, 1, 1), 0, 0);
668 break;
669
670 case TGSI_OPCODE_MOV:
671 case TGSI_OPCODE_SWZ:
672 emit_simple_arith(p, inst, A0_MOV, 1);
673 break;
674
675 case TGSI_OPCODE_MUL:
676 emit_simple_arith(p, inst, A0_MUL, 2);
677 break;
678
679 case TGSI_OPCODE_POW:
680 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
681 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
682 tmp = i915_get_utemp(p);
683 flags = get_result_flags(inst);
684
685 /* XXX: masking on intermediate values, here and elsewhere.
686 */
687 i915_emit_arith(p,
688 A0_LOG,
689 tmp, A0_DEST_CHANNEL_X, 0,
690 swizzle(src0, X, X, X, X), 0, 0);
691
692 i915_emit_arith(p, A0_MUL, tmp, A0_DEST_CHANNEL_X, 0, tmp, src1, 0);
693
694 i915_emit_arith(p,
695 A0_EXP,
696 get_result_vector(p, &inst->FullDstRegisters[0]),
697 flags, 0, swizzle(tmp, X, X, X, X), 0, 0);
698 break;
699
700 case TGSI_OPCODE_RET:
701 /* XXX: no-op? */
702 break;
703
704 case TGSI_OPCODE_RCP:
705 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
706
707 i915_emit_arith(p,
708 A0_RCP,
709 get_result_vector(p, &inst->FullDstRegisters[0]),
710 get_result_flags(inst), 0,
711 swizzle(src0, X, X, X, X), 0, 0);
712 break;
713
714 case TGSI_OPCODE_RSQ:
715 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
716
717 i915_emit_arith(p,
718 A0_RSQ,
719 get_result_vector(p, &inst->FullDstRegisters[0]),
720 get_result_flags(inst), 0,
721 swizzle(src0, X, X, X, X), 0, 0);
722 break;
723
724 case TGSI_OPCODE_SCS:
725 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
726 tmp = i915_get_utemp(p);
727
728 /*
729 * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1
730 * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, x
731 * t1 = MUL t0.xyyw t0.yz11 ; x^7 x^5 x^3 x
732 * scs.x = DP4 t1, sin_constants
733 * t1 = MUL t0.xxz1 t0.z111 ; x^6 x^4 x^2 1
734 * scs.y = DP4 t1, cos_constants
735 */
736 i915_emit_arith(p,
737 A0_MUL,
738 tmp, A0_DEST_CHANNEL_XY, 0,
739 swizzle(src0, X, X, ONE, ONE),
740 swizzle(src0, X, ONE, ONE, ONE), 0);
741
742 i915_emit_arith(p,
743 A0_MUL,
744 tmp, A0_DEST_CHANNEL_ALL, 0,
745 swizzle(tmp, X, Y, X, Y),
746 swizzle(tmp, X, X, ONE, ONE), 0);
747
748 writemask = inst->FullDstRegisters[0].DstRegister.WriteMask;
749
750 if (writemask & TGSI_WRITEMASK_Y) {
751 uint tmp1;
752
753 if (writemask & TGSI_WRITEMASK_X)
754 tmp1 = i915_get_utemp(p);
755 else
756 tmp1 = tmp;
757
758 i915_emit_arith(p,
759 A0_MUL,
760 tmp1, A0_DEST_CHANNEL_ALL, 0,
761 swizzle(tmp, X, Y, Y, W),
762 swizzle(tmp, X, Z, ONE, ONE), 0);
763
764 i915_emit_arith(p,
765 A0_DP4,
766 get_result_vector(p, &inst->FullDstRegisters[0]),
767 A0_DEST_CHANNEL_Y, 0,
768 swizzle(tmp1, W, Z, Y, X),
769 i915_emit_const4fv(p, sin_constants), 0);
770 }
771
772 if (writemask & TGSI_WRITEMASK_X) {
773 i915_emit_arith(p,
774 A0_MUL,
775 tmp, A0_DEST_CHANNEL_XYZ, 0,
776 swizzle(tmp, X, X, Z, ONE),
777 swizzle(tmp, Z, ONE, ONE, ONE), 0);
778
779 i915_emit_arith(p,
780 A0_DP4,
781 get_result_vector(p, &inst->FullDstRegisters[0]),
782 A0_DEST_CHANNEL_X, 0,
783 swizzle(tmp, ONE, Z, Y, X),
784 i915_emit_const4fv(p, cos_constants), 0);
785 }
786 break;
787
788 case TGSI_OPCODE_SGE:
789 emit_simple_arith(p, inst, A0_SGE, 2);
790 break;
791
792 case TGSI_OPCODE_SLE:
793 /* like SGE, but swap reg0, reg1 */
794 emit_simple_arith_swap2(p, inst, A0_SGE, 2);
795 break;
796
797 case TGSI_OPCODE_SIN:
798 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
799 tmp = i915_get_utemp(p);
800
801 i915_emit_arith(p,
802 A0_MUL,
803 tmp, A0_DEST_CHANNEL_X, 0,
804 src0, i915_emit_const1f(p, 1.0f / (float) (M_PI * 2.0)), 0);
805
806 i915_emit_arith(p, A0_MOD, tmp, A0_DEST_CHANNEL_X, 0, tmp, 0, 0);
807
808 /* By choosing different taylor constants, could get rid of this mul:
809 */
810 i915_emit_arith(p,
811 A0_MUL,
812 tmp, A0_DEST_CHANNEL_X, 0,
813 tmp, i915_emit_const1f(p, (float) (M_PI * 2.0)), 0);
814
815 /*
816 * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1
817 * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, x
818 * t1 = MUL t0.xyyw t0.yz11 ; x^7 x^5 x^3 x
819 * result = DP4 t1.wzyx, sin_constants
820 */
821 i915_emit_arith(p,
822 A0_MUL,
823 tmp, A0_DEST_CHANNEL_XY, 0,
824 swizzle(tmp, X, X, ONE, ONE),
825 swizzle(tmp, X, ONE, ONE, ONE), 0);
826
827 i915_emit_arith(p,
828 A0_MUL,
829 tmp, A0_DEST_CHANNEL_ALL, 0,
830 swizzle(tmp, X, Y, X, Y),
831 swizzle(tmp, X, X, ONE, ONE), 0);
832
833 i915_emit_arith(p,
834 A0_MUL,
835 tmp, A0_DEST_CHANNEL_ALL, 0,
836 swizzle(tmp, X, Y, Y, W),
837 swizzle(tmp, X, Z, ONE, ONE), 0);
838
839 i915_emit_arith(p,
840 A0_DP4,
841 get_result_vector(p, &inst->FullDstRegisters[0]),
842 get_result_flags(inst), 0,
843 swizzle(tmp, W, Z, Y, X),
844 i915_emit_const4fv(p, sin_constants), 0);
845 break;
846
847 case TGSI_OPCODE_SLT:
848 emit_simple_arith(p, inst, A0_SLT, 2);
849 break;
850
851 case TGSI_OPCODE_SGT:
852 /* like SLT, but swap reg0, reg1 */
853 emit_simple_arith_swap2(p, inst, A0_SLT, 2);
854 break;
855
856 case TGSI_OPCODE_SUB:
857 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
858 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
859
860 i915_emit_arith(p,
861 A0_ADD,
862 get_result_vector(p, &inst->FullDstRegisters[0]),
863 get_result_flags(inst), 0,
864 src0, negate(src1, 1, 1, 1, 1), 0);
865 break;
866
867 case TGSI_OPCODE_TEX:
868 emit_tex(p, inst, T0_TEXLD);
869 break;
870
871 case TGSI_OPCODE_TXB:
872 emit_tex(p, inst, T0_TEXLDB);
873 break;
874
875 case TGSI_OPCODE_TXP:
876 emit_tex(p, inst, T0_TEXLDP);
877 break;
878
879 case TGSI_OPCODE_XPD:
880 /* Cross product:
881 * result.x = src0.y * src1.z - src0.z * src1.y;
882 * result.y = src0.z * src1.x - src0.x * src1.z;
883 * result.z = src0.x * src1.y - src0.y * src1.x;
884 * result.w = undef;
885 */
886 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
887 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
888 tmp = i915_get_utemp(p);
889
890 i915_emit_arith(p,
891 A0_MUL,
892 tmp, A0_DEST_CHANNEL_ALL, 0,
893 swizzle(src0, Z, X, Y, ONE),
894 swizzle(src1, Y, Z, X, ONE), 0);
895
896 i915_emit_arith(p,
897 A0_MAD,
898 get_result_vector(p, &inst->FullDstRegisters[0]),
899 get_result_flags(inst), 0,
900 swizzle(src0, Y, Z, X, ONE),
901 swizzle(src1, Z, X, Y, ONE),
902 negate(tmp, 1, 1, 1, 0));
903 break;
904
905 default:
906 i915_program_error(p, "bad opcode %d", inst->Instruction.Opcode);
907 p->error = 1;
908 return;
909 }
910
911 i915_release_utemps(p);
912 }
913
914
915 /**
916 * Translate TGSI fragment shader into i915 hardware instructions.
917 * \param p the translation state
918 * \param tokens the TGSI token array
919 */
920 static void
921 i915_translate_instructions(struct i915_fp_compile *p,
922 const struct tgsi_token *tokens)
923 {
924 struct i915_fragment_shader *ifs = p->shader;
925 struct tgsi_parse_context parse;
926
927 tgsi_parse_init( &parse, tokens );
928
929 while( !tgsi_parse_end_of_tokens( &parse ) ) {
930
931 tgsi_parse_token( &parse );
932
933 switch( parse.FullToken.Token.Type ) {
934 case TGSI_TOKEN_TYPE_DECLARATION:
935 if (parse.FullToken.FullDeclaration.Declaration.File
936 == TGSI_FILE_CONSTANT) {
937 uint i;
938 for (i = parse.FullToken.FullDeclaration.DeclarationRange.First;
939 i <= parse.FullToken.FullDeclaration.DeclarationRange.Last;
940 i++) {
941 assert(ifs->constant_flags[i] == 0x0);
942 ifs->constant_flags[i] = I915_CONSTFLAG_USER;
943 ifs->num_constants = MAX2(ifs->num_constants, i + 1);
944 }
945 }
946 else if (parse.FullToken.FullDeclaration.Declaration.File
947 == TGSI_FILE_TEMPORARY) {
948 uint i;
949 for (i = parse.FullToken.FullDeclaration.DeclarationRange.First;
950 i <= parse.FullToken.FullDeclaration.DeclarationRange.Last;
951 i++) {
952 assert(i < I915_MAX_TEMPORARY);
953 /* XXX just use shader->info->file_mask[TGSI_FILE_TEMPORARY] */
954 p->temp_flag |= (1 << i); /* mark temp as used */
955 }
956 }
957 break;
958
959 case TGSI_TOKEN_TYPE_IMMEDIATE:
960 {
961 const struct tgsi_full_immediate *imm
962 = &parse.FullToken.FullImmediate;
963 const uint pos = p->num_immediates++;
964 uint j;
965 for (j = 0; j < imm->Immediate.Size; j++) {
966 p->immediates[pos][j] = imm->u.ImmediateFloat32[j].Float;
967 }
968 }
969 break;
970
971 case TGSI_TOKEN_TYPE_INSTRUCTION:
972 if (p->first_instruction) {
973 /* resolve location of immediates */
974 uint i, j;
975 for (i = 0; i < p->num_immediates; i++) {
976 /* find constant slot for this immediate */
977 for (j = 0; j < I915_MAX_CONSTANT; j++) {
978 if (ifs->constant_flags[j] == 0x0) {
979 memcpy(ifs->constants[j],
980 p->immediates[i],
981 4 * sizeof(float));
982 /*printf("immediate %d maps to const %d\n", i, j);*/
983 ifs->constant_flags[j] = 0xf; /* all four comps used */
984 p->immediates_map[i] = j;
985 ifs->num_constants = MAX2(ifs->num_constants, j + 1);
986 break;
987 }
988 }
989 }
990
991 p->first_instruction = FALSE;
992 }
993
994 i915_translate_instruction(p, &parse.FullToken.FullInstruction);
995 break;
996
997 default:
998 assert( 0 );
999 }
1000
1001 } /* while */
1002
1003 tgsi_parse_free (&parse);
1004 }
1005
1006
1007 static struct i915_fp_compile *
1008 i915_init_compile(struct i915_context *i915,
1009 struct i915_fragment_shader *ifs)
1010 {
1011 struct i915_fp_compile *p = CALLOC_STRUCT(i915_fp_compile);
1012
1013 p->shader = ifs;
1014
1015 /* Put new constants at end of const buffer, growing downward.
1016 * The problem is we don't know how many user-defined constants might
1017 * be specified with pipe->set_constant_buffer().
1018 * Should pre-scan the user's program to determine the highest-numbered
1019 * constant referenced.
1020 */
1021 ifs->num_constants = 0;
1022 memset(ifs->constant_flags, 0, sizeof(ifs->constant_flags));
1023
1024 p->first_instruction = TRUE;
1025
1026 p->nr_tex_indirect = 1; /* correct? */
1027 p->nr_tex_insn = 0;
1028 p->nr_alu_insn = 0;
1029 p->nr_decl_insn = 0;
1030
1031 p->csr = p->program;
1032 p->decl = p->declarations;
1033 p->decl_s = 0;
1034 p->decl_t = 0;
1035 p->temp_flag = ~0x0 << I915_MAX_TEMPORARY;
1036 p->utemp_flag = ~0x7;
1037
1038 p->wpos_tex = -1;
1039
1040 /* initialize the first program word */
1041 *(p->decl++) = _3DSTATE_PIXEL_SHADER_PROGRAM;
1042
1043 return p;
1044 }
1045
1046
1047 /* Copy compile results to the fragment program struct and destroy the
1048 * compilation context.
1049 */
1050 static void
1051 i915_fini_compile(struct i915_context *i915, struct i915_fp_compile *p)
1052 {
1053 struct i915_fragment_shader *ifs = p->shader;
1054 unsigned long program_size = (unsigned long) (p->csr - p->program);
1055 unsigned long decl_size = (unsigned long) (p->decl - p->declarations);
1056
1057 if (p->nr_tex_indirect > I915_MAX_TEX_INDIRECT)
1058 i915_program_error(p, "Exceeded max nr indirect texture lookups");
1059
1060 if (p->nr_tex_insn > I915_MAX_TEX_INSN)
1061 i915_program_error(p, "Exceeded max TEX instructions");
1062
1063 if (p->nr_alu_insn > I915_MAX_ALU_INSN)
1064 i915_program_error(p, "Exceeded max ALU instructions");
1065
1066 if (p->nr_decl_insn > I915_MAX_DECL_INSN)
1067 i915_program_error(p, "Exceeded max DECL instructions");
1068
1069 if (p->error) {
1070 p->NumNativeInstructions = 0;
1071 p->NumNativeAluInstructions = 0;
1072 p->NumNativeTexInstructions = 0;
1073 p->NumNativeTexIndirections = 0;
1074
1075 i915_use_passthrough_shader(ifs);
1076 }
1077 else {
1078 p->NumNativeInstructions
1079 = p->nr_alu_insn + p->nr_tex_insn + p->nr_decl_insn;
1080 p->NumNativeAluInstructions = p->nr_alu_insn;
1081 p->NumNativeTexInstructions = p->nr_tex_insn;
1082 p->NumNativeTexIndirections = p->nr_tex_indirect;
1083
1084 /* patch in the program length */
1085 p->declarations[0] |= program_size + decl_size - 2;
1086
1087 /* Copy compilation results to fragment program struct:
1088 */
1089 assert(!ifs->program);
1090 ifs->program
1091 = (uint *) MALLOC((program_size + decl_size) * sizeof(uint));
1092 if (ifs->program) {
1093 ifs->program_len = program_size + decl_size;
1094
1095 memcpy(ifs->program,
1096 p->declarations,
1097 decl_size * sizeof(uint));
1098
1099 memcpy(ifs->program + decl_size,
1100 p->program,
1101 program_size * sizeof(uint));
1102 }
1103 }
1104
1105 /* Release the compilation struct:
1106 */
1107 FREE(p);
1108 }
1109
1110
1111 /**
1112 * Find an unused texture coordinate slot to use for fragment WPOS.
1113 * Update p->fp->wpos_tex with the result (-1 if no used texcoord slot is found).
1114 */
1115 static void
1116 i915_find_wpos_space(struct i915_fp_compile *p)
1117 {
1118 #if 0
1119 const uint inputs
1120 = p->shader->inputs_read | (1 << TGSI_ATTRIB_POS); /*XXX hack*/
1121 uint i;
1122
1123 p->wpos_tex = -1;
1124
1125 if (inputs & (1 << TGSI_ATTRIB_POS)) {
1126 for (i = 0; i < I915_TEX_UNITS; i++) {
1127 if ((inputs & (1 << (TGSI_ATTRIB_TEX0 + i))) == 0) {
1128 p->wpos_tex = i;
1129 return;
1130 }
1131 }
1132
1133 i915_program_error(p, "No free texcoord for wpos value");
1134 }
1135 #else
1136 if (p->shader->info.input_semantic_name[0] == TGSI_SEMANTIC_POSITION) {
1137 /* frag shader using the fragment position input */
1138 #if 0
1139 assert(0);
1140 #endif
1141 }
1142 #endif
1143 }
1144
1145
1146
1147
1148 /**
1149 * Rather than trying to intercept and jiggle depth writes during
1150 * emit, just move the value into its correct position at the end of
1151 * the program:
1152 */
1153 static void
1154 i915_fixup_depth_write(struct i915_fp_compile *p)
1155 {
1156 /* XXX assuming pos/depth is always in output[0] */
1157 if (p->shader->info.output_semantic_name[0] == TGSI_SEMANTIC_POSITION) {
1158 const uint depth = UREG(REG_TYPE_OD, 0);
1159
1160 i915_emit_arith(p,
1161 A0_MOV, /* opcode */
1162 depth, /* dest reg */
1163 A0_DEST_CHANNEL_W, /* write mask */
1164 0, /* saturate? */
1165 swizzle(depth, X, Y, Z, Z), /* src0 */
1166 0, 0 /* src1, src2 */);
1167 }
1168 }
1169
1170
1171 void
1172 i915_translate_fragment_program( struct i915_context *i915,
1173 struct i915_fragment_shader *fs)
1174 {
1175 struct i915_fp_compile *p = i915_init_compile(i915, fs);
1176 const struct tgsi_token *tokens = fs->state.tokens;
1177
1178 i915_find_wpos_space(p);
1179
1180 #if 0
1181 tgsi_dump(tokens, 0);
1182 #endif
1183
1184 i915_translate_instructions(p, tokens);
1185 i915_fixup_depth_write(p);
1186
1187 i915_fini_compile(i915, p);
1188 }