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Merge commit 'origin/gallium-master-merge'
[mesa.git] / src / gallium / drivers / i915simple / i915_fpc_translate.c
1 /**************************************************************************
2 *
3 * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29 #include <stdarg.h>
30
31 #include "i915_reg.h"
32 #include "i915_context.h"
33 #include "i915_fpc.h"
34
35 #include "pipe/p_shader_tokens.h"
36 #include "util/u_math.h"
37 #include "util/u_memory.h"
38 #include "util/u_string.h"
39 #include "tgsi/tgsi_parse.h"
40 #include "tgsi/tgsi_dump.h"
41
42 #include "draw/draw_vertex.h"
43
44
45 /**
46 * Simple pass-through fragment shader to use when we don't have
47 * a real shader (or it fails to compile for some reason).
48 */
49 static unsigned passthrough[] =
50 {
51 _3DSTATE_PIXEL_SHADER_PROGRAM | ((2*3)-1),
52
53 /* declare input color:
54 */
55 (D0_DCL |
56 (REG_TYPE_T << D0_TYPE_SHIFT) |
57 (T_DIFFUSE << D0_NR_SHIFT) |
58 D0_CHANNEL_ALL),
59 0,
60 0,
61
62 /* move to output color:
63 */
64 (A0_MOV |
65 (REG_TYPE_OC << A0_DEST_TYPE_SHIFT) |
66 A0_DEST_CHANNEL_ALL |
67 (REG_TYPE_T << A0_SRC0_TYPE_SHIFT) |
68 (T_DIFFUSE << A0_SRC0_NR_SHIFT)),
69 0x01230000, /* .xyzw */
70 0
71 };
72
73
74 /* 1, -1/3!, 1/5!, -1/7! */
75 static const float sin_constants[4] = { 1.0,
76 -1.0f / (3 * 2 * 1),
77 1.0f / (5 * 4 * 3 * 2 * 1),
78 -1.0f / (7 * 6 * 5 * 4 * 3 * 2 * 1)
79 };
80
81 /* 1, -1/2!, 1/4!, -1/6! */
82 static const float cos_constants[4] = { 1.0,
83 -1.0f / (2 * 1),
84 1.0f / (4 * 3 * 2 * 1),
85 -1.0f / (6 * 5 * 4 * 3 * 2 * 1)
86 };
87
88
89
90 /**
91 * component-wise negation of ureg
92 */
93 static INLINE int
94 negate(int reg, int x, int y, int z, int w)
95 {
96 /* Another neat thing about the UREG representation */
97 return reg ^ (((x & 1) << UREG_CHANNEL_X_NEGATE_SHIFT) |
98 ((y & 1) << UREG_CHANNEL_Y_NEGATE_SHIFT) |
99 ((z & 1) << UREG_CHANNEL_Z_NEGATE_SHIFT) |
100 ((w & 1) << UREG_CHANNEL_W_NEGATE_SHIFT));
101 }
102
103
104 /**
105 * In the event of a translation failure, we'll generate a simple color
106 * pass-through program.
107 */
108 static void
109 i915_use_passthrough_shader(struct i915_fragment_shader *fs)
110 {
111 fs->program = (uint *) MALLOC(sizeof(passthrough));
112 if (fs->program) {
113 memcpy(fs->program, passthrough, sizeof(passthrough));
114 fs->program_len = Elements(passthrough);
115 }
116 fs->num_constants = 0;
117 }
118
119
120 void
121 i915_program_error(struct i915_fp_compile *p, const char *msg, ...)
122 {
123 va_list args;
124 char buffer[1024];
125
126 debug_printf("i915_program_error: ");
127 va_start( args, msg );
128 util_vsnprintf( buffer, sizeof(buffer), msg, args );
129 va_end( args );
130 debug_printf(buffer);
131 debug_printf("\n");
132
133 p->error = 1;
134 }
135
136
137
138 /**
139 * Construct a ureg for the given source register. Will emit
140 * constants, apply swizzling and negation as needed.
141 */
142 static uint
143 src_vector(struct i915_fp_compile *p,
144 const struct tgsi_full_src_register *source)
145 {
146 uint index = source->SrcRegister.Index;
147 uint src = 0, sem_name, sem_ind;
148
149 switch (source->SrcRegister.File) {
150 case TGSI_FILE_TEMPORARY:
151 if (source->SrcRegister.Index >= I915_MAX_TEMPORARY) {
152 i915_program_error(p, "Exceeded max temporary reg");
153 return 0;
154 }
155 src = UREG(REG_TYPE_R, index);
156 break;
157 case TGSI_FILE_INPUT:
158 /* XXX: Packing COL1, FOGC into a single attribute works for
159 * texenv programs, but will fail for real fragment programs
160 * that use these attributes and expect them to be a full 4
161 * components wide. Could use a texcoord to pass these
162 * attributes if necessary, but that won't work in the general
163 * case.
164 *
165 * We also use a texture coordinate to pass wpos when possible.
166 */
167
168 sem_name = p->shader->info.input_semantic_name[index];
169 sem_ind = p->shader->info.input_semantic_index[index];
170
171 switch (sem_name) {
172 case TGSI_SEMANTIC_POSITION:
173 debug_printf("SKIP SEM POS\n");
174 /*
175 assert(p->wpos_tex != -1);
176 src = i915_emit_decl(p, REG_TYPE_T, p->wpos_tex, D0_CHANNEL_ALL);
177 */
178 break;
179 case TGSI_SEMANTIC_COLOR:
180 if (sem_ind == 0) {
181 src = i915_emit_decl(p, REG_TYPE_T, T_DIFFUSE, D0_CHANNEL_ALL);
182 }
183 else {
184 /* secondary color */
185 assert(sem_ind == 1);
186 src = i915_emit_decl(p, REG_TYPE_T, T_SPECULAR, D0_CHANNEL_XYZ);
187 src = swizzle(src, X, Y, Z, ONE);
188 }
189 break;
190 case TGSI_SEMANTIC_FOG:
191 src = i915_emit_decl(p, REG_TYPE_T, T_FOG_W, D0_CHANNEL_W);
192 src = swizzle(src, W, W, W, W);
193 break;
194 case TGSI_SEMANTIC_GENERIC:
195 /* usually a texcoord */
196 src = i915_emit_decl(p, REG_TYPE_T, T_TEX0 + sem_ind, D0_CHANNEL_ALL);
197 break;
198 default:
199 i915_program_error(p, "Bad source->Index");
200 return 0;
201 }
202 break;
203
204 case TGSI_FILE_IMMEDIATE:
205 assert(index < p->num_immediates);
206 index = p->immediates_map[index];
207 /* fall-through */
208 case TGSI_FILE_CONSTANT:
209 src = UREG(REG_TYPE_CONST, index);
210 break;
211
212 default:
213 i915_program_error(p, "Bad source->File");
214 return 0;
215 }
216
217 if (source->SrcRegister.Extended) {
218 src = swizzle(src,
219 source->SrcRegisterExtSwz.ExtSwizzleX,
220 source->SrcRegisterExtSwz.ExtSwizzleY,
221 source->SrcRegisterExtSwz.ExtSwizzleZ,
222 source->SrcRegisterExtSwz.ExtSwizzleW);
223 }
224 else {
225 src = swizzle(src,
226 source->SrcRegister.SwizzleX,
227 source->SrcRegister.SwizzleY,
228 source->SrcRegister.SwizzleZ,
229 source->SrcRegister.SwizzleW);
230 }
231
232
233 /* There's both negate-all-components and per-component negation.
234 * Try to handle both here.
235 */
236 {
237 int nx = source->SrcRegisterExtSwz.NegateX;
238 int ny = source->SrcRegisterExtSwz.NegateY;
239 int nz = source->SrcRegisterExtSwz.NegateZ;
240 int nw = source->SrcRegisterExtSwz.NegateW;
241 if (source->SrcRegister.Negate) {
242 nx = !nx;
243 ny = !ny;
244 nz = !nz;
245 nw = !nw;
246 }
247 src = negate(src, nx, ny, nz, nw);
248 }
249
250 /* no abs() or post-abs negation */
251 #if 0
252 /* XXX assertions disabled to allow arbfplight.c to run */
253 /* XXX enable these assertions, or fix things */
254 assert(!source->SrcRegisterExtMod.Absolute);
255 assert(!source->SrcRegisterExtMod.Negate);
256 #endif
257 return src;
258 }
259
260
261 /**
262 * Construct a ureg for a destination register.
263 */
264 static uint
265 get_result_vector(struct i915_fp_compile *p,
266 const struct tgsi_full_dst_register *dest)
267 {
268 switch (dest->DstRegister.File) {
269 case TGSI_FILE_OUTPUT:
270 {
271 uint sem_name = p->shader->info.output_semantic_name[dest->DstRegister.Index];
272 switch (sem_name) {
273 case TGSI_SEMANTIC_POSITION:
274 return UREG(REG_TYPE_OD, 0);
275 case TGSI_SEMANTIC_COLOR:
276 return UREG(REG_TYPE_OC, 0);
277 default:
278 i915_program_error(p, "Bad inst->DstReg.Index/semantics");
279 return 0;
280 }
281 }
282 case TGSI_FILE_TEMPORARY:
283 return UREG(REG_TYPE_R, dest->DstRegister.Index);
284 default:
285 i915_program_error(p, "Bad inst->DstReg.File");
286 return 0;
287 }
288 }
289
290
291 /**
292 * Compute flags for saturation and writemask.
293 */
294 static uint
295 get_result_flags(const struct tgsi_full_instruction *inst)
296 {
297 const uint writeMask
298 = inst->FullDstRegisters[0].DstRegister.WriteMask;
299 uint flags = 0x0;
300
301 if (inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE)
302 flags |= A0_DEST_SATURATE;
303
304 if (writeMask & TGSI_WRITEMASK_X)
305 flags |= A0_DEST_CHANNEL_X;
306 if (writeMask & TGSI_WRITEMASK_Y)
307 flags |= A0_DEST_CHANNEL_Y;
308 if (writeMask & TGSI_WRITEMASK_Z)
309 flags |= A0_DEST_CHANNEL_Z;
310 if (writeMask & TGSI_WRITEMASK_W)
311 flags |= A0_DEST_CHANNEL_W;
312
313 return flags;
314 }
315
316
317 /**
318 * Convert TGSI_TEXTURE_x token to DO_SAMPLE_TYPE_x token
319 */
320 static uint
321 translate_tex_src_target(struct i915_fp_compile *p, uint tex)
322 {
323 switch (tex) {
324 case TGSI_TEXTURE_1D:
325 return D0_SAMPLE_TYPE_2D;
326 case TGSI_TEXTURE_2D:
327 return D0_SAMPLE_TYPE_2D;
328 case TGSI_TEXTURE_RECT:
329 return D0_SAMPLE_TYPE_2D;
330 case TGSI_TEXTURE_3D:
331 return D0_SAMPLE_TYPE_VOLUME;
332 case TGSI_TEXTURE_CUBE:
333 return D0_SAMPLE_TYPE_CUBE;
334 default:
335 i915_program_error(p, "TexSrc type");
336 return 0;
337 }
338 }
339
340
341 /**
342 * Generate texel lookup instruction.
343 */
344 static void
345 emit_tex(struct i915_fp_compile *p,
346 const struct tgsi_full_instruction *inst,
347 uint opcode)
348 {
349 uint texture = inst->InstructionExtTexture.Texture;
350 uint unit = inst->FullSrcRegisters[1].SrcRegister.Index;
351 uint tex = translate_tex_src_target( p, texture );
352 uint sampler = i915_emit_decl(p, REG_TYPE_S, unit, tex);
353 uint coord = src_vector( p, &inst->FullSrcRegisters[0]);
354
355 i915_emit_texld( p,
356 get_result_vector( p, &inst->FullDstRegisters[0] ),
357 get_result_flags( inst ),
358 sampler,
359 coord,
360 opcode);
361 }
362
363
364 /**
365 * Generate a simple arithmetic instruction
366 * \param opcode the i915 opcode
367 * \param numArgs the number of input/src arguments
368 */
369 static void
370 emit_simple_arith(struct i915_fp_compile *p,
371 const struct tgsi_full_instruction *inst,
372 uint opcode, uint numArgs)
373 {
374 uint arg1, arg2, arg3;
375
376 assert(numArgs <= 3);
377
378 arg1 = (numArgs < 1) ? 0 : src_vector( p, &inst->FullSrcRegisters[0] );
379 arg2 = (numArgs < 2) ? 0 : src_vector( p, &inst->FullSrcRegisters[1] );
380 arg3 = (numArgs < 3) ? 0 : src_vector( p, &inst->FullSrcRegisters[2] );
381
382 i915_emit_arith( p,
383 opcode,
384 get_result_vector( p, &inst->FullDstRegisters[0]),
385 get_result_flags( inst ), 0,
386 arg1,
387 arg2,
388 arg3 );
389 }
390
391
392 /** As above, but swap the first two src regs */
393 static void
394 emit_simple_arith_swap2(struct i915_fp_compile *p,
395 const struct tgsi_full_instruction *inst,
396 uint opcode, uint numArgs)
397 {
398 struct tgsi_full_instruction inst2;
399
400 assert(numArgs == 2);
401
402 /* transpose first two registers */
403 inst2 = *inst;
404 inst2.FullSrcRegisters[0] = inst->FullSrcRegisters[1];
405 inst2.FullSrcRegisters[1] = inst->FullSrcRegisters[0];
406
407 emit_simple_arith(p, &inst2, opcode, numArgs);
408 }
409
410
411 #ifndef M_PI
412 #define M_PI 3.14159265358979323846
413 #endif
414
415 /*
416 * Translate TGSI instruction to i915 instruction.
417 *
418 * Possible concerns:
419 *
420 * SIN, COS -- could use another taylor step?
421 * LIT -- results seem a little different to sw mesa
422 * LOG -- different to mesa on negative numbers, but this is conformant.
423 */
424 static void
425 i915_translate_instruction(struct i915_fp_compile *p,
426 const struct tgsi_full_instruction *inst)
427 {
428 uint writemask;
429 uint src0, src1, src2, flags;
430 uint tmp = 0;
431
432 switch (inst->Instruction.Opcode) {
433 case TGSI_OPCODE_ABS:
434 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
435 i915_emit_arith(p,
436 A0_MAX,
437 get_result_vector(p, &inst->FullDstRegisters[0]),
438 get_result_flags(inst), 0,
439 src0, negate(src0, 1, 1, 1, 1), 0);
440 break;
441
442 case TGSI_OPCODE_ADD:
443 emit_simple_arith(p, inst, A0_ADD, 2);
444 break;
445
446 case TGSI_OPCODE_CMP:
447 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
448 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
449 src2 = src_vector(p, &inst->FullSrcRegisters[2]);
450 i915_emit_arith(p, A0_CMP,
451 get_result_vector(p, &inst->FullDstRegisters[0]),
452 get_result_flags(inst),
453 0, src0, src2, src1); /* NOTE: order of src2, src1 */
454 break;
455
456 case TGSI_OPCODE_COS:
457 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
458 tmp = i915_get_utemp(p);
459
460 i915_emit_arith(p,
461 A0_MUL,
462 tmp, A0_DEST_CHANNEL_X, 0,
463 src0, i915_emit_const1f(p, 1.0f / (float) (M_PI * 2.0)), 0);
464
465 i915_emit_arith(p, A0_MOD, tmp, A0_DEST_CHANNEL_X, 0, tmp, 0, 0);
466
467 /* By choosing different taylor constants, could get rid of this mul:
468 */
469 i915_emit_arith(p,
470 A0_MUL,
471 tmp, A0_DEST_CHANNEL_X, 0,
472 tmp, i915_emit_const1f(p, (float) (M_PI * 2.0)), 0);
473
474 /*
475 * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1
476 * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, 1
477 * t0 = MUL t0.xxz1 t0.z111 ; x^6 x^4 x^2 1
478 * result = DP4 t0, cos_constants
479 */
480 i915_emit_arith(p,
481 A0_MUL,
482 tmp, A0_DEST_CHANNEL_XY, 0,
483 swizzle(tmp, X, X, ONE, ONE),
484 swizzle(tmp, X, ONE, ONE, ONE), 0);
485
486 i915_emit_arith(p,
487 A0_MUL,
488 tmp, A0_DEST_CHANNEL_XYZ, 0,
489 swizzle(tmp, X, Y, X, ONE),
490 swizzle(tmp, X, X, ONE, ONE), 0);
491
492 i915_emit_arith(p,
493 A0_MUL,
494 tmp, A0_DEST_CHANNEL_XYZ, 0,
495 swizzle(tmp, X, X, Z, ONE),
496 swizzle(tmp, Z, ONE, ONE, ONE), 0);
497
498 i915_emit_arith(p,
499 A0_DP4,
500 get_result_vector(p, &inst->FullDstRegisters[0]),
501 get_result_flags(inst), 0,
502 swizzle(tmp, ONE, Z, Y, X),
503 i915_emit_const4fv(p, cos_constants), 0);
504 break;
505
506 case TGSI_OPCODE_DP3:
507 emit_simple_arith(p, inst, A0_DP3, 2);
508 break;
509
510 case TGSI_OPCODE_DP4:
511 emit_simple_arith(p, inst, A0_DP4, 2);
512 break;
513
514 case TGSI_OPCODE_DPH:
515 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
516 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
517
518 i915_emit_arith(p,
519 A0_DP4,
520 get_result_vector(p, &inst->FullDstRegisters[0]),
521 get_result_flags(inst), 0,
522 swizzle(src0, X, Y, Z, ONE), src1, 0);
523 break;
524
525 case TGSI_OPCODE_DST:
526 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
527 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
528
529 /* result[0] = 1 * 1;
530 * result[1] = a[1] * b[1];
531 * result[2] = a[2] * 1;
532 * result[3] = 1 * b[3];
533 */
534 i915_emit_arith(p,
535 A0_MUL,
536 get_result_vector(p, &inst->FullDstRegisters[0]),
537 get_result_flags(inst), 0,
538 swizzle(src0, ONE, Y, Z, ONE),
539 swizzle(src1, ONE, Y, ONE, W), 0);
540 break;
541
542 case TGSI_OPCODE_END:
543 /* no-op */
544 break;
545
546 case TGSI_OPCODE_EX2:
547 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
548
549 i915_emit_arith(p,
550 A0_EXP,
551 get_result_vector(p, &inst->FullDstRegisters[0]),
552 get_result_flags(inst), 0,
553 swizzle(src0, X, X, X, X), 0, 0);
554 break;
555
556 case TGSI_OPCODE_FLR:
557 emit_simple_arith(p, inst, A0_FLR, 1);
558 break;
559
560 case TGSI_OPCODE_FRC:
561 emit_simple_arith(p, inst, A0_FRC, 1);
562 break;
563
564 case TGSI_OPCODE_KIL:
565 /* kill if src[0].x < 0 || src[0].y < 0 ... */
566 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
567 tmp = i915_get_utemp(p);
568
569 i915_emit_texld(p,
570 tmp, /* dest reg: a dummy reg */
571 A0_DEST_CHANNEL_ALL, /* dest writemask */
572 0, /* sampler */
573 src0, /* coord*/
574 T0_TEXKILL); /* opcode */
575 break;
576
577 case TGSI_OPCODE_KILP:
578 assert(0); /* not tested yet */
579 break;
580
581 case TGSI_OPCODE_LG2:
582 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
583
584 i915_emit_arith(p,
585 A0_LOG,
586 get_result_vector(p, &inst->FullDstRegisters[0]),
587 get_result_flags(inst), 0,
588 swizzle(src0, X, X, X, X), 0, 0);
589 break;
590
591 case TGSI_OPCODE_LIT:
592 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
593 tmp = i915_get_utemp(p);
594
595 /* tmp = max( a.xyzw, a.00zw )
596 * XXX: Clamp tmp.w to -128..128
597 * tmp.y = log(tmp.y)
598 * tmp.y = tmp.w * tmp.y
599 * tmp.y = exp(tmp.y)
600 * result = cmp (a.11-x1, a.1x01, a.1xy1 )
601 */
602 i915_emit_arith(p, A0_MAX, tmp, A0_DEST_CHANNEL_ALL, 0,
603 src0, swizzle(src0, ZERO, ZERO, Z, W), 0);
604
605 i915_emit_arith(p, A0_LOG, tmp, A0_DEST_CHANNEL_Y, 0,
606 swizzle(tmp, Y, Y, Y, Y), 0, 0);
607
608 i915_emit_arith(p, A0_MUL, tmp, A0_DEST_CHANNEL_Y, 0,
609 swizzle(tmp, ZERO, Y, ZERO, ZERO),
610 swizzle(tmp, ZERO, W, ZERO, ZERO), 0);
611
612 i915_emit_arith(p, A0_EXP, tmp, A0_DEST_CHANNEL_Y, 0,
613 swizzle(tmp, Y, Y, Y, Y), 0, 0);
614
615 i915_emit_arith(p, A0_CMP,
616 get_result_vector(p, &inst->FullDstRegisters[0]),
617 get_result_flags(inst), 0,
618 negate(swizzle(tmp, ONE, ONE, X, ONE), 0, 0, 1, 0),
619 swizzle(tmp, ONE, X, ZERO, ONE),
620 swizzle(tmp, ONE, X, Y, ONE));
621
622 break;
623
624 case TGSI_OPCODE_LRP:
625 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
626 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
627 src2 = src_vector(p, &inst->FullSrcRegisters[2]);
628 flags = get_result_flags(inst);
629 tmp = i915_get_utemp(p);
630
631 /* b*a + c*(1-a)
632 *
633 * b*a + c - ca
634 *
635 * tmp = b*a + c,
636 * result = (-c)*a + tmp
637 */
638 i915_emit_arith(p, A0_MAD, tmp,
639 flags & A0_DEST_CHANNEL_ALL, 0, src1, src0, src2);
640
641 i915_emit_arith(p, A0_MAD,
642 get_result_vector(p, &inst->FullDstRegisters[0]),
643 flags, 0, negate(src2, 1, 1, 1, 1), src0, tmp);
644 break;
645
646 case TGSI_OPCODE_MAD:
647 emit_simple_arith(p, inst, A0_MAD, 3);
648 break;
649
650 case TGSI_OPCODE_MAX:
651 emit_simple_arith(p, inst, A0_MAX, 2);
652 break;
653
654 case TGSI_OPCODE_MIN:
655 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
656 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
657 tmp = i915_get_utemp(p);
658 flags = get_result_flags(inst);
659
660 i915_emit_arith(p,
661 A0_MAX,
662 tmp, flags & A0_DEST_CHANNEL_ALL, 0,
663 negate(src0, 1, 1, 1, 1),
664 negate(src1, 1, 1, 1, 1), 0);
665
666 i915_emit_arith(p,
667 A0_MOV,
668 get_result_vector(p, &inst->FullDstRegisters[0]),
669 flags, 0, negate(tmp, 1, 1, 1, 1), 0, 0);
670 break;
671
672 case TGSI_OPCODE_MOV:
673 case TGSI_OPCODE_SWZ:
674 emit_simple_arith(p, inst, A0_MOV, 1);
675 break;
676
677 case TGSI_OPCODE_MUL:
678 emit_simple_arith(p, inst, A0_MUL, 2);
679 break;
680
681 case TGSI_OPCODE_POW:
682 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
683 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
684 tmp = i915_get_utemp(p);
685 flags = get_result_flags(inst);
686
687 /* XXX: masking on intermediate values, here and elsewhere.
688 */
689 i915_emit_arith(p,
690 A0_LOG,
691 tmp, A0_DEST_CHANNEL_X, 0,
692 swizzle(src0, X, X, X, X), 0, 0);
693
694 i915_emit_arith(p, A0_MUL, tmp, A0_DEST_CHANNEL_X, 0, tmp, src1, 0);
695
696 i915_emit_arith(p,
697 A0_EXP,
698 get_result_vector(p, &inst->FullDstRegisters[0]),
699 flags, 0, swizzle(tmp, X, X, X, X), 0, 0);
700 break;
701
702 case TGSI_OPCODE_RET:
703 /* XXX: no-op? */
704 break;
705
706 case TGSI_OPCODE_RCP:
707 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
708
709 i915_emit_arith(p,
710 A0_RCP,
711 get_result_vector(p, &inst->FullDstRegisters[0]),
712 get_result_flags(inst), 0,
713 swizzle(src0, X, X, X, X), 0, 0);
714 break;
715
716 case TGSI_OPCODE_RSQ:
717 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
718
719 i915_emit_arith(p,
720 A0_RSQ,
721 get_result_vector(p, &inst->FullDstRegisters[0]),
722 get_result_flags(inst), 0,
723 swizzle(src0, X, X, X, X), 0, 0);
724 break;
725
726 case TGSI_OPCODE_SCS:
727 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
728 tmp = i915_get_utemp(p);
729
730 /*
731 * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1
732 * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, x
733 * t1 = MUL t0.xyyw t0.yz11 ; x^7 x^5 x^3 x
734 * scs.x = DP4 t1, sin_constants
735 * t1 = MUL t0.xxz1 t0.z111 ; x^6 x^4 x^2 1
736 * scs.y = DP4 t1, cos_constants
737 */
738 i915_emit_arith(p,
739 A0_MUL,
740 tmp, A0_DEST_CHANNEL_XY, 0,
741 swizzle(src0, X, X, ONE, ONE),
742 swizzle(src0, X, ONE, ONE, ONE), 0);
743
744 i915_emit_arith(p,
745 A0_MUL,
746 tmp, A0_DEST_CHANNEL_ALL, 0,
747 swizzle(tmp, X, Y, X, Y),
748 swizzle(tmp, X, X, ONE, ONE), 0);
749
750 writemask = inst->FullDstRegisters[0].DstRegister.WriteMask;
751
752 if (writemask & TGSI_WRITEMASK_Y) {
753 uint tmp1;
754
755 if (writemask & TGSI_WRITEMASK_X)
756 tmp1 = i915_get_utemp(p);
757 else
758 tmp1 = tmp;
759
760 i915_emit_arith(p,
761 A0_MUL,
762 tmp1, A0_DEST_CHANNEL_ALL, 0,
763 swizzle(tmp, X, Y, Y, W),
764 swizzle(tmp, X, Z, ONE, ONE), 0);
765
766 i915_emit_arith(p,
767 A0_DP4,
768 get_result_vector(p, &inst->FullDstRegisters[0]),
769 A0_DEST_CHANNEL_Y, 0,
770 swizzle(tmp1, W, Z, Y, X),
771 i915_emit_const4fv(p, sin_constants), 0);
772 }
773
774 if (writemask & TGSI_WRITEMASK_X) {
775 i915_emit_arith(p,
776 A0_MUL,
777 tmp, A0_DEST_CHANNEL_XYZ, 0,
778 swizzle(tmp, X, X, Z, ONE),
779 swizzle(tmp, Z, ONE, ONE, ONE), 0);
780
781 i915_emit_arith(p,
782 A0_DP4,
783 get_result_vector(p, &inst->FullDstRegisters[0]),
784 A0_DEST_CHANNEL_X, 0,
785 swizzle(tmp, ONE, Z, Y, X),
786 i915_emit_const4fv(p, cos_constants), 0);
787 }
788 break;
789
790 case TGSI_OPCODE_SGE:
791 emit_simple_arith(p, inst, A0_SGE, 2);
792 break;
793
794 case TGSI_OPCODE_SLE:
795 /* like SGE, but swap reg0, reg1 */
796 emit_simple_arith_swap2(p, inst, A0_SGE, 2);
797 break;
798
799 case TGSI_OPCODE_SIN:
800 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
801 tmp = i915_get_utemp(p);
802
803 i915_emit_arith(p,
804 A0_MUL,
805 tmp, A0_DEST_CHANNEL_X, 0,
806 src0, i915_emit_const1f(p, 1.0f / (float) (M_PI * 2.0)), 0);
807
808 i915_emit_arith(p, A0_MOD, tmp, A0_DEST_CHANNEL_X, 0, tmp, 0, 0);
809
810 /* By choosing different taylor constants, could get rid of this mul:
811 */
812 i915_emit_arith(p,
813 A0_MUL,
814 tmp, A0_DEST_CHANNEL_X, 0,
815 tmp, i915_emit_const1f(p, (float) (M_PI * 2.0)), 0);
816
817 /*
818 * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1
819 * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, x
820 * t1 = MUL t0.xyyw t0.yz11 ; x^7 x^5 x^3 x
821 * result = DP4 t1.wzyx, sin_constants
822 */
823 i915_emit_arith(p,
824 A0_MUL,
825 tmp, A0_DEST_CHANNEL_XY, 0,
826 swizzle(tmp, X, X, ONE, ONE),
827 swizzle(tmp, X, ONE, ONE, ONE), 0);
828
829 i915_emit_arith(p,
830 A0_MUL,
831 tmp, A0_DEST_CHANNEL_ALL, 0,
832 swizzle(tmp, X, Y, X, Y),
833 swizzle(tmp, X, X, ONE, ONE), 0);
834
835 i915_emit_arith(p,
836 A0_MUL,
837 tmp, A0_DEST_CHANNEL_ALL, 0,
838 swizzle(tmp, X, Y, Y, W),
839 swizzle(tmp, X, Z, ONE, ONE), 0);
840
841 i915_emit_arith(p,
842 A0_DP4,
843 get_result_vector(p, &inst->FullDstRegisters[0]),
844 get_result_flags(inst), 0,
845 swizzle(tmp, W, Z, Y, X),
846 i915_emit_const4fv(p, sin_constants), 0);
847 break;
848
849 case TGSI_OPCODE_SLT:
850 emit_simple_arith(p, inst, A0_SLT, 2);
851 break;
852
853 case TGSI_OPCODE_SGT:
854 /* like SLT, but swap reg0, reg1 */
855 emit_simple_arith_swap2(p, inst, A0_SLT, 2);
856 break;
857
858 case TGSI_OPCODE_SUB:
859 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
860 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
861
862 i915_emit_arith(p,
863 A0_ADD,
864 get_result_vector(p, &inst->FullDstRegisters[0]),
865 get_result_flags(inst), 0,
866 src0, negate(src1, 1, 1, 1, 1), 0);
867 break;
868
869 case TGSI_OPCODE_TEX:
870 emit_tex(p, inst, T0_TEXLD);
871 break;
872
873 case TGSI_OPCODE_TXB:
874 emit_tex(p, inst, T0_TEXLDB);
875 break;
876
877 case TGSI_OPCODE_TXP:
878 emit_tex(p, inst, T0_TEXLDP);
879 break;
880
881 case TGSI_OPCODE_XPD:
882 /* Cross product:
883 * result.x = src0.y * src1.z - src0.z * src1.y;
884 * result.y = src0.z * src1.x - src0.x * src1.z;
885 * result.z = src0.x * src1.y - src0.y * src1.x;
886 * result.w = undef;
887 */
888 src0 = src_vector(p, &inst->FullSrcRegisters[0]);
889 src1 = src_vector(p, &inst->FullSrcRegisters[1]);
890 tmp = i915_get_utemp(p);
891
892 i915_emit_arith(p,
893 A0_MUL,
894 tmp, A0_DEST_CHANNEL_ALL, 0,
895 swizzle(src0, Z, X, Y, ONE),
896 swizzle(src1, Y, Z, X, ONE), 0);
897
898 i915_emit_arith(p,
899 A0_MAD,
900 get_result_vector(p, &inst->FullDstRegisters[0]),
901 get_result_flags(inst), 0,
902 swizzle(src0, Y, Z, X, ONE),
903 swizzle(src1, Z, X, Y, ONE),
904 negate(tmp, 1, 1, 1, 0));
905 break;
906
907 default:
908 i915_program_error(p, "bad opcode %d", inst->Instruction.Opcode);
909 p->error = 1;
910 return;
911 }
912
913 i915_release_utemps(p);
914 }
915
916
917 /**
918 * Translate TGSI fragment shader into i915 hardware instructions.
919 * \param p the translation state
920 * \param tokens the TGSI token array
921 */
922 static void
923 i915_translate_instructions(struct i915_fp_compile *p,
924 const struct tgsi_token *tokens)
925 {
926 struct i915_fragment_shader *ifs = p->shader;
927 struct tgsi_parse_context parse;
928
929 tgsi_parse_init( &parse, tokens );
930
931 while( !tgsi_parse_end_of_tokens( &parse ) ) {
932
933 tgsi_parse_token( &parse );
934
935 switch( parse.FullToken.Token.Type ) {
936 case TGSI_TOKEN_TYPE_DECLARATION:
937 if (parse.FullToken.FullDeclaration.Declaration.File
938 == TGSI_FILE_CONSTANT) {
939 uint i;
940 for (i = parse.FullToken.FullDeclaration.DeclarationRange.First;
941 i <= parse.FullToken.FullDeclaration.DeclarationRange.Last;
942 i++) {
943 assert(ifs->constant_flags[i] == 0x0);
944 ifs->constant_flags[i] = I915_CONSTFLAG_USER;
945 ifs->num_constants = MAX2(ifs->num_constants, i + 1);
946 }
947 }
948 else if (parse.FullToken.FullDeclaration.Declaration.File
949 == TGSI_FILE_TEMPORARY) {
950 uint i;
951 for (i = parse.FullToken.FullDeclaration.DeclarationRange.First;
952 i <= parse.FullToken.FullDeclaration.DeclarationRange.Last;
953 i++) {
954 assert(i < I915_MAX_TEMPORARY);
955 /* XXX just use shader->info->file_mask[TGSI_FILE_TEMPORARY] */
956 p->temp_flag |= (1 << i); /* mark temp as used */
957 }
958 }
959 break;
960
961 case TGSI_TOKEN_TYPE_IMMEDIATE:
962 {
963 const struct tgsi_full_immediate *imm
964 = &parse.FullToken.FullImmediate;
965 const uint pos = p->num_immediates++;
966 uint j;
967 for (j = 0; j < imm->Immediate.NrTokens - 1; j++) {
968 p->immediates[pos][j] = imm->u.ImmediateFloat32[j].Float;
969 }
970 }
971 break;
972
973 case TGSI_TOKEN_TYPE_INSTRUCTION:
974 if (p->first_instruction) {
975 /* resolve location of immediates */
976 uint i, j;
977 for (i = 0; i < p->num_immediates; i++) {
978 /* find constant slot for this immediate */
979 for (j = 0; j < I915_MAX_CONSTANT; j++) {
980 if (ifs->constant_flags[j] == 0x0) {
981 memcpy(ifs->constants[j],
982 p->immediates[i],
983 4 * sizeof(float));
984 /*printf("immediate %d maps to const %d\n", i, j);*/
985 ifs->constant_flags[j] = 0xf; /* all four comps used */
986 p->immediates_map[i] = j;
987 ifs->num_constants = MAX2(ifs->num_constants, j + 1);
988 break;
989 }
990 }
991 }
992
993 p->first_instruction = FALSE;
994 }
995
996 i915_translate_instruction(p, &parse.FullToken.FullInstruction);
997 break;
998
999 default:
1000 assert( 0 );
1001 }
1002
1003 } /* while */
1004
1005 tgsi_parse_free (&parse);
1006 }
1007
1008
1009 static struct i915_fp_compile *
1010 i915_init_compile(struct i915_context *i915,
1011 struct i915_fragment_shader *ifs)
1012 {
1013 struct i915_fp_compile *p = CALLOC_STRUCT(i915_fp_compile);
1014
1015 p->shader = ifs;
1016
1017 /* Put new constants at end of const buffer, growing downward.
1018 * The problem is we don't know how many user-defined constants might
1019 * be specified with pipe->set_constant_buffer().
1020 * Should pre-scan the user's program to determine the highest-numbered
1021 * constant referenced.
1022 */
1023 ifs->num_constants = 0;
1024 memset(ifs->constant_flags, 0, sizeof(ifs->constant_flags));
1025
1026 p->first_instruction = TRUE;
1027
1028 p->nr_tex_indirect = 1; /* correct? */
1029 p->nr_tex_insn = 0;
1030 p->nr_alu_insn = 0;
1031 p->nr_decl_insn = 0;
1032
1033 p->csr = p->program;
1034 p->decl = p->declarations;
1035 p->decl_s = 0;
1036 p->decl_t = 0;
1037 p->temp_flag = ~0x0 << I915_MAX_TEMPORARY;
1038 p->utemp_flag = ~0x7;
1039
1040 p->wpos_tex = -1;
1041
1042 /* initialize the first program word */
1043 *(p->decl++) = _3DSTATE_PIXEL_SHADER_PROGRAM;
1044
1045 return p;
1046 }
1047
1048
1049 /* Copy compile results to the fragment program struct and destroy the
1050 * compilation context.
1051 */
1052 static void
1053 i915_fini_compile(struct i915_context *i915, struct i915_fp_compile *p)
1054 {
1055 struct i915_fragment_shader *ifs = p->shader;
1056 unsigned long program_size = (unsigned long) (p->csr - p->program);
1057 unsigned long decl_size = (unsigned long) (p->decl - p->declarations);
1058
1059 if (p->nr_tex_indirect > I915_MAX_TEX_INDIRECT)
1060 i915_program_error(p, "Exceeded max nr indirect texture lookups");
1061
1062 if (p->nr_tex_insn > I915_MAX_TEX_INSN)
1063 i915_program_error(p, "Exceeded max TEX instructions");
1064
1065 if (p->nr_alu_insn > I915_MAX_ALU_INSN)
1066 i915_program_error(p, "Exceeded max ALU instructions");
1067
1068 if (p->nr_decl_insn > I915_MAX_DECL_INSN)
1069 i915_program_error(p, "Exceeded max DECL instructions");
1070
1071 if (p->error) {
1072 p->NumNativeInstructions = 0;
1073 p->NumNativeAluInstructions = 0;
1074 p->NumNativeTexInstructions = 0;
1075 p->NumNativeTexIndirections = 0;
1076
1077 i915_use_passthrough_shader(ifs);
1078 }
1079 else {
1080 p->NumNativeInstructions
1081 = p->nr_alu_insn + p->nr_tex_insn + p->nr_decl_insn;
1082 p->NumNativeAluInstructions = p->nr_alu_insn;
1083 p->NumNativeTexInstructions = p->nr_tex_insn;
1084 p->NumNativeTexIndirections = p->nr_tex_indirect;
1085
1086 /* patch in the program length */
1087 p->declarations[0] |= program_size + decl_size - 2;
1088
1089 /* Copy compilation results to fragment program struct:
1090 */
1091 assert(!ifs->program);
1092 ifs->program
1093 = (uint *) MALLOC((program_size + decl_size) * sizeof(uint));
1094 if (ifs->program) {
1095 ifs->program_len = program_size + decl_size;
1096
1097 memcpy(ifs->program,
1098 p->declarations,
1099 decl_size * sizeof(uint));
1100
1101 memcpy(ifs->program + decl_size,
1102 p->program,
1103 program_size * sizeof(uint));
1104 }
1105 }
1106
1107 /* Release the compilation struct:
1108 */
1109 FREE(p);
1110 }
1111
1112
1113 /**
1114 * Find an unused texture coordinate slot to use for fragment WPOS.
1115 * Update p->fp->wpos_tex with the result (-1 if no used texcoord slot is found).
1116 */
1117 static void
1118 i915_find_wpos_space(struct i915_fp_compile *p)
1119 {
1120 #if 0
1121 const uint inputs
1122 = p->shader->inputs_read | (1 << TGSI_ATTRIB_POS); /*XXX hack*/
1123 uint i;
1124
1125 p->wpos_tex = -1;
1126
1127 if (inputs & (1 << TGSI_ATTRIB_POS)) {
1128 for (i = 0; i < I915_TEX_UNITS; i++) {
1129 if ((inputs & (1 << (TGSI_ATTRIB_TEX0 + i))) == 0) {
1130 p->wpos_tex = i;
1131 return;
1132 }
1133 }
1134
1135 i915_program_error(p, "No free texcoord for wpos value");
1136 }
1137 #else
1138 if (p->shader->info.input_semantic_name[0] == TGSI_SEMANTIC_POSITION) {
1139 /* frag shader using the fragment position input */
1140 #if 0
1141 assert(0);
1142 #endif
1143 }
1144 #endif
1145 }
1146
1147
1148
1149
1150 /**
1151 * Rather than trying to intercept and jiggle depth writes during
1152 * emit, just move the value into its correct position at the end of
1153 * the program:
1154 */
1155 static void
1156 i915_fixup_depth_write(struct i915_fp_compile *p)
1157 {
1158 /* XXX assuming pos/depth is always in output[0] */
1159 if (p->shader->info.output_semantic_name[0] == TGSI_SEMANTIC_POSITION) {
1160 const uint depth = UREG(REG_TYPE_OD, 0);
1161
1162 i915_emit_arith(p,
1163 A0_MOV, /* opcode */
1164 depth, /* dest reg */
1165 A0_DEST_CHANNEL_W, /* write mask */
1166 0, /* saturate? */
1167 swizzle(depth, X, Y, Z, Z), /* src0 */
1168 0, 0 /* src1, src2 */);
1169 }
1170 }
1171
1172
1173 void
1174 i915_translate_fragment_program( struct i915_context *i915,
1175 struct i915_fragment_shader *fs)
1176 {
1177 struct i915_fp_compile *p = i915_init_compile(i915, fs);
1178 const struct tgsi_token *tokens = fs->state.tokens;
1179
1180 i915_find_wpos_space(p);
1181
1182 #if 0
1183 tgsi_dump(tokens, 0);
1184 #endif
1185
1186 i915_translate_instructions(p, tokens);
1187 i915_fixup_depth_write(p);
1188
1189 i915_fini_compile(i915, p);
1190 }