Merge branch '7.8'
[mesa.git] / src / gallium / drivers / i965 / brw_context.h
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
35
36 #include "brw_structs.h"
37 #include "brw_winsys.h"
38 #include "brw_reg.h"
39 #include "pipe/p_state.h"
40 #include "pipe/p_context.h"
41 #include "tgsi/tgsi_scan.h"
42
43
44 /* Glossary:
45 *
46 * URB - uniform resource buffer. A mid-sized buffer which is
47 * partitioned between the fixed function units and used for passing
48 * values (vertices, primitives, constants) between them.
49 *
50 * CURBE - constant URB entry. An urb region (entry) used to hold
51 * constant values which the fixed function units can be instructed to
52 * preload into the GRF when spawning a thread.
53 *
54 * VUE - vertex URB entry. An urb entry holding a vertex and usually
55 * a vertex header. The header contains control information and
56 * things like primitive type, Begin/end flags and clip codes.
57 *
58 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
59 * unit holding rasterization and interpolation parameters.
60 *
61 * GRF - general register file. One of several register files
62 * addressable by programmed threads. The inputs (r0, payload, curbe,
63 * urb) of the thread are preloaded to this area before the thread is
64 * spawned. The registers are individually 8 dwords wide and suitable
65 * for general usage. Registers holding thread input values are not
66 * special and may be overwritten.
67 *
68 * MRF - message register file. Threads communicate (and terminate)
69 * by sending messages. Message parameters are placed in contiguous
70 * MRF registers. All program output is via these messages. URB
71 * entries are populated by sending a message to the shared URB
72 * function containing the new data, together with a control word,
73 * often an unmodified copy of R0.
74 *
75 * R0 - GRF register 0. Typically holds control information used when
76 * sending messages to other threads.
77 *
78 * EU or GEN4 EU: The name of the programmable subsystem of the
79 * i965 hardware. Threads are executed by the EU, the registers
80 * described above are part of the EU architecture.
81 *
82 * Fixed function units:
83 *
84 * CS - Command streamer. Notional first unit, little software
85 * interaction. Holds the URB entries used for constant data, ie the
86 * CURBEs.
87 *
88 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
89 * this unit is responsible for pulling vertices out of vertex buffers
90 * in vram and injecting them into the processing pipe as VUEs. If
91 * enabled, it first passes them to a VS thread which is a good place
92 * for the driver to implement any active vertex shader.
93 *
94 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
95 * enabled, incoming strips etc are passed to GS threads in individual
96 * line/triangle/point units. The GS thread may perform arbitary
97 * computation and emit whatever primtives with whatever vertices it
98 * chooses. This makes GS an excellent place to implement GL's
99 * unfilled polygon modes, though of course it is capable of much
100 * more. Additionally, GS is used to translate away primitives not
101 * handled by latter units, including Quads and Lineloops.
102 *
103 * CS - Clipper. Mesa's clipping algorithms are imported to run on
104 * this unit. The fixed function part performs cliptesting against
105 * the 6 fixed clipplanes and makes decisions on whether or not the
106 * incoming primitive needs to be passed to a thread for clipping.
107 * User clip planes are handled via cooperation with the VS thread.
108 *
109 * SF - Strips Fans or Setup: Triangles are prepared for
110 * rasterization. Interpolation coefficients are calculated.
111 * Flatshading and two-side lighting usually performed here.
112 *
113 * WM - Windower. Interpolation of vertex attributes performed here.
114 * Fragment shader implemented here. SIMD aspects of EU taken full
115 * advantage of, as pixels are processed in blocks of 16.
116 *
117 * CC - Color Calculator. No EU threads associated with this unit.
118 * Handles blending and (presumably) depth and stencil testing.
119 */
120
121 #define BRW_MAX_CURBE (32*16)
122
123
124 /* Need a value to say a particular vertex shader output isn't
125 * present. Limits us to 63 outputs currently.
126 */
127 #define BRW_OUTPUT_NOT_PRESENT ((1<<6)-1)
128
129
130 struct brw_context;
131
132 struct brw_depth_stencil_state {
133 /* Precalculated hardware state:
134 */
135 struct brw_cc0 cc0;
136 struct brw_cc1 cc1;
137 struct brw_cc2 cc2;
138 struct brw_cc3 cc3;
139 struct brw_cc7 cc7;
140
141 unsigned iz_lookup;
142 };
143
144
145 struct brw_blend_state {
146 /* Precalculated hardware state:
147 */
148 struct brw_cc2 cc2;
149 struct brw_cc3 cc3;
150 struct brw_cc5 cc5;
151 struct brw_cc6 cc6;
152
153 struct brw_surf_ss0 ss0;
154 };
155
156 struct brw_rasterizer_state;
157
158 struct brw_immediate_data {
159 unsigned nr;
160 float (*data)[4];
161 };
162
163 struct brw_vertex_shader {
164 const struct tgsi_token *tokens;
165 struct brw_winsys_buffer *const_buffer; /** Program constant buffer/surface */
166
167 struct tgsi_shader_info info;
168 struct brw_immediate_data immediates;
169
170 GLuint has_flow_control:1;
171 GLuint use_const_buffer:1;
172
173 /* Offsets of special vertex shader outputs required for clipping.
174 */
175 GLuint output_hpos:6; /* not always zero? */
176 GLuint output_color0:6;
177 GLuint output_color1:6;
178 GLuint output_bfc0:6;
179 GLuint output_bfc1:6;
180 GLuint output_edgeflag:6;
181
182 unsigned id;
183 };
184
185 struct brw_fs_signature {
186 GLuint nr_inputs;
187 struct {
188 GLuint interp:3; /* TGSI_INTERPOLATE_x */
189 GLuint semantic:5; /* TGSI_SEMANTIC_x */
190 GLuint semantic_index:24;
191 } input[PIPE_MAX_SHADER_INPUTS];
192 };
193
194 #define brw_fs_signature_size(s) (offsetof(struct brw_fs_signature, input) + \
195 ((s)->nr_inputs * sizeof (s)->input[0]))
196
197
198 struct brw_fragment_shader {
199 const struct tgsi_token *tokens;
200 struct tgsi_shader_info info;
201
202 struct brw_fs_signature signature;
203 struct brw_immediate_data immediates;
204
205 unsigned iz_lookup;
206 /*unsigned wm_lookup;*/
207
208 unsigned uses_depth:1;
209 unsigned has_flow_control:1;
210
211 unsigned id;
212 struct brw_winsys_buffer *const_buffer; /** Program constant buffer/surface */
213 GLboolean use_const_buffer;
214 };
215
216
217 struct brw_sampler {
218 struct brw_ss0 ss0;
219 struct brw_ss1 ss1;
220 float border_color[4];
221 struct brw_ss3 ss3;
222 };
223
224
225
226 #define PIPE_NEW_DEPTH_STENCIL_ALPHA 0x1
227 #define PIPE_NEW_RAST 0x2
228 #define PIPE_NEW_BLEND 0x4
229 #define PIPE_NEW_VIEWPORT 0x8
230 #define PIPE_NEW_SAMPLERS 0x10
231 #define PIPE_NEW_VERTEX_BUFFER 0x20
232 #define PIPE_NEW_VERTEX_ELEMENT 0x40
233 #define PIPE_NEW_FRAGMENT_SHADER 0x80
234 #define PIPE_NEW_VERTEX_SHADER 0x100
235 #define PIPE_NEW_FRAGMENT_CONSTANTS 0x200
236 #define PIPE_NEW_VERTEX_CONSTANTS 0x400
237 #define PIPE_NEW_CLIP 0x800
238 #define PIPE_NEW_INDEX_BUFFER 0x1000
239 #define PIPE_NEW_INDEX_RANGE 0x2000
240 #define PIPE_NEW_BLEND_COLOR 0x4000
241 #define PIPE_NEW_POLYGON_STIPPLE 0x8000
242 #define PIPE_NEW_FRAMEBUFFER_DIMENSIONS 0x10000
243 #define PIPE_NEW_DEPTH_BUFFER 0x20000
244 #define PIPE_NEW_COLOR_BUFFERS 0x40000
245 #define PIPE_NEW_QUERY 0x80000
246 #define PIPE_NEW_SCISSOR 0x100000
247 #define PIPE_NEW_BOUND_TEXTURES 0x200000
248 #define PIPE_NEW_NR_CBUFS 0x400000
249 #define PIPE_NEW_FRAGMENT_SIGNATURE 0x800000
250
251
252
253 #define BRW_NEW_URB_FENCE 0x1
254 #define BRW_NEW_FRAGMENT_PROGRAM 0x2
255 #define BRW_NEW_VERTEX_PROGRAM 0x4
256 #define BRW_NEW_INPUT_DIMENSIONS 0x8
257 #define BRW_NEW_CURBE_OFFSETS 0x10
258 #define BRW_NEW_REDUCED_PRIMITIVE 0x20
259 #define BRW_NEW_PRIMITIVE 0x40
260 #define BRW_NEW_CONTEXT 0x80
261 #define BRW_NEW_WM_INPUT_DIMENSIONS 0x100
262 #define BRW_NEW_PSP 0x800
263 #define BRW_NEW_WM_SURFACES 0x1000
264 #define BRW_NEW_xxx 0x2000 /* was FENCE */
265 #define BRW_NEW_INDICES 0x4000
266
267 /**
268 * Used for any batch entry with a relocated pointer that will be used
269 * by any 3D rendering. Need to re-emit these fresh in each
270 * batchbuffer as the referenced buffers may be relocated in the
271 * meantime.
272 */
273 #define BRW_NEW_BATCH 0x10000
274 #define BRW_NEW_NR_WM_SURFACES 0x40000
275 #define BRW_NEW_NR_VS_SURFACES 0x80000
276 #define BRW_NEW_INDEX_BUFFER 0x100000
277
278 struct brw_state_flags {
279 /** State update flags signalled by mesa internals */
280 GLuint mesa;
281 /**
282 * State update flags signalled as the result of brw_tracked_state updates
283 */
284 GLuint brw;
285 /** State update flags signalled by brw_state_cache.c searches */
286 GLuint cache;
287 };
288
289
290
291 /* Data about a particular attempt to compile a program. Note that
292 * there can be many of these, each in a different GL state
293 * corresponding to a different brw_wm_prog_key struct, with different
294 * compiled programs:
295 */
296 struct brw_wm_prog_data {
297 GLuint curb_read_length;
298 GLuint urb_read_length;
299
300 GLuint first_curbe_grf;
301 GLuint total_grf;
302 GLuint total_scratch;
303
304 GLuint nr_params; /**< number of float params/constants */
305 GLboolean error;
306
307 /* Pointer to tracked values (only valid once
308 * _mesa_load_state_parameters has been called at runtime).
309 */
310 const GLfloat *param[BRW_MAX_CURBE];
311 };
312
313 struct brw_sf_prog_data {
314 GLuint urb_read_length;
315 GLuint total_grf;
316
317 /* Each vertex may have upto 12 attributes, 4 components each,
318 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
319 * rows.
320 *
321 * Actually we use 4 for each, so call it 12 rows.
322 */
323 GLuint urb_entry_size;
324 };
325
326
327 struct brw_clip_prog_data;
328
329 struct brw_gs_prog_data {
330 GLuint urb_read_length;
331 GLuint total_grf;
332 };
333
334 struct brw_vs_prog_data {
335 GLuint curb_read_length;
336 GLuint urb_read_length;
337 GLuint total_grf;
338
339 GLuint nr_outputs;
340 GLuint nr_inputs;
341
342 GLuint nr_params; /**< number of TGSI_FILE_CONSTANT's */
343
344 GLboolean writes_psiz;
345
346 /* Used for calculating urb partitions:
347 */
348 GLuint urb_entry_size;
349 };
350
351
352 /* Size == 0 if output either not written, or always [0,0,0,1]
353 */
354 struct brw_vs_output_sizes {
355 GLubyte output_size[PIPE_MAX_SHADER_OUTPUTS];
356 };
357
358
359 /** Number of texture sampler units */
360 #define BRW_MAX_TEX_UNIT 16
361
362 /** Max number of render targets in a shader */
363 #define BRW_MAX_DRAW_BUFFERS 4
364
365 /**
366 * Size of our surface binding table for the WM.
367 * This contains pointers to the drawing surfaces and current texture
368 * objects and shader constant buffers (+2).
369 */
370 #define BRW_WM_MAX_SURF (BRW_MAX_DRAW_BUFFERS + BRW_MAX_TEX_UNIT + 1)
371
372 /**
373 * Helpers to convert drawing buffers, textures and constant buffers
374 * to surface binding table indexes, for WM.
375 */
376 #define BTI_COLOR_BUF(d) (d)
377 #define BTI_FRAGMENT_CONSTANTS (BRW_MAX_DRAW_BUFFERS)
378 #define BTI_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 1 + (t))
379
380 /**
381 * Size of surface binding table for the VS.
382 * Only one constant buffer for now.
383 */
384 #define BRW_VS_MAX_SURF 1
385
386 /**
387 * Only a VS constant buffer
388 */
389 #define SURF_INDEX_VERT_CONST_BUFFER 0
390
391
392 /* Bit of a hack to align these with the winsys buffer_data_type enum.
393 */
394 enum brw_cache_id {
395 BRW_CC_VP = BRW_DATA_GS_CC_VP,
396 BRW_CC_UNIT = BRW_DATA_GS_CC_UNIT,
397 BRW_WM_PROG = BRW_DATA_GS_WM_PROG,
398 BRW_SAMPLER_DEFAULT_COLOR = BRW_DATA_GS_SAMPLER_DEFAULT_COLOR,
399 BRW_SAMPLER = BRW_DATA_GS_SAMPLER,
400 BRW_WM_UNIT = BRW_DATA_GS_WM_UNIT,
401 BRW_SF_PROG = BRW_DATA_GS_SF_PROG,
402 BRW_SF_VP = BRW_DATA_GS_SF_VP,
403 BRW_SF_UNIT = BRW_DATA_GS_SF_UNIT,
404 BRW_VS_UNIT = BRW_DATA_GS_VS_UNIT,
405 BRW_VS_PROG = BRW_DATA_GS_VS_PROG,
406 BRW_GS_UNIT = BRW_DATA_GS_GS_UNIT,
407 BRW_GS_PROG = BRW_DATA_GS_GS_PROG,
408 BRW_CLIP_VP = BRW_DATA_GS_CLIP_VP,
409 BRW_CLIP_UNIT = BRW_DATA_GS_CLIP_UNIT,
410 BRW_CLIP_PROG = BRW_DATA_GS_CLIP_PROG,
411 BRW_SS_SURFACE = BRW_DATA_SS_SURFACE,
412 BRW_SS_SURF_BIND = BRW_DATA_SS_SURF_BIND,
413
414 BRW_MAX_CACHE
415 };
416
417 struct brw_cache_item {
418 /**
419 * Effectively part of the key, cache_id identifies what kind of state
420 * buffer is involved, and also which brw->state.dirty.cache flag should
421 * be set when this cache item is chosen.
422 */
423 enum brw_cache_id cache_id;
424 /** 32-bit hash of the key data */
425 GLuint hash;
426 GLuint key_size; /* for variable-sized keys */
427 const void *key;
428 struct brw_winsys_reloc *relocs;
429 GLuint nr_relocs;
430
431 struct brw_winsys_buffer *bo;
432 GLuint data_size;
433
434 struct brw_cache_item *next;
435 };
436
437
438
439 struct brw_cache {
440 struct brw_context *brw;
441 struct brw_winsys_screen *sws;
442
443 struct brw_cache_item **items;
444 GLuint size, n_items;
445
446 enum brw_buffer_type buffer_type;
447
448 GLuint key_size[BRW_MAX_CACHE]; /* for fixed-size keys */
449 GLuint aux_size[BRW_MAX_CACHE];
450 char *name[BRW_MAX_CACHE];
451
452
453 /* Record of the last BOs chosen for each cache_id. Used to set
454 * brw->state.dirty.cache when a new cache item is chosen.
455 */
456 struct brw_winsys_buffer *last_bo[BRW_MAX_CACHE];
457 };
458
459
460 struct brw_tracked_state {
461 struct brw_state_flags dirty;
462 int (*prepare)( struct brw_context *brw );
463 int (*emit)( struct brw_context *brw );
464 };
465
466 /* Flags for brw->state.cache.
467 */
468 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
469 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
470 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
471 #define CACHE_NEW_SAMPLER_DEFAULT_COLOR (1<<BRW_SAMPLER_DEFAULT_COLOR)
472 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
473 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
474 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
475 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
476 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
477 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
478 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
479 #define CACHE_NEW_GS_UNIT (1<<BRW_GS_UNIT)
480 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
481 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
482 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
483 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
484 #define CACHE_NEW_SURFACE (1<<BRW_SS_SURFACE)
485 #define CACHE_NEW_SURF_BIND (1<<BRW_SS_SURF_BIND)
486
487 struct brw_cached_batch_item {
488 struct header *header;
489 GLuint sz;
490 struct brw_cached_batch_item *next;
491 };
492
493
494
495 /* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life
496 * be easier if C allowed arrays of packed elements?
497 */
498 #define VS_INPUT_BITMASK_DWORDS ((PIPE_MAX_SHADER_INPUTS+31)/32)
499
500
501
502
503 struct brw_vertex_info {
504 GLuint sizes[VS_INPUT_BITMASK_DWORDS * 2]; /* sizes:2[VERT_ATTRIB_MAX] */
505 };
506
507
508 struct brw_query_object {
509 /** Doubly linked list of active query objects in the context. */
510 struct brw_query_object *prev, *next;
511
512 /** Last query BO associated with this query. */
513 struct brw_winsys_buffer *bo;
514 /** First index in bo with query data for this object. */
515 int first_index;
516 /** Last index in bo with query data for this object. */
517 int last_index;
518
519 /* Total count of pixels from previous BOs */
520 uint64_t result;
521 };
522
523 #define CC_RELOC_VP 0
524
525
526 /**
527 * brw_context is derived from pipe_context
528 */
529 struct brw_context
530 {
531 struct pipe_context base;
532 struct brw_chipset chipset;
533
534 struct brw_winsys_screen *sws;
535
536 struct brw_batchbuffer *batch;
537
538 GLuint primitive;
539 GLuint reduced_primitive;
540
541 /* Active state from the state tracker:
542 */
543 struct {
544 struct brw_vertex_shader *vertex_shader;
545 struct brw_fragment_shader *fragment_shader;
546 const struct brw_blend_state *blend;
547 const struct brw_rasterizer_state *rast;
548 const struct brw_depth_stencil_state *zstencil;
549 const struct brw_vertex_element_packet *velems;
550
551 const struct brw_sampler *sampler[PIPE_MAX_SAMPLERS];
552 unsigned num_samplers;
553
554 struct pipe_sampler_view *fragment_sampler_views[PIPE_MAX_SAMPLERS];
555 struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
556 unsigned num_fragment_sampler_views;
557 unsigned num_vertex_buffers;
558
559 struct pipe_scissor_state scissor;
560 struct pipe_viewport_state viewport;
561 struct pipe_stencil_ref stencil_ref;
562 struct pipe_framebuffer_state fb;
563 struct pipe_clip_state ucp;
564 struct pipe_buffer *vertex_constants;
565 struct pipe_buffer *fragment_constants;
566
567 struct brw_blend_constant_color bcc;
568 struct brw_cc1 cc1_stencil_ref;
569 struct brw_polygon_stipple bps;
570 struct brw_cc_viewport ccv;
571
572 /**
573 * Index buffer for this draw_prims call.
574 *
575 * Updates are signaled by PIPE_NEW_INDEX_BUFFER.
576 */
577 struct pipe_buffer *index_buffer;
578 unsigned index_size;
579
580 /* Updates are signalled by PIPE_NEW_INDEX_RANGE:
581 */
582 unsigned min_index;
583 unsigned max_index;
584
585 } curr;
586
587 struct {
588 struct brw_state_flags dirty;
589
590 /**
591 * List of buffers accumulated in brw_validate_state to receive
592 * dri_bo_check_aperture treatment before exec, so we can know if we
593 * should flush the batch and try again before emitting primitives.
594 *
595 * This can be a fixed number as we only have a limited number of
596 * objects referenced from the batchbuffer in a primitive emit,
597 * consisting of the vertex buffers, pipelined state pointers,
598 * the CURBE, the depth buffer, and a query BO.
599 */
600 struct brw_winsys_buffer *validated_bos[PIPE_MAX_SHADER_INPUTS + 16];
601 int validated_bo_count;
602 } state;
603
604 struct brw_cache cache; /** non-surface items */
605 struct brw_cache surface_cache; /* surface items */
606 struct brw_cached_batch_item *cached_batch_items;
607
608 struct {
609 struct u_upload_mgr *upload_vertex;
610 struct u_upload_mgr *upload_index;
611
612 /* Information on uploaded vertex buffers:
613 */
614 struct {
615 unsigned stride; /* in bytes between successive vertices */
616 unsigned offset; /* in bytes, of first vertex in bo */
617 unsigned vertex_count; /* count of valid vertices which may be accessed */
618 struct brw_winsys_buffer *bo;
619 } vb[PIPE_MAX_ATTRIBS];
620
621 unsigned nr_vb; /* currently the same as curr.num_vertex_buffers */
622 } vb;
623
624 struct {
625 /* Updates to these fields are signaled by BRW_NEW_INDEX_BUFFER. */
626 struct brw_winsys_buffer *bo;
627 unsigned int offset;
628 unsigned int size;
629 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
630 * avoid re-uploading the IB packet over and over if we're actually
631 * referencing the same index buffer.
632 */
633 unsigned int start_vertex_offset;
634 } ib;
635
636
637 /* BRW_NEW_URB_ALLOCATIONS:
638 */
639 struct {
640 GLuint vsize; /* vertex size plus header in urb registers */
641 GLuint csize; /* constant buffer size in urb registers */
642 GLuint sfsize; /* setup data size in urb registers */
643
644 GLboolean constrained;
645
646 GLuint nr_vs_entries;
647 GLuint nr_gs_entries;
648 GLuint nr_clip_entries;
649 GLuint nr_sf_entries;
650 GLuint nr_cs_entries;
651
652 GLuint vs_start;
653 GLuint gs_start;
654 GLuint clip_start;
655 GLuint sf_start;
656 GLuint cs_start;
657 } urb;
658
659
660 /* BRW_NEW_CURBE_OFFSETS:
661 */
662 struct {
663 GLuint wm_start; /**< pos of first wm const in CURBE buffer */
664 GLuint wm_size; /**< number of float[4] consts, multiple of 16 */
665 GLuint clip_start;
666 GLuint clip_size;
667 GLuint vs_start;
668 GLuint vs_size;
669 GLuint total_size;
670
671 struct brw_winsys_buffer *curbe_bo;
672 /** Offset within curbe_bo of space for current curbe entry */
673 GLuint curbe_offset;
674 /** Offset within curbe_bo of space for next curbe entry */
675 GLuint curbe_next_offset;
676
677 GLfloat *last_buf;
678 GLuint last_bufsz;
679 /**
680 * Whether we should create a new bo instead of reusing the old one
681 * (if we just dispatch the batch pointing at the old one.
682 */
683 GLboolean need_new_bo;
684 } curbe;
685
686 struct {
687 struct brw_vs_prog_data *prog_data;
688
689 struct brw_winsys_buffer *prog_bo;
690 struct brw_winsys_buffer *state_bo;
691
692 /** Binding table of pointers to surf_bo entries */
693 struct brw_winsys_buffer *bind_bo;
694 struct brw_winsys_buffer *surf_bo[BRW_VS_MAX_SURF];
695 GLuint nr_surfaces;
696 } vs;
697
698 struct {
699 struct brw_gs_prog_data *prog_data;
700
701 GLboolean prog_active;
702 struct brw_winsys_buffer *prog_bo;
703 struct brw_winsys_buffer *state_bo;
704 } gs;
705
706 struct {
707 struct brw_clip_prog_data *prog_data;
708
709 struct brw_winsys_buffer *prog_bo;
710 struct brw_winsys_buffer *state_bo;
711 struct brw_winsys_buffer *vp_bo;
712 } clip;
713
714
715 struct {
716 struct brw_sf_prog_data *prog_data;
717
718 struct brw_winsys_buffer *prog_bo;
719 struct brw_winsys_buffer *state_bo;
720 struct brw_winsys_buffer *vp_bo;
721 } sf;
722
723 struct {
724 struct brw_wm_prog_data *prog_data;
725 struct brw_wm_compile *compile_data;
726
727 /** Input sizes, calculated from active vertex program.
728 * One bit per fragment program input attribute.
729 */
730 /*GLbitfield input_size_masks[4];*/
731
732 /** Array of surface default colors (texture border color) */
733 struct brw_winsys_buffer *sdc_bo[BRW_MAX_TEX_UNIT];
734
735 GLuint render_surf;
736 GLuint nr_surfaces;
737
738 GLuint max_threads;
739 struct brw_winsys_buffer *scratch_bo;
740
741 GLuint sampler_count;
742 struct brw_winsys_buffer *sampler_bo;
743
744 /** Binding table of pointers to surf_bo entries */
745 struct brw_winsys_buffer *bind_bo;
746 struct brw_winsys_buffer *surf_bo[BRW_WM_MAX_SURF];
747
748 struct brw_winsys_buffer *prog_bo;
749 struct brw_winsys_buffer *state_bo;
750 } wm;
751
752
753 struct {
754 struct brw_winsys_buffer *state_bo;
755
756 struct brw_cc_unit_state cc;
757 struct brw_winsys_reloc reloc[1];
758 } cc;
759
760 struct {
761 struct brw_query_object active_head;
762 struct brw_winsys_buffer *bo;
763 int index;
764 GLboolean active;
765 int stats_wm;
766 } query;
767
768 struct {
769 unsigned always_emit_state:1;
770 unsigned always_flush_batch:1;
771 unsigned force_swtnl:1;
772 unsigned no_swtnl:1;
773 } flags;
774
775 /* Used to give every program string a unique id
776 */
777 GLuint program_id;
778 };
779
780
781
782 /*======================================================================
783 * brw_queryobj.c
784 */
785 void brw_init_query(struct brw_context *brw);
786 enum pipe_error brw_prepare_query_begin(struct brw_context *brw);
787 void brw_emit_query_begin(struct brw_context *brw);
788 void brw_emit_query_end(struct brw_context *brw);
789
790 /*======================================================================
791 * brw_state_dump.c
792 */
793 void brw_debug_batch(struct brw_context *intel);
794
795
796 /*======================================================================
797 * brw_pipe_*.c
798 */
799 void brw_pipe_blend_init( struct brw_context *brw );
800 void brw_pipe_depth_stencil_init( struct brw_context *brw );
801 void brw_pipe_framebuffer_init( struct brw_context *brw );
802 void brw_pipe_flush_init( struct brw_context *brw );
803 void brw_pipe_misc_init( struct brw_context *brw );
804 void brw_pipe_query_init( struct brw_context *brw );
805 void brw_pipe_rast_init( struct brw_context *brw );
806 void brw_pipe_sampler_init( struct brw_context *brw );
807 void brw_pipe_shader_init( struct brw_context *brw );
808 void brw_pipe_vertex_init( struct brw_context *brw );
809 void brw_pipe_clear_init( struct brw_context *brw );
810
811
812 void brw_pipe_blend_cleanup( struct brw_context *brw );
813 void brw_pipe_depth_stencil_cleanup( struct brw_context *brw );
814 void brw_pipe_framebuffer_cleanup( struct brw_context *brw );
815 void brw_pipe_flush_cleanup( struct brw_context *brw );
816 void brw_pipe_misc_cleanup( struct brw_context *brw );
817 void brw_pipe_query_cleanup( struct brw_context *brw );
818 void brw_pipe_rast_cleanup( struct brw_context *brw );
819 void brw_pipe_sampler_cleanup( struct brw_context *brw );
820 void brw_pipe_shader_cleanup( struct brw_context *brw );
821 void brw_pipe_vertex_cleanup( struct brw_context *brw );
822 void brw_pipe_clear_cleanup( struct brw_context *brw );
823
824 void brw_hw_cc_init( struct brw_context *brw );
825 void brw_hw_cc_cleanup( struct brw_context *brw );
826
827
828
829 void brw_context_flush( struct brw_context *brw );
830
831
832 /* brw_urb.c
833 */
834 int brw_upload_urb_fence(struct brw_context *brw);
835
836 /* brw_curbe.c
837 */
838 int brw_upload_cs_urb_state(struct brw_context *brw);
839
840 /* brw_context.c
841 */
842 struct pipe_context *brw_create_context(struct pipe_screen *screen,
843 void *priv);
844
845 /*======================================================================
846 * Inline conversion functions. These are better-typed than the
847 * macros used previously:
848 */
849 static INLINE struct brw_context *
850 brw_context( struct pipe_context *ctx )
851 {
852 return (struct brw_context *)ctx;
853 }
854
855
856 #define BRW_IS_965(brw) ((brw)->chipset.is_965)
857 #define BRW_IS_IGDNG(brw) ((brw)->chipset.is_igdng)
858 #define BRW_IS_G4X(brw) ((brw)->chipset.is_g4x)
859
860
861 #endif
862