src/gallium/drivers/i965/brw_screen.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2008 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 #include "pipe/p_inlines.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_string.h"
  32
  33 #include "brw_reg.h"
  34 #include "brw_context.h"
  35 #include "brw_screen.h"
  36 #include "brw_winsys.h"
  37 #include "brw_debug.h"
  38
  39 #ifdef DEBUG
  40 static const struct debug_named_value debug_names[] = {
  41    { "tex",   DEBUG_TEXTURE},
  42    { "state", DEBUG_STATE},
  43    { "ioctl", DEBUG_IOCTL},
  44    { "blit",  DEBUG_BLIT},
  45    { "curbe", DEBUG_CURBE},
  46    { "fall",  DEBUG_FALLBACKS},
  47    { "verb",  DEBUG_VERBOSE},
  48    { "bat",   DEBUG_BATCH},
  49    { "pix",   DEBUG_PIXEL},
  50    { "wins",  DEBUG_WINSYS},
  51    { "min",   DEBUG_MIN_URB},
  52    { "dis",   DEBUG_DISASSEM},
  53    { "sync",  DEBUG_SYNC},
  54    { "prim",  DEBUG_PRIMS },
  55    { "vert",  DEBUG_VERTS },
  56    { "dma",   DEBUG_DMA },
  57    { "san",   DEBUG_SANITY },
  58    { "sleep", DEBUG_SLEEP },
  59    { "stats", DEBUG_STATS },
  60    { "sing",  DEBUG_SINGLE_THREAD },
  61    { "thre",  DEBUG_SINGLE_THREAD },
  62    { "wm",    DEBUG_WM },
  63    { "urb",   DEBUG_URB },
  64    { "vs",    DEBUG_VS },
  65    { NULL,    0 }
  66 };
  67
  68 static const struct debug_named_value dump_names[] = {
  69    { "asm",   DUMP_ASM},
  70    { "state", DUMP_STATE},
  71    { "batch", DUMP_BATCH},
  72    { NULL, 0 }
  73 };
  74
  75 int BRW_DEBUG = 0;
  76 int BRW_DUMP = 0;
  77
  78 #endif
  79
  80
  81 /*
  82  * Probe functions
  83  */
  84
  85
  86 static const char *
  87 brw_get_vendor(struct pipe_screen *screen)
  88 {
  89    return "VMware, Inc.";
  90 }
  91
  92 static const char *
  93 brw_get_name(struct pipe_screen *screen)
  94 {
  95    static char buffer[128];
  96    const char *chipset;
  97
  98    switch (brw_screen(screen)->chipset.pci_id) {
  99    case PCI_CHIP_I965_G:
 100       chipset = "I965_G";
 101       break;
 102    case PCI_CHIP_I965_Q:
 103       chipset = "I965_Q";
 104       break;
 105    case PCI_CHIP_I965_G_1:
 106       chipset = "I965_G_1";
 107       break;
 108    case PCI_CHIP_I946_GZ:
 109       chipset = "I946_GZ";
 110       break;
 111    case PCI_CHIP_I965_GM:
 112       chipset = "I965_GM";
 113       break;
 114    case PCI_CHIP_I965_GME:
 115       chipset = "I965_GME";
 116       break;
 117    case PCI_CHIP_GM45_GM:
 118       chipset = "GM45_GM";
 119       break;
 120    case PCI_CHIP_IGD_E_G:
 121       chipset = "IGD_E_G";
 122       break;
 123    case PCI_CHIP_Q45_G:
 124       chipset = "Q45_G";
 125       break;
 126    case PCI_CHIP_G45_G:
 127       chipset = "G45_G";
 128       break;
 129    case PCI_CHIP_G41_G:
 130       chipset = "G41_G";
 131       break;
 132    case PCI_CHIP_B43_G:
 133       chipset = "B43_G";
 134       break;
 135    case PCI_CHIP_ILD_G:
 136       chipset = "ILD_G";
 137       break;
 138    case PCI_CHIP_ILM_G:
 139       chipset = "ILM_G";
 140       break;
 141    default:
 142       chipset = "unknown";
 143       break;
 144    }
 145
 146    util_snprintf(buffer, sizeof(buffer), "i965 (chipset: %s)", chipset);
 147    return buffer;
 148 }
 149
 150 static int
 151 brw_get_param(struct pipe_screen *screen, int param)
 152 {
 153    switch (param) {
 154    case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
 155       return 8;
 156    case PIPE_CAP_NPOT_TEXTURES:
 157       return 1;
 158    case PIPE_CAP_TWO_SIDED_STENCIL:
 159       return 1;
 160    case PIPE_CAP_GLSL:
 161       return 0;
 162    case PIPE_CAP_ANISOTROPIC_FILTER:
 163       return 0;
 164    case PIPE_CAP_POINT_SPRITE:
 165       return 0;
 166    case PIPE_CAP_MAX_RENDER_TARGETS:
 167       return 1;
 168    case PIPE_CAP_OCCLUSION_QUERY:
 169       return 0;
 170    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 171       return 1;
 172    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 173       return 11; /* max 1024x1024 */
 174    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 175       return 8;  /* max 128x128x128 */
 176    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 177       return 11; /* max 1024x1024 */
 178    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 179    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 180       return 1;
 181    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 182    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 183       return 0;
 184    default:
 185       return 0;
 186    }
 187 }
 188
 189 static float
 190 brw_get_paramf(struct pipe_screen *screen, int param)
 191 {
 192    switch (param) {
 193    case PIPE_CAP_MAX_LINE_WIDTH:
 194       /* fall-through */
 195    case PIPE_CAP_MAX_LINE_WIDTH_AA:
 196       return 7.5;
 197
 198    case PIPE_CAP_MAX_POINT_WIDTH:
 199       /* fall-through */
 200    case PIPE_CAP_MAX_POINT_WIDTH_AA:
 201       return 255.0;
 202
 203    case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 204       return 4.0;
 205
 206    case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 207       return 16.0;
 208
 209    default:
 210       return 0;
 211    }
 212 }
 213
 214 static boolean
 215 brw_is_format_supported(struct pipe_screen *screen,
 216                          enum pipe_format format,
 217                          enum pipe_texture_target target,
 218                          unsigned tex_usage,
 219                          unsigned geom_flags)
 220 {
 221    static const enum pipe_format tex_supported[] = {
 222       PIPE_FORMAT_L8_UNORM,
 223       PIPE_FORMAT_I8_UNORM,
 224       PIPE_FORMAT_A8_UNORM,
 225       PIPE_FORMAT_L16_UNORM,
 226       /*PIPE_FORMAT_I16_UNORM,*/
 227       /*PIPE_FORMAT_A16_UNORM,*/
 228       PIPE_FORMAT_A8L8_UNORM,
 229       PIPE_FORMAT_R5G6B5_UNORM,
 230       PIPE_FORMAT_A1R5G5B5_UNORM,
 231       PIPE_FORMAT_A4R4G4B4_UNORM,
 232       PIPE_FORMAT_X8R8G8B8_UNORM,
 233       PIPE_FORMAT_A8R8G8B8_UNORM,
 234       /* video */
 235       PIPE_FORMAT_YCBCR,
 236       PIPE_FORMAT_YCBCR_REV,
 237       /* compressed */
 238       /*PIPE_FORMAT_FXT1_RGBA,*/
 239       PIPE_FORMAT_DXT1_RGB,
 240       PIPE_FORMAT_DXT1_RGBA,
 241       PIPE_FORMAT_DXT3_RGBA,
 242       PIPE_FORMAT_DXT5_RGBA,
 243       /* sRGB */
 244       PIPE_FORMAT_R8G8B8A8_SRGB,
 245       PIPE_FORMAT_A8L8_SRGB,
 246       PIPE_FORMAT_L8_SRGB,
 247       PIPE_FORMAT_DXT1_SRGB,
 248       /* depth */
 249       PIPE_FORMAT_Z32_FLOAT,
 250       PIPE_FORMAT_X8Z24_UNORM,
 251       PIPE_FORMAT_S8Z24_UNORM,
 252       PIPE_FORMAT_Z16_UNORM,
 253       /* signed */
 254       PIPE_FORMAT_R8G8_SNORM,
 255       PIPE_FORMAT_R8G8B8A8_SNORM,
 256       PIPE_FORMAT_NONE  /* list terminator */
 257    };
 258    static const enum pipe_format render_supported[] = {
 259       PIPE_FORMAT_X8R8G8B8_UNORM,
 260       PIPE_FORMAT_A8R8G8B8_UNORM,
 261       PIPE_FORMAT_R5G6B5_UNORM,
 262       PIPE_FORMAT_NONE  /* list terminator */
 263    };
 264    static const enum pipe_format depth_supported[] = {
 265       PIPE_FORMAT_Z32_FLOAT,
 266       PIPE_FORMAT_X8Z24_UNORM,
 267       PIPE_FORMAT_S8Z24_UNORM,
 268       PIPE_FORMAT_Z16_UNORM,
 269       PIPE_FORMAT_NONE  /* list terminator */
 270    };
 271    const enum pipe_format *list;
 272    uint i;
 273
 274    if (tex_usage & PIPE_TEXTURE_USAGE_DEPTH_STENCIL)
 275       list = depth_supported;
 276    else if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET)
 277       list = render_supported;
 278    else
 279       list = tex_supported;
 280
 281    for (i = 0; list[i] != PIPE_FORMAT_NONE; i++) {
 282       if (list[i] == format)
 283          return TRUE;
 284    }
 285
 286    return FALSE;
 287 }
 288
 289
 290 /*
 291  * Fence functions
 292  */
 293
 294
 295 static void
 296 brw_fence_reference(struct pipe_screen *screen,
 297                      struct pipe_fence_handle **ptr,
 298                      struct pipe_fence_handle *fence)
 299 {
 300 }
 301
 302 static int
 303 brw_fence_signalled(struct pipe_screen *screen,
 304                      struct pipe_fence_handle *fence,
 305                      unsigned flags)
 306 {
 307    return 0;                    /* XXX shouldn't this be a boolean? */
 308 }
 309
 310 static int
 311 brw_fence_finish(struct pipe_screen *screen,
 312                  struct pipe_fence_handle *fence,
 313                  unsigned flags)
 314 {
 315    return 0;
 316 }
 317
 318
 319 /*
 320  * Generic functions
 321  */
 322
 323
 324 static void
 325 brw_destroy_screen(struct pipe_screen *screen)
 326 {
 327    struct brw_screen *bscreen = brw_screen(screen);
 328
 329    if (bscreen->sws)
 330       bscreen->sws->destroy(bscreen->sws);
 331
 332    FREE(bscreen);
 333 }
 334
 335 /**
 336  * Create a new brw_screen object
 337  */
 338 struct pipe_screen *
 339 brw_create_screen(struct brw_winsys_screen *sws, uint pci_id)
 340 {
 341    struct brw_screen *bscreen;
 342    struct brw_chipset chipset;
 343
 344 #ifdef DEBUG
 345    BRW_DEBUG = debug_get_flags_option("BRW_DEBUG", debug_names, 0);
 346    BRW_DEBUG |= debug_get_flags_option("INTEL_DEBUG", debug_names, 0);
 347    BRW_DEBUG |= DEBUG_STATS | DEBUG_MIN_URB | DEBUG_WM;
 348
 349    BRW_DUMP = debug_get_flags_option("BRW_DUMP", dump_names, 0);
 350 #endif
 351
 352    memset(&chipset, 0, sizeof chipset);
 353
 354    chipset.pci_id = pci_id;
 355
 356    switch (pci_id) {
 357    case PCI_CHIP_I965_G:
 358    case PCI_CHIP_I965_Q:
 359    case PCI_CHIP_I965_G_1:
 360    case PCI_CHIP_I946_GZ:
 361    case PCI_CHIP_I965_GM:
 362    case PCI_CHIP_I965_GME:
 363       chipset.is_965 = TRUE;
 364       break;
 365
 366    case PCI_CHIP_GM45_GM:
 367    case PCI_CHIP_IGD_E_G:
 368    case PCI_CHIP_Q45_G:
 369    case PCI_CHIP_G45_G:
 370    case PCI_CHIP_G41_G:
 371    case PCI_CHIP_B43_G:
 372       chipset.is_g4x = TRUE;
 373       break;
 374
 375    case PCI_CHIP_ILD_G:
 376    case PCI_CHIP_ILM_G:
 377       chipset.is_igdng = TRUE;
 378       break;
 379
 380    default:
 381       debug_printf("%s: unknown pci id 0x%x, cannot create screen\n",
 382                    __FUNCTION__, pci_id);
 383       return NULL;
 384    }
 385
 386
 387    bscreen = CALLOC_STRUCT(brw_screen);
 388    if (!bscreen)
 389       return NULL;
 390
 391    bscreen->chipset = chipset;
 392    bscreen->sws = sws;
 393    bscreen->base.winsys = NULL;
 394    bscreen->base.destroy = brw_destroy_screen;
 395    bscreen->base.get_name = brw_get_name;
 396    bscreen->base.get_vendor = brw_get_vendor;
 397    bscreen->base.get_param = brw_get_param;
 398    bscreen->base.get_paramf = brw_get_paramf;
 399    bscreen->base.is_format_supported = brw_is_format_supported;
 400    bscreen->base.fence_reference = brw_fence_reference;
 401    bscreen->base.fence_signalled = brw_fence_signalled;
 402    bscreen->base.fence_finish = brw_fence_finish;
 403
 404    brw_screen_tex_init(bscreen);
 405    brw_screen_tex_surface_init(bscreen);
 406    brw_screen_buffer_init(bscreen);
 407
 408    bscreen->no_tiling = debug_get_option("BRW_NO_TILING", FALSE) != NULL;
 409
 410
 411    return &bscreen->base;
 412 }