src/gallium/drivers/i965/brw_screen.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2008 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 #include "pipe/p_inlines.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_string.h"
  32
  33 #include "brw_reg.h"
  34 #include "brw_context.h"
  35 #include "brw_screen.h"
  36 #include "brw_winsys.h"
  37 #include "brw_debug.h"
  38
  39 #ifdef DEBUG
  40 static const struct debug_named_value debug_names[] = {
  41    { "tex",   DEBUG_TEXTURE},
  42    { "state", DEBUG_STATE},
  43    { "ioctl", DEBUG_IOCTL},
  44    { "blit",  DEBUG_BLIT},
  45    { "curbe", DEBUG_CURBE},
  46    { "fall",  DEBUG_FALLBACKS},
  47    { "verb",  DEBUG_VERBOSE},
  48    { "bat",   DEBUG_BATCH},
  49    { "pix",   DEBUG_PIXEL},
  50    { "wins",  DEBUG_WINSYS},
  51    { "min",   DEBUG_MIN_URB},
  52    { "dis",   DEBUG_DISASSEM},
  53    { "sync",  DEBUG_SYNC},
  54    { "prim",  DEBUG_PRIMS },
  55    { "vert",  DEBUG_VERTS },
  56    { "dma",   DEBUG_DMA },
  57    { "san",   DEBUG_SANITY },
  58    { "sleep", DEBUG_SLEEP },
  59    { "stats", DEBUG_STATS },
  60    { "sing",  DEBUG_SINGLE_THREAD },
  61    { "thre",  DEBUG_SINGLE_THREAD },
  62    { "wm",    DEBUG_WM },
  63    { "urb",   DEBUG_URB },
  64    { "vs",    DEBUG_VS },
  65    { NULL,    0 }
  66 };
  67
  68 static const struct debug_named_value dump_names[] = {
  69    { "asm",   DUMP_ASM},
  70    { "state", DUMP_STATE},
  71    { "batch", DUMP_BATCH},
  72    { NULL, 0 }
  73 };
  74
  75 int BRW_DEBUG = 0;
  76 int BRW_DUMP = 0;
  77
  78 #endif
  79
  80
  81 /*
  82  * Probe functions
  83  */
  84
  85
  86 static const char *
  87 brw_get_vendor(struct pipe_screen *screen)
  88 {
  89    return "VMware, Inc.";
  90 }
  91
  92 static const char *
  93 brw_get_name(struct pipe_screen *screen)
  94 {
  95    static char buffer[128];
  96    const char *chipset;
  97
  98    switch (brw_screen(screen)->chipset.pci_id) {
  99    case PCI_CHIP_I965_G:
 100       chipset = "I965_G";
 101       break;
 102    case PCI_CHIP_I965_Q:
 103       chipset = "I965_Q";
 104       break;
 105    case PCI_CHIP_I965_G_1:
 106       chipset = "I965_G_1";
 107       break;
 108    case PCI_CHIP_I946_GZ:
 109       chipset = "I946_GZ";
 110       break;
 111    case PCI_CHIP_I965_GM:
 112       chipset = "I965_GM";
 113       break;
 114    case PCI_CHIP_I965_GME:
 115       chipset = "I965_GME";
 116       break;
 117    case PCI_CHIP_GM45_GM:
 118       chipset = "GM45_GM";
 119       break;
 120    case PCI_CHIP_IGD_E_G:
 121       chipset = "IGD_E_G";
 122       break;
 123    case PCI_CHIP_Q45_G:
 124       chipset = "Q45_G";
 125       break;
 126    case PCI_CHIP_G45_G:
 127       chipset = "G45_G";
 128       break;
 129    case PCI_CHIP_G41_G:
 130       chipset = "G41_G";
 131       break;
 132    case PCI_CHIP_B43_G:
 133       chipset = "B43_G";
 134       break;
 135    case PCI_CHIP_ILD_G:
 136       chipset = "ILD_G";
 137       break;
 138    case PCI_CHIP_ILM_G:
 139       chipset = "ILM_G";
 140       break;
 141    }
 142
 143    util_snprintf(buffer, sizeof(buffer), "i965 (chipset: %s)", chipset);
 144    return buffer;
 145 }
 146
 147 static int
 148 brw_get_param(struct pipe_screen *screen, int param)
 149 {
 150    switch (param) {
 151    case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
 152       return 8;
 153    case PIPE_CAP_NPOT_TEXTURES:
 154       return 1;
 155    case PIPE_CAP_TWO_SIDED_STENCIL:
 156       return 1;
 157    case PIPE_CAP_GLSL:
 158       return 0;
 159    case PIPE_CAP_ANISOTROPIC_FILTER:
 160       return 0;
 161    case PIPE_CAP_POINT_SPRITE:
 162       return 0;
 163    case PIPE_CAP_MAX_RENDER_TARGETS:
 164       return 1;
 165    case PIPE_CAP_OCCLUSION_QUERY:
 166       return 0;
 167    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 168       return 1;
 169    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 170       return 11; /* max 1024x1024 */
 171    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 172       return 8;  /* max 128x128x128 */
 173    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 174       return 11; /* max 1024x1024 */
 175    default:
 176       return 0;
 177    }
 178 }
 179
 180 static float
 181 brw_get_paramf(struct pipe_screen *screen, int param)
 182 {
 183    switch (param) {
 184    case PIPE_CAP_MAX_LINE_WIDTH:
 185       /* fall-through */
 186    case PIPE_CAP_MAX_LINE_WIDTH_AA:
 187       return 7.5;
 188
 189    case PIPE_CAP_MAX_POINT_WIDTH:
 190       /* fall-through */
 191    case PIPE_CAP_MAX_POINT_WIDTH_AA:
 192       return 255.0;
 193
 194    case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 195       return 4.0;
 196
 197    case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 198       return 16.0;
 199
 200    default:
 201       return 0;
 202    }
 203 }
 204
 205 static boolean
 206 brw_is_format_supported(struct pipe_screen *screen,
 207                          enum pipe_format format,
 208                          enum pipe_texture_target target,
 209                          unsigned tex_usage,
 210                          unsigned geom_flags)
 211 {
 212    static const enum pipe_format tex_supported[] = {
 213       PIPE_FORMAT_L8_UNORM,
 214       PIPE_FORMAT_I8_UNORM,
 215       PIPE_FORMAT_A8_UNORM,
 216       PIPE_FORMAT_L16_UNORM,
 217       /*PIPE_FORMAT_I16_UNORM,*/
 218       /*PIPE_FORMAT_A16_UNORM,*/
 219       PIPE_FORMAT_A8L8_UNORM,
 220       PIPE_FORMAT_R5G6B5_UNORM,
 221       PIPE_FORMAT_A1R5G5B5_UNORM,
 222       PIPE_FORMAT_A4R4G4B4_UNORM,
 223       PIPE_FORMAT_X8R8G8B8_UNORM,
 224       PIPE_FORMAT_A8R8G8B8_UNORM,
 225       /* video */
 226       PIPE_FORMAT_YCBCR,
 227       PIPE_FORMAT_YCBCR_REV,
 228       /* compressed */
 229       /*PIPE_FORMAT_FXT1_RGBA,*/
 230       PIPE_FORMAT_DXT1_RGB,
 231       PIPE_FORMAT_DXT1_RGBA,
 232       PIPE_FORMAT_DXT3_RGBA,
 233       PIPE_FORMAT_DXT5_RGBA,
 234       /* sRGB */
 235       PIPE_FORMAT_R8G8B8A8_SRGB,
 236       PIPE_FORMAT_A8L8_SRGB,
 237       PIPE_FORMAT_L8_SRGB,
 238       PIPE_FORMAT_DXT1_SRGB,
 239       /* depth */
 240       PIPE_FORMAT_Z32_FLOAT,
 241       PIPE_FORMAT_X8Z24_UNORM,
 242       PIPE_FORMAT_S8Z24_UNORM,
 243       PIPE_FORMAT_Z16_UNORM,
 244       /* signed */
 245       PIPE_FORMAT_R8G8_SNORM,
 246       PIPE_FORMAT_R8G8B8A8_SNORM,
 247       PIPE_FORMAT_NONE  /* list terminator */
 248    };
 249    static const enum pipe_format render_supported[] = {
 250       PIPE_FORMAT_X8R8G8B8_UNORM,
 251       PIPE_FORMAT_A8R8G8B8_UNORM,
 252       PIPE_FORMAT_R5G6B5_UNORM,
 253       PIPE_FORMAT_NONE  /* list terminator */
 254    };
 255    static const enum pipe_format depth_supported[] = {
 256       PIPE_FORMAT_Z32_FLOAT,
 257       PIPE_FORMAT_X8Z24_UNORM,
 258       PIPE_FORMAT_S8Z24_UNORM,
 259       PIPE_FORMAT_Z16_UNORM,
 260       PIPE_FORMAT_NONE  /* list terminator */
 261    };
 262    const enum pipe_format *list;
 263    uint i;
 264
 265    if (tex_usage & PIPE_TEXTURE_USAGE_DEPTH_STENCIL)
 266       list = depth_supported;
 267    else if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET)
 268       list = render_supported;
 269    else
 270       list = tex_supported;
 271
 272    for (i = 0; list[i] != PIPE_FORMAT_NONE; i++) {
 273       if (list[i] == format)
 274          return TRUE;
 275    }
 276
 277    return FALSE;
 278 }
 279
 280
 281 /*
 282  * Fence functions
 283  */
 284
 285
 286 static void
 287 brw_fence_reference(struct pipe_screen *screen,
 288                      struct pipe_fence_handle **ptr,
 289                      struct pipe_fence_handle *fence)
 290 {
 291 }
 292
 293 static int
 294 brw_fence_signalled(struct pipe_screen *screen,
 295                      struct pipe_fence_handle *fence,
 296                      unsigned flags)
 297 {
 298    return 0;                    /* XXX shouldn't this be a boolean? */
 299 }
 300
 301 static int
 302 brw_fence_finish(struct pipe_screen *screen,
 303                  struct pipe_fence_handle *fence,
 304                  unsigned flags)
 305 {
 306    return 0;
 307 }
 308
 309
 310 /*
 311  * Generic functions
 312  */
 313
 314
 315 static void
 316 brw_destroy_screen(struct pipe_screen *screen)
 317 {
 318    struct brw_screen *bscreen = brw_screen(screen);
 319
 320    if (bscreen->sws)
 321       bscreen->sws->destroy(bscreen->sws);
 322
 323    FREE(bscreen);
 324 }
 325
 326 /**
 327  * Create a new brw_screen object
 328  */
 329 struct pipe_screen *
 330 brw_create_screen(struct brw_winsys_screen *sws, uint pci_id)
 331 {
 332    struct brw_screen *bscreen;
 333    struct brw_chipset chipset;
 334
 335 #ifdef DEBUG
 336    BRW_DEBUG = debug_get_flags_option("BRW_DEBUG", debug_names, 0);
 337    BRW_DEBUG |= debug_get_flags_option("INTEL_DEBUG", debug_names, 0);
 338    BRW_DEBUG |= DEBUG_STATS | DEBUG_MIN_URB | DEBUG_WM;
 339
 340    BRW_DUMP = debug_get_flags_option("BRW_DUMP", dump_names, 0);
 341 #endif
 342
 343    memset(&chipset, 0, sizeof chipset);
 344
 345    chipset.pci_id = pci_id;
 346
 347    switch (pci_id) {
 348    case PCI_CHIP_I965_G:
 349    case PCI_CHIP_I965_Q:
 350    case PCI_CHIP_I965_G_1:
 351    case PCI_CHIP_I946_GZ:
 352    case PCI_CHIP_I965_GM:
 353    case PCI_CHIP_I965_GME:
 354       chipset.is_965 = TRUE;
 355       break;
 356
 357    case PCI_CHIP_GM45_GM:
 358    case PCI_CHIP_IGD_E_G:
 359    case PCI_CHIP_Q45_G:
 360    case PCI_CHIP_G45_G:
 361    case PCI_CHIP_G41_G:
 362    case PCI_CHIP_B43_G:
 363       chipset.is_g4x = TRUE;
 364       break;
 365
 366    case PCI_CHIP_ILD_G:
 367    case PCI_CHIP_ILM_G:
 368       chipset.is_igdng = TRUE;
 369       break;
 370
 371    default:
 372       debug_printf("%s: unknown pci id 0x%x, cannot create screen\n",
 373                    __FUNCTION__, pci_id);
 374       return NULL;
 375    }
 376
 377
 378    bscreen = CALLOC_STRUCT(brw_screen);
 379    if (!bscreen)
 380       return NULL;
 381
 382    bscreen->chipset = chipset;
 383    bscreen->sws = sws;
 384    bscreen->base.winsys = NULL;
 385    bscreen->base.destroy = brw_destroy_screen;
 386    bscreen->base.get_name = brw_get_name;
 387    bscreen->base.get_vendor = brw_get_vendor;
 388    bscreen->base.get_param = brw_get_param;
 389    bscreen->base.get_paramf = brw_get_paramf;
 390    bscreen->base.is_format_supported = brw_is_format_supported;
 391    bscreen->base.fence_reference = brw_fence_reference;
 392    bscreen->base.fence_signalled = brw_fence_signalled;
 393    bscreen->base.fence_finish = brw_fence_finish;
 394
 395    brw_screen_tex_init(bscreen);
 396    brw_screen_tex_surface_init(bscreen);
 397    brw_screen_buffer_init(bscreen);
 398
 399    bscreen->no_tiling = debug_get_option("BRW_NO_TILING", FALSE) != NULL;
 400
 401
 402    return &bscreen->base;
 403 }