src/gallium/drivers/i965/brw_screen_surface.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32 #include "util/u_memory.h"
  33 #include "util/u_simple_list.h"
  34
  35 #include "pipe/p_screen.h"
  36 #include "brw_screen.h"
  37 #include "brw_defines.h"
  38 #include "brw_winsys.h"
  39
  40 enum {
  41    BRW_VIEW_LINEAR,
  42    BRW_VIEW_IN_PLACE
  43 };
  44
  45
  46 static boolean need_linear_view( struct brw_screen *brw_screen,
  47                                  struct brw_texture *brw_texture,
  48                                  union brw_surface_id id,
  49                                  unsigned usage )
  50 {
  51 #if 0
  52    /* XXX: what about IDGNG?
  53     */
  54    if (!BRW_IS_G4X(brw->brw_screen->pci_id))
  55    {
  56       struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
  57       struct intel_renderbuffer *irb = intel_renderbuffer(rb);
  58
  59       /* The original gen4 hardware couldn't set up WM surfaces pointing
  60        * at an offset within a tile, which can happen when rendering to
  61        * anything but the base level of a texture or the +X face/0 depth.
  62        * This was fixed with the 4 Series hardware.
  63        *
  64        * For these original chips, you would have to make the depth and
  65        * color destination surfaces include information on the texture
  66        * type, LOD, face, and various limits to use them as a destination.
  67        *
  68        * This is easy in Gallium as surfaces are all backed by
  69        * textures, but there's also a nasty requirement that the depth
  70        * and the color surfaces all be of the same LOD, which is
  71        * harder to get around as we can't look at a surface in
  72        * isolation and decide if it's legal.
  73        *
  74        * Instead, end up being pessimistic and say that for i965,
  75        * ... ??
  76        */
  77       if (brw_tex->tiling != I915_TILING_NONE &&
  78           (brw_tex_image_offset(brw_tex, face, level, zslize) & 4095)) {
  79          if (BRW_DEBUG & DEBUG_VIEW)
  80             debug_printf("%s: need surface view for non-aligned tex image\n",
  81                          __FUNCTION__);
  82          return GL_TRUE;
  83       }
  84    }
  85 #endif
  86
  87    /* Tiled 3d textures don't have subsets that look like 2d surfaces:
  88     */
  89
  90    /* Everything else should be fine to render to in-place:
  91     */
  92    return GL_FALSE;
  93 }
  94
  95 /* Look at all texture views and figure out if any of them need to be
  96  * back-copied into the texture for sampling
  97  */
  98 void brw_update_texture( struct brw_screen *brw_screen,
  99                          struct brw_texture *tex )
 100 {
 101    /* currently nothing to do */
 102 }
 103
 104
 105 /* Create a new surface with linear layout to serve as a render-target
 106  * where it would be illegal (perhaps due to tiling constraints) to do
 107  * this in-place.
 108  *
 109  * Currently not implmented, not sure if it's needed.
 110  */
 111 static struct brw_surface *create_linear_view( struct brw_screen *brw_screen,
 112                                                struct brw_texture *tex,
 113                                                union brw_surface_id id,
 114                                                unsigned usage )
 115 {
 116    return NULL;
 117 }
 118
 119
 120 /* Create a pipe_surface that just points directly into the existing
 121  * texture's storage.
 122  */
 123 static struct brw_surface *create_in_place_view( struct brw_screen *brw_screen,
 124                                                   struct brw_texture *tex,
 125                                                   union brw_surface_id id,
 126                                                   unsigned usage )
 127 {
 128    struct brw_surface *surface;
 129
 130    surface = CALLOC_STRUCT(brw_surface);
 131    if (surface == NULL)
 132       return NULL;
 133
 134    pipe_reference_init(&surface->base.reference, 1);
 135
 136    /* XXX: ignoring render-to-slice-of-3d-texture
 137     */
 138    assert(id.bits.zslice == 0);
 139
 140    surface->base.format = tex->base.format;
 141    surface->base.width = tex->base.width[id.bits.level];
 142    surface->base.height = tex->base.height[id.bits.level];
 143    surface->base.offset = tex->image_offset[id.bits.level][id.bits.face];
 144    surface->base.usage = usage;
 145    surface->base.zslice = id.bits.zslice;
 146    surface->base.face = id.bits.face;
 147    surface->base.level = id.bits.level;
 148    surface->id = id;
 149    surface->cpp = tex->cpp;
 150    surface->pitch = tex->pitch;
 151    surface->tiling = tex->tiling;
 152
 153    bo_reference( &surface->bo, tex->bo );
 154    pipe_texture_reference( &surface->base.texture, &tex->base );
 155
 156    surface->ss.ss0.surface_format = tex->ss.ss0.surface_format;
 157    surface->ss.ss0.surface_type = BRW_SURFACE_2D;
 158
 159    if (tex->tiling == BRW_TILING_NONE) {
 160       surface->ss.ss1.base_addr = surface->base.offset;
 161    } else {
 162       uint32_t tile_offset = surface->base.offset % 4096;
 163
 164       surface->ss.ss1.base_addr = surface->base.offset - tile_offset;
 165
 166       if (brw_screen->chipset.is_g4x) {
 167          if (tex->tiling == BRW_TILING_X) {
 168             /* Note that the low bits of these fields are missing, so
 169              * there's the possibility of getting in trouble.
 170              */
 171             surface->ss.ss5.x_offset = (tile_offset % 512) / tex->cpp / 4;
 172             surface->ss.ss5.y_offset = tile_offset / 512 / 2;
 173          } else {
 174             surface->ss.ss5.x_offset = (tile_offset % 128) / tex->cpp / 4;
 175             surface->ss.ss5.y_offset = tile_offset / 128 / 2;
 176          }
 177       }
 178       else {
 179          assert(tile_offset == 0);
 180       }
 181    }
 182
 183 #if 0
 184    if (region_bo != NULL)
 185       surface->ss.ss1.base_addr += region_bo->offset; /* reloc */
 186 #endif
 187
 188    surface->ss.ss2.width = surface->base.width - 1;
 189    surface->ss.ss2.height = surface->base.height - 1;
 190    surface->ss.ss3.tiled_surface = tex->ss.ss3.tiled_surface;
 191    surface->ss.ss3.tile_walk = tex->ss.ss3.tile_walk;
 192    surface->ss.ss3.pitch = tex->ss.ss3.pitch;
 193
 194    return surface;
 195 }
 196
 197 /* Get a surface which is view into a texture
 198  */
 199 static struct pipe_surface *brw_get_tex_surface(struct pipe_screen *screen,
 200                                                 struct pipe_texture *pt,
 201                                                 unsigned face, unsigned level,
 202                                                 unsigned zslice,
 203                                                 unsigned usage )
 204 {
 205    struct brw_texture *tex = brw_texture(pt);
 206    struct brw_screen *bscreen = brw_screen(screen);
 207    struct brw_surface *surface;
 208    union brw_surface_id id;
 209    int type;
 210
 211    id.bits.face = face;
 212    id.bits.level = level;
 213    id.bits.zslice = zslice;
 214
 215    if (need_linear_view(bscreen, tex, id, usage))
 216       type = BRW_VIEW_LINEAR;
 217    else
 218       type = BRW_VIEW_IN_PLACE;
 219
 220
 221    foreach (surface, &tex->views[type]) {
 222       if (id.value == surface->id.value)
 223          return &surface->base;
 224    }
 225
 226    switch (type) {
 227    case BRW_VIEW_LINEAR:
 228       surface = create_linear_view( bscreen, tex, id, usage );
 229       break;
 230    case BRW_VIEW_IN_PLACE:
 231       surface = create_in_place_view( bscreen, tex, id, usage );
 232       break;
 233    default:
 234       return NULL;
 235    }
 236
 237    insert_at_head( &tex->views[type], surface );
 238    return &surface->base;
 239 }
 240
 241
 242 static void brw_tex_surface_destroy( struct pipe_surface *surf )
 243 {
 244    struct brw_surface *surface = brw_surface(surf);
 245
 246    /* Unreference texture, shared buffer:
 247     */
 248    remove_from_list(surface);
 249    bo_reference(&surface->bo, NULL);
 250    pipe_texture_reference( &surface->base.texture, NULL );
 251
 252
 253    FREE(surface);
 254 }
 255
 256
 257 void brw_screen_tex_surface_init( struct brw_screen *brw_screen )
 258 {
 259    brw_screen->base.get_tex_surface = brw_get_tex_surface;
 260    brw_screen->base.tex_surface_destroy = brw_tex_surface_destroy;
 261 }