Merge commit 'origin/gallium-master-merge'
[mesa.git] / src / gallium / drivers / i965simple / brw_clip_util.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #include "brw_defines.h"
34 #include "brw_context.h"
35 #include "brw_eu.h"
36 #include "brw_util.h"
37 #include "brw_clip.h"
38
39
40
41
42
43 static struct brw_reg get_tmp( struct brw_clip_compile *c )
44 {
45 struct brw_reg tmp = brw_vec4_grf(c->last_tmp, 0);
46
47 if (++c->last_tmp > c->prog_data.total_grf)
48 c->prog_data.total_grf = c->last_tmp;
49
50 return tmp;
51 }
52
53 static void release_tmp( struct brw_clip_compile *c, struct brw_reg tmp )
54 {
55 if (tmp.nr == c->last_tmp-1)
56 c->last_tmp--;
57 }
58
59
60 static struct brw_reg make_plane_ud(unsigned x, unsigned y, unsigned z, unsigned w)
61 {
62 return brw_imm_ud((w<<24) | (z<<16) | (y<<8) | x);
63 }
64
65
66 void brw_clip_init_planes( struct brw_clip_compile *c )
67 {
68 struct brw_compile *p = &c->func;
69
70 if (!c->key.nr_userclip) {
71 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 0), make_plane_ud( 0, 0, 0xff, 1));
72 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 1), make_plane_ud( 0, 0, 1, 1));
73 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 2), make_plane_ud( 0, 0xff, 0, 1));
74 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 3), make_plane_ud( 0, 1, 0, 1));
75 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 4), make_plane_ud(0xff, 0, 0, 1));
76 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 5), make_plane_ud( 1, 0, 0, 1));
77 }
78 }
79
80
81
82 #define W 3
83
84 /* Project 'pos' to screen space (or back again), overwrite with results:
85 */
86 static void brw_clip_project_position(struct brw_clip_compile *c, struct brw_reg pos )
87 {
88 struct brw_compile *p = &c->func;
89
90 /* calc rhw
91 */
92 brw_math_invert(p, get_element(pos, W), get_element(pos, W));
93
94 /* value.xyz *= value.rhw
95 */
96 brw_set_access_mode(p, BRW_ALIGN_16);
97 brw_MUL(p, brw_writemask(pos, TGSI_WRITEMASK_XYZ), pos, brw_swizzle1(pos, W));
98 brw_set_access_mode(p, BRW_ALIGN_1);
99 }
100
101
102 static void brw_clip_project_vertex( struct brw_clip_compile *c,
103 struct brw_indirect vert_addr )
104 {
105 #if 0
106 struct brw_compile *p = &c->func;
107 struct brw_reg tmp = get_tmp(c);
108
109 /* Fixup position. Extract from the original vertex and re-project
110 * to screen space:
111 */
112 brw_MOV(p, tmp, deref_4f(vert_addr, c->offset[VERT_RESULT_HPOS]));
113 brw_clip_project_position(c, tmp);
114 brw_MOV(p, deref_4f(vert_addr, c->header_position_offset), tmp);
115
116 release_tmp(c, tmp);
117 #else
118 #warning "disabled"
119 #endif
120 }
121
122
123
124
125 /* Interpolate between two vertices and put the result into a0.0.
126 * Increment a0.0 accordingly.
127 */
128 void brw_clip_interp_vertex( struct brw_clip_compile *c,
129 struct brw_indirect dest_ptr,
130 struct brw_indirect v0_ptr, /* from */
131 struct brw_indirect v1_ptr, /* to */
132 struct brw_reg t0,
133 boolean force_edgeflag)
134 {
135 #if 0
136 struct brw_compile *p = &c->func;
137 struct brw_reg tmp = get_tmp(c);
138 unsigned i;
139
140 /* Just copy the vertex header:
141 */
142 brw_copy_indirect_to_indirect(p, dest_ptr, v0_ptr, 1);
143
144 /* Iterate over each attribute (could be done in pairs?)
145 */
146 for (i = 0; i < c->nr_attrs; i++) {
147 unsigned delta = i*16 + 32;
148
149 if (delta == c->offset[VERT_RESULT_EDGE]) {
150 if (force_edgeflag)
151 brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(1));
152 else
153 brw_MOV(p, deref_4f(dest_ptr, delta), deref_4f(v0_ptr, delta));
154 }
155 else {
156 /* Interpolate:
157 *
158 * New = attr0 + t*attr1 - t*attr0
159 */
160 brw_MUL(p,
161 vec4(brw_null_reg()),
162 deref_4f(v1_ptr, delta),
163 t0);
164
165 brw_MAC(p,
166 tmp,
167 negate(deref_4f(v0_ptr, delta)),
168 t0);
169
170 brw_ADD(p,
171 deref_4f(dest_ptr, delta),
172 deref_4f(v0_ptr, delta),
173 tmp);
174 }
175 }
176
177 if (i & 1) {
178 unsigned delta = i*16 + 32;
179 brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(0));
180 }
181
182 release_tmp(c, tmp);
183
184 /* Recreate the projected (NDC) coordinate in the new vertex
185 * header:
186 */
187 brw_clip_project_vertex(c, dest_ptr );
188 #else
189 #warning "disabled"
190 #endif
191 }
192
193
194
195
196 #define MAX_MRF 16
197
198 void brw_clip_emit_vue(struct brw_clip_compile *c,
199 struct brw_indirect vert,
200 boolean allocate,
201 boolean eot,
202 unsigned header)
203 {
204 struct brw_compile *p = &c->func;
205 unsigned start = c->last_mrf;
206
207 assert(!(allocate && eot));
208
209 /* Cycle through mrf regs - probably futile as we have to wait for
210 * the allocation response anyway. Also, the order this function
211 * is invoked doesn't correspond to the order the instructions will
212 * be executed, so it won't have any effect in many cases.
213 */
214 #if 0
215 if (start + c->nr_regs + 1 >= MAX_MRF)
216 start = 0;
217
218 c->last_mrf = start + c->nr_regs + 1;
219 #endif
220
221 /* Copy the vertex from vertn into m1..mN+1:
222 */
223 brw_copy_from_indirect(p, brw_message_reg(start+1), vert, c->nr_regs);
224
225 /* Overwrite PrimType and PrimStart in the message header, for
226 * each vertex in turn:
227 */
228 brw_MOV(p, get_element_ud(c->reg.R0, 2), brw_imm_ud(header));
229
230
231 /* Send each vertex as a seperate write to the urb. This
232 * is different to the concept in brw_sf_emit.c, where
233 * subsequent writes are used to build up a single urb
234 * entry. Each of these writes instantiates a seperate
235 * urb entry - (I think... what about 'allocate'?)
236 */
237 brw_urb_WRITE(p,
238 allocate ? c->reg.R0 : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
239 start,
240 c->reg.R0,
241 allocate,
242 1, /* used */
243 c->nr_regs + 1, /* msg length */
244 allocate ? 1 : 0, /* response_length */
245 eot, /* eot */
246 1, /* writes_complete */
247 0, /* urb offset */
248 BRW_URB_SWIZZLE_NONE);
249 }
250
251
252
253 void brw_clip_kill_thread(struct brw_clip_compile *c)
254 {
255 struct brw_compile *p = &c->func;
256
257 /* Send an empty message to kill the thread and release any
258 * allocated urb entry:
259 */
260 brw_urb_WRITE(p,
261 retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
262 0,
263 c->reg.R0,
264 0, /* allocate */
265 0, /* used */
266 0, /* msg len */
267 0, /* response len */
268 1, /* eot */
269 1, /* writes complete */
270 0,
271 BRW_URB_SWIZZLE_NONE);
272 }
273
274
275
276
277 struct brw_reg brw_clip_plane0_address( struct brw_clip_compile *c )
278 {
279 return brw_address(c->reg.fixed_planes);
280 }
281
282
283 struct brw_reg brw_clip_plane_stride( struct brw_clip_compile *c )
284 {
285 if (c->key.nr_userclip) {
286 return brw_imm_uw(16);
287 }
288 else {
289 return brw_imm_uw(4);
290 }
291 }
292
293
294 /* If flatshading, distribute color from provoking vertex prior to
295 * clipping.
296 */
297 void brw_clip_copy_colors( struct brw_clip_compile *c,
298 unsigned to, unsigned from )
299 {
300 #if 0
301 struct brw_compile *p = &c->func;
302
303 if (c->offset[VERT_RESULT_COL0])
304 brw_MOV(p,
305 byte_offset(c->reg.vertex[to], c->offset[VERT_RESULT_COL0]),
306 byte_offset(c->reg.vertex[from], c->offset[VERT_RESULT_COL0]));
307
308 if (c->offset[VERT_RESULT_COL1])
309 brw_MOV(p,
310 byte_offset(c->reg.vertex[to], c->offset[VERT_RESULT_COL1]),
311 byte_offset(c->reg.vertex[from], c->offset[VERT_RESULT_COL1]));
312
313 if (c->offset[VERT_RESULT_BFC0])
314 brw_MOV(p,
315 byte_offset(c->reg.vertex[to], c->offset[VERT_RESULT_BFC0]),
316 byte_offset(c->reg.vertex[from], c->offset[VERT_RESULT_BFC0]));
317
318 if (c->offset[VERT_RESULT_BFC1])
319 brw_MOV(p,
320 byte_offset(c->reg.vertex[to], c->offset[VERT_RESULT_BFC1]),
321 byte_offset(c->reg.vertex[from], c->offset[VERT_RESULT_BFC1]));
322 #else
323 #warning "disabled"
324 #endif
325 }
326
327
328
329 void brw_clip_init_clipmask( struct brw_clip_compile *c )
330 {
331 struct brw_compile *p = &c->func;
332 struct brw_reg incoming = get_element_ud(c->reg.R0, 2);
333
334 /* Shift so that lowest outcode bit is rightmost:
335 */
336 brw_SHR(p, c->reg.planemask, incoming, brw_imm_ud(26));
337
338 if (c->key.nr_userclip) {
339 struct brw_reg tmp = retype(vec1(get_tmp(c)), BRW_REGISTER_TYPE_UD);
340
341 /* Rearrange userclip outcodes so that they come directly after
342 * the fixed plane bits.
343 */
344 brw_AND(p, tmp, incoming, brw_imm_ud(0x3f<<14));
345 brw_SHR(p, tmp, tmp, brw_imm_ud(8));
346 brw_OR(p, c->reg.planemask, c->reg.planemask, tmp);
347
348 release_tmp(c, tmp);
349 }
350 }
351