2 * Mesa 3-D graphics library
4 * Copyright (C) 2014 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #ifndef ILO_BUILDER_MI_H
29 #define ILO_BUILDER_MI_H
31 #include "genhw/genhw.h"
32 #include "intel_winsys.h"
36 #include "ilo_builder.h"
39 gen6_MI_STORE_DATA_IMM(struct ilo_builder
*builder
,
40 struct intel_bo
*bo
, uint32_t bo_offset
,
43 const uint8_t cmd_len
= (ilo_dev_gen(builder
->dev
) >= ILO_GEN(8)) ? 6 : 5;
44 uint32_t reloc_flags
= INTEL_RELOC_WRITE
;
48 ILO_DEV_ASSERT(builder
->dev
, 6, 8);
50 assert(bo_offset
% 8 == 0);
52 pos
= ilo_builder_batch_pointer(builder
, cmd_len
, &dw
);
54 dw
[0] = GEN6_MI_CMD(MI_STORE_DATA_IMM
) | (cmd_len
- 2);
55 /* must use GGTT on GEN6 as in PIPE_CONTROL */
56 if (ilo_dev_gen(builder
->dev
) == ILO_GEN(6)) {
57 dw
[0] |= GEN6_MI_STORE_DATA_IMM_DW0_USE_GGTT
;
58 reloc_flags
|= INTEL_RELOC_GGTT
;
63 if (ilo_dev_gen(builder
->dev
) >= ILO_GEN(8)) {
64 dw
[4] = (uint32_t) val
;
65 dw
[5] = (uint32_t) (val
>> 32);
67 ilo_builder_batch_reloc64(builder
, pos
+ 2, bo
, bo_offset
, reloc_flags
);
69 dw
[3] = (uint32_t) val
;
70 dw
[4] = (uint32_t) (val
>> 32);
72 ilo_builder_batch_reloc(builder
, pos
+ 2, bo
, bo_offset
, reloc_flags
);
77 gen6_MI_LOAD_REGISTER_IMM(struct ilo_builder
*builder
,
78 uint32_t reg
, uint32_t val
)
80 const uint8_t cmd_len
= 3;
83 ILO_DEV_ASSERT(builder
->dev
, 6, 8);
87 ilo_builder_batch_pointer(builder
, cmd_len
, &dw
);
89 dw
[0] = GEN6_MI_CMD(MI_LOAD_REGISTER_IMM
) | (cmd_len
- 2);
95 gen6_MI_STORE_REGISTER_MEM(struct ilo_builder
*builder
, uint32_t reg
,
96 struct intel_bo
*bo
, uint32_t bo_offset
)
98 const uint8_t cmd_len
= (ilo_dev_gen(builder
->dev
) >= ILO_GEN(8)) ? 4 : 3;
99 uint32_t reloc_flags
= INTEL_RELOC_WRITE
;
103 ILO_DEV_ASSERT(builder
->dev
, 6, 8);
105 assert(reg
% 4 == 0 && bo_offset
% 4 == 0);
107 pos
= ilo_builder_batch_pointer(builder
, cmd_len
, &dw
);
109 dw
[0] = GEN6_MI_CMD(MI_STORE_REGISTER_MEM
) | (cmd_len
- 2);
112 if (ilo_dev_gen(builder
->dev
) >= ILO_GEN(8)) {
113 ilo_builder_batch_reloc64(builder
, pos
+ 2, bo
, bo_offset
, reloc_flags
);
115 /* must use GGTT on Gen6 as in PIPE_CONTROL */
116 if (ilo_dev_gen(builder
->dev
) == ILO_GEN(6)) {
117 dw
[0] |= GEN6_MI_STORE_REGISTER_MEM_DW0_USE_GGTT
;
118 reloc_flags
|= INTEL_RELOC_GGTT
;
121 ilo_builder_batch_reloc(builder
, pos
+ 2, bo
, bo_offset
, reloc_flags
);
126 gen6_MI_FLUSH_DW(struct ilo_builder
*builder
)
128 const uint8_t cmd_len
= 4;
131 ILO_DEV_ASSERT(builder
->dev
, 6, 8);
133 ilo_builder_batch_pointer(builder
, cmd_len
, &dw
);
135 dw
[0] = GEN6_MI_CMD(MI_FLUSH_DW
) | (cmd_len
- 2);
142 gen6_MI_REPORT_PERF_COUNT(struct ilo_builder
*builder
,
143 struct intel_bo
*bo
, uint32_t bo_offset
,
146 const uint8_t cmd_len
= 3;
147 uint32_t reloc_flags
= INTEL_RELOC_WRITE
;
151 ILO_DEV_ASSERT(builder
->dev
, 6, 7.5);
153 assert(bo_offset
% 64 == 0);
155 /* must use GGTT on GEN6 as in PIPE_CONTROL */
156 if (ilo_dev_gen(builder
->dev
) == ILO_GEN(6)) {
157 bo_offset
|= GEN6_MI_REPORT_PERF_COUNT_DW1_USE_GGTT
;
158 reloc_flags
|= INTEL_RELOC_GGTT
;
161 pos
= ilo_builder_batch_pointer(builder
, cmd_len
, &dw
);
163 dw
[0] = GEN6_MI_CMD(MI_REPORT_PERF_COUNT
) | (cmd_len
- 2);
166 ilo_builder_batch_reloc(builder
, pos
+ 1, bo
, bo_offset
, reloc_flags
);
170 gen7_MI_LOAD_REGISTER_MEM(struct ilo_builder
*builder
, uint32_t reg
,
171 struct intel_bo
*bo
, uint32_t bo_offset
)
173 const uint8_t cmd_len
= (ilo_dev_gen(builder
->dev
) >= ILO_GEN(8)) ? 4 : 3;
177 ILO_DEV_ASSERT(builder
->dev
, 7, 8);
179 assert(reg
% 4 == 0 && bo_offset
% 4 == 0);
181 pos
= ilo_builder_batch_pointer(builder
, cmd_len
, &dw
);
183 dw
[0] = GEN7_MI_CMD(MI_LOAD_REGISTER_MEM
) | (cmd_len
- 2);
186 if (ilo_dev_gen(builder
->dev
) >= ILO_GEN(8))
187 ilo_builder_batch_reloc64(builder
, pos
+ 2, bo
, bo_offset
, 0);
189 ilo_builder_batch_reloc(builder
, pos
+ 2, bo
, bo_offset
, 0);
193 * Add a MI_BATCH_BUFFER_END to the batch buffer. Pad with MI_NOOP if
197 gen6_mi_batch_buffer_end(struct ilo_builder
*builder
)
200 * From the Sandy Bridge PRM, volume 1 part 1, page 107:
202 * "The batch buffer must be QWord aligned and a multiple of QWords in
205 const bool pad
= !(builder
->writers
[ILO_BUILDER_WRITER_BATCH
].used
& 0x7);
208 ILO_DEV_ASSERT(builder
->dev
, 6, 8);
211 ilo_builder_batch_pointer(builder
, 2, &dw
);
212 dw
[0] = GEN6_MI_CMD(MI_BATCH_BUFFER_END
);
213 dw
[1] = GEN6_MI_CMD(MI_NOOP
);
215 ilo_builder_batch_pointer(builder
, 1, &dw
);
216 dw
[0] = GEN6_MI_CMD(MI_BATCH_BUFFER_END
);
220 #endif /* ILO_BUILDER_MI_H */