2 * Mesa 3-D graphics library
4 * Copyright (C) 2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "genhw/genhw.h"
29 #include "util/u_dual_blend.h"
30 #include "util/u_prim.h"
32 #include "ilo_blitter.h"
33 #include "ilo_builder_3d.h"
34 #include "ilo_builder_mi.h"
35 #include "ilo_builder_render.h"
36 #include "ilo_query.h"
37 #include "ilo_shader.h"
38 #include "ilo_state.h"
39 #include "ilo_render_gen.h"
42 * A wrapper for gen6_PIPE_CONTROL().
45 gen6_pipe_control(struct ilo_render
*r
, uint32_t dw1
)
47 struct intel_bo
*bo
= (dw1
& GEN6_PIPE_CONTROL_WRITE__MASK
) ?
48 r
->workaround_bo
: NULL
;
50 ILO_DEV_ASSERT(r
->dev
, 6, 6);
52 gen6_PIPE_CONTROL(r
->builder
, dw1
, bo
, 0, false);
54 r
->state
.current_pipe_control_dw1
|= dw1
;
56 assert(!r
->state
.deferred_pipe_control_dw1
);
60 * This should be called before PIPE_CONTROL.
63 gen6_wa_pre_pipe_control(struct ilo_render
*r
, uint32_t dw1
)
66 * From the Sandy Bridge PRM, volume 2 part 1, page 60:
68 * "Pipe-control with CS-stall bit set must be sent BEFORE the
69 * pipe-control with a post-sync op and no write-cache flushes."
71 * This WA may also be triggered indirectly by the other two WAs on the
74 * "Before any depth stall flush (including those produced by
75 * non-pipelined state commands), software needs to first send a
76 * PIPE_CONTROL with no bits set except Post-Sync Operation != 0."
78 * "Before a PIPE_CONTROL with Write Cache Flush Enable =1, a
79 * PIPE_CONTROL with any non-zero post-sync-op is required."
81 const bool direct_wa_cond
= (dw1
& GEN6_PIPE_CONTROL_WRITE__MASK
) &&
82 !(dw1
& GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH
);
83 const bool indirect_wa_cond
= (dw1
& GEN6_PIPE_CONTROL_DEPTH_STALL
) |
84 (dw1
& GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH
);
86 ILO_DEV_ASSERT(r
->dev
, 6, 6);
88 if (!direct_wa_cond
&& !indirect_wa_cond
)
91 if (!(r
->state
.current_pipe_control_dw1
& GEN6_PIPE_CONTROL_CS_STALL
)) {
93 * From the Sandy Bridge PRM, volume 2 part 1, page 73:
95 * "1 of the following must also be set (when CS stall is set):
97 * - Depth Cache Flush Enable ([0] of DW1)
98 * - Stall at Pixel Scoreboard ([1] of DW1)
99 * - Depth Stall ([13] of DW1)
100 * - Post-Sync Operation ([13] of DW1)
101 * - Render Target Cache Flush Enable ([12] of DW1)
102 * - Notify Enable ([8] of DW1)"
104 * Because of the WAs above, we have to pick Stall at Pixel Scoreboard.
106 const uint32_t direct_wa
= GEN6_PIPE_CONTROL_CS_STALL
|
107 GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL
;
109 gen6_pipe_control(r
, direct_wa
);
112 if (indirect_wa_cond
&&
113 !(r
->state
.current_pipe_control_dw1
& GEN6_PIPE_CONTROL_WRITE__MASK
)) {
114 const uint32_t indirect_wa
= GEN6_PIPE_CONTROL_WRITE_IMM
;
116 gen6_pipe_control(r
, indirect_wa
);
121 * This should be called before any non-pipelined state command.
124 gen6_wa_pre_non_pipelined(struct ilo_render
*r
)
126 ILO_DEV_ASSERT(r
->dev
, 6, 6);
128 /* non-pipelined state commands produce depth stall */
129 gen6_wa_pre_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
133 gen6_wa_post_3dstate_constant_vs(struct ilo_render
*r
)
136 * According to upload_vs_state() of the classic driver, we need to emit a
137 * PIPE_CONTROL after 3DSTATE_CONSTANT_VS, otherwise the command is kept
138 * being buffered by VS FF, to the point that the FF dies.
140 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_STALL
|
141 GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
|
142 GEN6_PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
144 gen6_wa_pre_pipe_control(r
, dw1
);
146 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
147 gen6_pipe_control(r
, dw1
);
151 gen6_wa_pre_3dstate_wm_max_threads(struct ilo_render
*r
)
154 * From the Sandy Bridge PRM, volume 2 part 1, page 274:
156 * "A PIPE_CONTROL command, with only the Stall At Pixel Scoreboard
157 * field set (DW1 Bit 1), must be issued prior to any change to the
158 * value in this field (Maximum Number of Threads in 3DSTATE_WM)"
160 const uint32_t dw1
= GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL
;
162 ILO_DEV_ASSERT(r
->dev
, 6, 6);
164 gen6_wa_pre_pipe_control(r
, dw1
);
166 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
167 gen6_pipe_control(r
, dw1
);
171 gen6_wa_pre_3dstate_multisample(struct ilo_render
*r
)
174 * From the Sandy Bridge PRM, volume 2 part 1, page 305:
176 * "Driver must guarentee that all the caches in the depth pipe are
177 * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
178 * requires driver to send a PIPE_CONTROL with a CS stall along with a
179 * Depth Flush prior to this command."
181 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
182 GEN6_PIPE_CONTROL_CS_STALL
;
184 ILO_DEV_ASSERT(r
->dev
, 6, 6);
186 gen6_wa_pre_pipe_control(r
, dw1
);
188 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
189 gen6_pipe_control(r
, dw1
);
193 gen6_wa_pre_depth(struct ilo_render
*r
)
195 ILO_DEV_ASSERT(r
->dev
, 6, 6);
198 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
200 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
201 * any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
202 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
203 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
204 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
205 * Depth Flush Bit set, followed by another pipelined depth stall
206 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
207 * guarantee that the pipeline from WM onwards is already flushed
208 * (e.g., via a preceding MI_FLUSH)."
210 * According to the classic driver, it also applies for GEN6.
212 gen6_wa_pre_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
|
213 GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
215 gen6_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
216 gen6_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
217 gen6_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
220 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
223 gen6_draw_common_select(struct ilo_render
*r
,
224 const struct ilo_state_vector
*vec
,
225 struct ilo_render_draw_session
*session
)
227 /* PIPELINE_SELECT */
228 if (r
->hw_ctx_changed
) {
229 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
230 gen6_wa_pre_non_pipelined(r
);
232 gen6_PIPELINE_SELECT(r
->builder
, 0x0);
237 gen6_draw_common_sip(struct ilo_render
*r
,
238 const struct ilo_state_vector
*vec
,
239 struct ilo_render_draw_session
*session
)
242 if (r
->hw_ctx_changed
) {
243 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
244 gen6_wa_pre_non_pipelined(r
);
246 gen6_STATE_SIP(r
->builder
, 0);
251 gen6_draw_common_base_address(struct ilo_render
*r
,
252 const struct ilo_state_vector
*vec
,
253 struct ilo_render_draw_session
*session
)
255 /* STATE_BASE_ADDRESS */
256 if (r
->state_bo_changed
|| r
->instruction_bo_changed
||
257 r
->batch_bo_changed
) {
258 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
259 gen6_wa_pre_non_pipelined(r
);
261 gen6_state_base_address(r
->builder
, r
->hw_ctx_changed
);
264 * From the Sandy Bridge PRM, volume 1 part 1, page 28:
266 * "The following commands must be reissued following any change to
267 * the base addresses:
269 * * 3DSTATE_BINDING_TABLE_POINTERS
270 * * 3DSTATE_SAMPLER_STATE_POINTERS
271 * * 3DSTATE_VIEWPORT_STATE_POINTERS
272 * * 3DSTATE_CC_POINTERS
273 * * MEDIA_STATE_POINTERS"
275 * 3DSTATE_SCISSOR_STATE_POINTERS is not on the list, but it is
276 * reasonable to also reissue the command. Same to PCB.
278 session
->viewport_changed
= true;
280 session
->scissor_changed
= true;
282 session
->blend_changed
= true;
283 session
->dsa_changed
= true;
284 session
->cc_changed
= true;
286 session
->sampler_vs_changed
= true;
287 session
->sampler_gs_changed
= true;
288 session
->sampler_fs_changed
= true;
290 session
->pcb_vs_changed
= true;
291 session
->pcb_gs_changed
= true;
292 session
->pcb_fs_changed
= true;
294 session
->binding_table_vs_changed
= true;
295 session
->binding_table_gs_changed
= true;
296 session
->binding_table_fs_changed
= true;
301 gen6_draw_common_urb(struct ilo_render
*r
,
302 const struct ilo_state_vector
*vec
,
303 struct ilo_render_draw_session
*session
)
306 if (DIRTY(VE
) || DIRTY(VS
) || DIRTY(GS
)) {
307 const bool gs_active
= (vec
->gs
|| (vec
->vs
&&
308 ilo_shader_get_kernel_param(vec
->vs
, ILO_KERNEL_VS_GEN6_SO
)));
309 int vs_entry_size
, gs_entry_size
;
310 int vs_total_size
, gs_total_size
;
312 vs_entry_size
= (vec
->vs
) ?
313 ilo_shader_get_kernel_param(vec
->vs
, ILO_KERNEL_OUTPUT_COUNT
) : 0;
316 * As indicated by 2e712e41db0c0676e9f30fc73172c0e8de8d84d4, VF and VS
317 * share VUE handles. The VUE allocation size must be large enough to
318 * store either VF outputs (number of VERTEX_ELEMENTs) and VS outputs.
320 * I am not sure if the PRM explicitly states that VF and VS share VUE
321 * handles. But here is a citation that implies so:
323 * From the Sandy Bridge PRM, volume 2 part 1, page 44:
325 * "Once a FF stage that spawn threads has sufficient input to
326 * initiate a thread, it must guarantee that it is safe to request
327 * the thread initiation. For all these FF stages, this check is
330 * - The availability of output URB entries:
331 * - VS: As the input URB entries are overwritten with the
332 * VS-generated output data, output URB availability isn't a
335 if (vs_entry_size
< vec
->ve
->count
)
336 vs_entry_size
= vec
->ve
->count
;
338 gs_entry_size
= (vec
->gs
) ?
339 ilo_shader_get_kernel_param(vec
->gs
, ILO_KERNEL_OUTPUT_COUNT
) :
340 (gs_active
) ? vs_entry_size
: 0;
343 vs_entry_size
*= sizeof(float) * 4;
344 gs_entry_size
*= sizeof(float) * 4;
345 vs_total_size
= r
->dev
->urb_size
;
349 gs_total_size
= vs_total_size
;
355 gen6_3DSTATE_URB(r
->builder
, vs_total_size
, gs_total_size
,
356 vs_entry_size
, gs_entry_size
);
359 * From the Sandy Bridge PRM, volume 2 part 1, page 27:
361 * "Because of a urb corruption caused by allocating a previous
362 * gsunit's urb entry to vsunit software is required to send a
363 * "GS NULL Fence" (Send URB fence with VS URB size == 1 and GS URB
364 * size == 0) plus a dummy DRAW call before any case where VS will
365 * be taking over GS URB space."
367 if (r
->state
.gs
.active
&& !gs_active
)
368 ilo_render_emit_flush(r
);
370 r
->state
.gs
.active
= gs_active
;
375 gen6_draw_common_pointers_1(struct ilo_render
*r
,
376 const struct ilo_state_vector
*vec
,
377 struct ilo_render_draw_session
*session
)
379 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
380 if (session
->viewport_changed
) {
381 gen6_3DSTATE_VIEWPORT_STATE_POINTERS(r
->builder
,
382 r
->state
.CLIP_VIEWPORT
,
383 r
->state
.SF_VIEWPORT
,
384 r
->state
.CC_VIEWPORT
);
389 gen6_draw_common_pointers_2(struct ilo_render
*r
,
390 const struct ilo_state_vector
*vec
,
391 struct ilo_render_draw_session
*session
)
393 /* 3DSTATE_CC_STATE_POINTERS */
394 if (session
->blend_changed
||
395 session
->dsa_changed
||
396 session
->cc_changed
) {
397 gen6_3DSTATE_CC_STATE_POINTERS(r
->builder
,
398 r
->state
.BLEND_STATE
,
399 r
->state
.DEPTH_STENCIL_STATE
,
400 r
->state
.COLOR_CALC_STATE
);
403 /* 3DSTATE_SAMPLER_STATE_POINTERS */
404 if (session
->sampler_vs_changed
||
405 session
->sampler_gs_changed
||
406 session
->sampler_fs_changed
) {
407 gen6_3DSTATE_SAMPLER_STATE_POINTERS(r
->builder
,
408 r
->state
.vs
.SAMPLER_STATE
,
410 r
->state
.wm
.SAMPLER_STATE
);
415 gen6_draw_common_pointers_3(struct ilo_render
*r
,
416 const struct ilo_state_vector
*vec
,
417 struct ilo_render_draw_session
*session
)
419 /* 3DSTATE_SCISSOR_STATE_POINTERS */
420 if (session
->scissor_changed
) {
421 gen6_3DSTATE_SCISSOR_STATE_POINTERS(r
->builder
,
422 r
->state
.SCISSOR_RECT
);
425 /* 3DSTATE_BINDING_TABLE_POINTERS */
426 if (session
->binding_table_vs_changed
||
427 session
->binding_table_gs_changed
||
428 session
->binding_table_fs_changed
) {
429 gen6_3DSTATE_BINDING_TABLE_POINTERS(r
->builder
,
430 r
->state
.vs
.BINDING_TABLE_STATE
,
431 r
->state
.gs
.BINDING_TABLE_STATE
,
432 r
->state
.wm
.BINDING_TABLE_STATE
);
437 gen6_draw_vf(struct ilo_render
*r
,
438 const struct ilo_state_vector
*vec
,
439 struct ilo_render_draw_session
*session
)
441 if (ilo_dev_gen(r
->dev
) >= ILO_GEN(7.5)) {
442 /* 3DSTATE_INDEX_BUFFER */
443 if (DIRTY(IB
) || r
->batch_bo_changed
) {
444 gen6_3DSTATE_INDEX_BUFFER(r
->builder
,
449 if (session
->primitive_restart_changed
) {
450 gen7_3DSTATE_VF(r
->builder
, vec
->draw
->primitive_restart
,
451 vec
->draw
->restart_index
);
455 /* 3DSTATE_INDEX_BUFFER */
456 if (DIRTY(IB
) || session
->primitive_restart_changed
||
457 r
->batch_bo_changed
) {
458 gen6_3DSTATE_INDEX_BUFFER(r
->builder
,
459 &vec
->ib
, vec
->draw
->primitive_restart
);
463 /* 3DSTATE_VERTEX_BUFFERS */
464 if (DIRTY(VB
) || DIRTY(VE
) || r
->batch_bo_changed
)
465 gen6_3DSTATE_VERTEX_BUFFERS(r
->builder
, vec
->ve
, &vec
->vb
);
467 /* 3DSTATE_VERTEX_ELEMENTS */
468 if (DIRTY(VE
) || DIRTY(VS
)) {
469 const struct ilo_ve_state
*ve
= vec
->ve
;
470 bool last_velement_edgeflag
= false;
471 bool prepend_generate_ids
= false;
474 if (ilo_shader_get_kernel_param(vec
->vs
,
475 ILO_KERNEL_VS_INPUT_EDGEFLAG
)) {
476 /* we rely on the state tracker here */
477 assert(ilo_shader_get_kernel_param(vec
->vs
,
478 ILO_KERNEL_INPUT_COUNT
) == ve
->count
);
480 last_velement_edgeflag
= true;
483 if (ilo_shader_get_kernel_param(vec
->vs
,
484 ILO_KERNEL_VS_INPUT_INSTANCEID
) ||
485 ilo_shader_get_kernel_param(vec
->vs
,
486 ILO_KERNEL_VS_INPUT_VERTEXID
))
487 prepend_generate_ids
= true;
490 gen6_3DSTATE_VERTEX_ELEMENTS(r
->builder
, ve
,
491 last_velement_edgeflag
, prepend_generate_ids
);
496 gen6_draw_vf_statistics(struct ilo_render
*r
,
497 const struct ilo_state_vector
*vec
,
498 struct ilo_render_draw_session
*session
)
500 /* 3DSTATE_VF_STATISTICS */
501 if (r
->hw_ctx_changed
)
502 gen6_3DSTATE_VF_STATISTICS(r
->builder
, false);
506 gen6_draw_vf_draw(struct ilo_render
*r
,
507 const struct ilo_state_vector
*vec
,
508 struct ilo_render_draw_session
*session
)
511 gen6_3DPRIMITIVE(r
->builder
, vec
->draw
, &vec
->ib
);
513 r
->state
.current_pipe_control_dw1
= 0;
514 assert(!r
->state
.deferred_pipe_control_dw1
);
518 gen6_draw_vs(struct ilo_render
*r
,
519 const struct ilo_state_vector
*vec
,
520 struct ilo_render_draw_session
*session
)
522 const bool emit_3dstate_vs
= (DIRTY(VS
) || DIRTY(SAMPLER_VS
) ||
523 r
->instruction_bo_changed
);
524 const bool emit_3dstate_constant_vs
= session
->pcb_vs_changed
;
527 * the classic i965 does this in upload_vs_state(), citing a spec that I
530 if (emit_3dstate_vs
&& ilo_dev_gen(r
->dev
) == ILO_GEN(6))
531 gen6_wa_pre_non_pipelined(r
);
533 /* 3DSTATE_CONSTANT_VS */
534 if (emit_3dstate_constant_vs
) {
535 gen6_3DSTATE_CONSTANT_VS(r
->builder
,
536 &r
->state
.vs
.PUSH_CONSTANT_BUFFER
,
537 &r
->state
.vs
.PUSH_CONSTANT_BUFFER_size
,
542 if (emit_3dstate_vs
) {
543 const int num_samplers
= vec
->sampler
[PIPE_SHADER_VERTEX
].count
;
545 gen6_3DSTATE_VS(r
->builder
, vec
->vs
, num_samplers
);
548 if (emit_3dstate_constant_vs
&& ilo_dev_gen(r
->dev
) == ILO_GEN(6))
549 gen6_wa_post_3dstate_constant_vs(r
);
553 gen6_draw_gs(struct ilo_render
*r
,
554 const struct ilo_state_vector
*vec
,
555 struct ilo_render_draw_session
*session
)
557 /* 3DSTATE_CONSTANT_GS */
558 if (session
->pcb_gs_changed
)
559 gen6_3DSTATE_CONSTANT_GS(r
->builder
, NULL
, NULL
, 0);
562 if (DIRTY(GS
) || DIRTY(VS
) ||
563 session
->prim_changed
|| r
->instruction_bo_changed
) {
564 const int verts_per_prim
= u_vertices_per_prim(session
->reduced_prim
);
566 gen6_3DSTATE_GS(r
->builder
, vec
->gs
, vec
->vs
, verts_per_prim
);
571 gen6_draw_update_max_svbi(struct ilo_render
*r
,
572 const struct ilo_state_vector
*vec
,
573 struct ilo_render_draw_session
*session
)
575 if (DIRTY(VS
) || DIRTY(GS
) || DIRTY(SO
)) {
576 const struct pipe_stream_output_info
*so_info
=
577 (vec
->gs
) ? ilo_shader_get_kernel_so_info(vec
->gs
) :
578 (vec
->vs
) ? ilo_shader_get_kernel_so_info(vec
->vs
) : NULL
;
579 unsigned max_svbi
= 0xffffffff;
582 for (i
= 0; i
< so_info
->num_outputs
; i
++) {
583 const int output_buffer
= so_info
->output
[i
].output_buffer
;
584 const struct pipe_stream_output_target
*so
=
585 vec
->so
.states
[output_buffer
];
586 const int struct_size
= so_info
->stride
[output_buffer
] * 4;
587 const int elem_size
= so_info
->output
[i
].num_components
* 4;
595 buf_size
= so
->buffer_size
- so_info
->output
[i
].dst_offset
* 4;
597 count
= buf_size
/ struct_size
;
598 if (buf_size
% struct_size
>= elem_size
)
601 if (count
< max_svbi
)
605 if (r
->state
.so_max_vertices
!= max_svbi
) {
606 r
->state
.so_max_vertices
= max_svbi
;
615 gen6_draw_gs_svbi(struct ilo_render
*r
,
616 const struct ilo_state_vector
*vec
,
617 struct ilo_render_draw_session
*session
)
619 const bool emit
= gen6_draw_update_max_svbi(r
, vec
, session
);
621 /* 3DSTATE_GS_SVB_INDEX */
623 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
624 gen6_wa_pre_non_pipelined(r
);
626 gen6_3DSTATE_GS_SVB_INDEX(r
->builder
,
627 0, 0, r
->state
.so_max_vertices
,
630 if (r
->hw_ctx_changed
) {
634 * From the Sandy Bridge PRM, volume 2 part 1, page 148:
636 * "If a buffer is not enabled then the SVBI must be set to 0x0
637 * in order to not cause overflow in that SVBI."
639 * "If a buffer is not enabled then the MaxSVBI must be set to
640 * 0xFFFFFFFF in order to not cause overflow in that SVBI."
642 for (i
= 1; i
< 4; i
++) {
643 gen6_3DSTATE_GS_SVB_INDEX(r
->builder
,
644 i
, 0, 0xffffffff, false);
651 gen6_draw_clip(struct ilo_render
*r
,
652 const struct ilo_state_vector
*vec
,
653 struct ilo_render_draw_session
*session
)
656 if (DIRTY(RASTERIZER
) || DIRTY(FS
) || DIRTY(VIEWPORT
) || DIRTY(FB
)) {
657 bool enable_guardband
= true;
661 * We do not do 2D clipping yet. Guard band test should only be enabled
662 * when the viewport is larger than the framebuffer.
664 for (i
= 0; i
< vec
->viewport
.count
; i
++) {
665 const struct ilo_viewport_cso
*vp
= &vec
->viewport
.cso
[i
];
667 if (vp
->min_x
> 0.0f
|| vp
->max_x
< vec
->fb
.state
.width
||
668 vp
->min_y
> 0.0f
|| vp
->max_y
< vec
->fb
.state
.height
) {
669 enable_guardband
= false;
674 gen6_3DSTATE_CLIP(r
->builder
, vec
->rasterizer
,
675 vec
->fs
, enable_guardband
, 1);
680 gen6_draw_sf(struct ilo_render
*r
,
681 const struct ilo_state_vector
*vec
,
682 struct ilo_render_draw_session
*session
)
685 if (DIRTY(RASTERIZER
) || DIRTY(FS
))
686 gen6_3DSTATE_SF(r
->builder
, vec
->rasterizer
, vec
->fs
);
690 gen6_draw_sf_rect(struct ilo_render
*r
,
691 const struct ilo_state_vector
*vec
,
692 struct ilo_render_draw_session
*session
)
694 /* 3DSTATE_DRAWING_RECTANGLE */
696 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
697 gen6_wa_pre_non_pipelined(r
);
699 gen6_3DSTATE_DRAWING_RECTANGLE(r
->builder
, 0, 0,
700 vec
->fb
.state
.width
, vec
->fb
.state
.height
);
705 gen6_draw_wm(struct ilo_render
*r
,
706 const struct ilo_state_vector
*vec
,
707 struct ilo_render_draw_session
*session
)
709 /* 3DSTATE_CONSTANT_PS */
710 if (session
->pcb_fs_changed
) {
711 gen6_3DSTATE_CONSTANT_PS(r
->builder
,
712 &r
->state
.wm
.PUSH_CONSTANT_BUFFER
,
713 &r
->state
.wm
.PUSH_CONSTANT_BUFFER_size
,
718 if (DIRTY(FS
) || DIRTY(SAMPLER_FS
) || DIRTY(BLEND
) || DIRTY(DSA
) ||
719 DIRTY(RASTERIZER
) || r
->instruction_bo_changed
) {
720 const int num_samplers
= vec
->sampler
[PIPE_SHADER_FRAGMENT
].count
;
721 const bool dual_blend
= vec
->blend
->dual_blend
;
722 const bool cc_may_kill
= (vec
->dsa
->dw_alpha
||
723 vec
->blend
->alpha_to_coverage
);
725 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6) && r
->hw_ctx_changed
)
726 gen6_wa_pre_3dstate_wm_max_threads(r
);
728 gen6_3DSTATE_WM(r
->builder
, vec
->fs
, num_samplers
,
729 vec
->rasterizer
, dual_blend
, cc_may_kill
, 0);
734 gen6_draw_wm_multisample(struct ilo_render
*r
,
735 const struct ilo_state_vector
*vec
,
736 struct ilo_render_draw_session
*session
)
738 /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
739 if (DIRTY(SAMPLE_MASK
) || DIRTY(FB
)) {
740 const uint32_t *packed_sample_pos
;
742 packed_sample_pos
= (vec
->fb
.num_samples
> 1) ?
743 &r
->packed_sample_position_4x
: &r
->packed_sample_position_1x
;
745 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6)) {
746 gen6_wa_pre_non_pipelined(r
);
747 gen6_wa_pre_3dstate_multisample(r
);
750 gen6_3DSTATE_MULTISAMPLE(r
->builder
,
751 vec
->fb
.num_samples
, packed_sample_pos
,
752 vec
->rasterizer
->state
.half_pixel_center
);
754 gen6_3DSTATE_SAMPLE_MASK(r
->builder
,
755 (vec
->fb
.num_samples
> 1) ? vec
->sample_mask
: 0x1);
760 gen6_draw_wm_depth(struct ilo_render
*r
,
761 const struct ilo_state_vector
*vec
,
762 struct ilo_render_draw_session
*session
)
764 /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
765 if (DIRTY(FB
) || r
->batch_bo_changed
) {
766 const struct ilo_zs_surface
*zs
;
767 uint32_t clear_params
;
769 if (vec
->fb
.state
.zsbuf
) {
770 const struct ilo_surface_cso
*surface
=
771 (const struct ilo_surface_cso
*) vec
->fb
.state
.zsbuf
;
772 const struct ilo_texture_slice
*slice
=
773 ilo_texture_get_slice(ilo_texture(surface
->base
.texture
),
774 surface
->base
.u
.tex
.level
, surface
->base
.u
.tex
.first_layer
);
776 assert(!surface
->is_rt
);
779 clear_params
= slice
->clear_value
;
782 zs
= &vec
->fb
.null_zs
;
786 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6)) {
787 gen6_wa_pre_non_pipelined(r
);
788 gen6_wa_pre_depth(r
);
791 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
, zs
);
792 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
, zs
);
793 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
, zs
);
794 gen6_3DSTATE_CLEAR_PARAMS(r
->builder
, clear_params
);
799 gen6_draw_wm_raster(struct ilo_render
*r
,
800 const struct ilo_state_vector
*vec
,
801 struct ilo_render_draw_session
*session
)
803 /* 3DSTATE_POLY_STIPPLE_PATTERN and 3DSTATE_POLY_STIPPLE_OFFSET */
804 if ((DIRTY(RASTERIZER
) || DIRTY(POLY_STIPPLE
)) &&
805 vec
->rasterizer
->state
.poly_stipple_enable
) {
806 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
807 gen6_wa_pre_non_pipelined(r
);
809 gen6_3DSTATE_POLY_STIPPLE_PATTERN(r
->builder
,
812 gen6_3DSTATE_POLY_STIPPLE_OFFSET(r
->builder
, 0, 0);
815 /* 3DSTATE_LINE_STIPPLE */
816 if (DIRTY(RASTERIZER
) && vec
->rasterizer
->state
.line_stipple_enable
) {
817 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
818 gen6_wa_pre_non_pipelined(r
);
820 gen6_3DSTATE_LINE_STIPPLE(r
->builder
,
821 vec
->rasterizer
->state
.line_stipple_pattern
,
822 vec
->rasterizer
->state
.line_stipple_factor
+ 1);
825 /* 3DSTATE_AA_LINE_PARAMETERS */
826 if (DIRTY(RASTERIZER
) && vec
->rasterizer
->state
.line_smooth
) {
827 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
828 gen6_wa_pre_non_pipelined(r
);
830 gen6_3DSTATE_AA_LINE_PARAMETERS(r
->builder
);
837 ilo_render_emit_draw_commands_gen6(struct ilo_render
*render
,
838 const struct ilo_state_vector
*vec
,
839 struct ilo_render_draw_session
*session
)
841 ILO_DEV_ASSERT(render
->dev
, 6, 6);
844 * We try to keep the order of the commands match, as closely as possible,
845 * that of the classic i965 driver. It allows us to compare the command
848 gen6_draw_common_select(render
, vec
, session
);
849 gen6_draw_gs_svbi(render
, vec
, session
);
850 gen6_draw_common_sip(render
, vec
, session
);
851 gen6_draw_vf_statistics(render
, vec
, session
);
852 gen6_draw_common_base_address(render
, vec
, session
);
853 gen6_draw_common_pointers_1(render
, vec
, session
);
854 gen6_draw_common_urb(render
, vec
, session
);
855 gen6_draw_common_pointers_2(render
, vec
, session
);
856 gen6_draw_wm_multisample(render
, vec
, session
);
857 gen6_draw_vs(render
, vec
, session
);
858 gen6_draw_gs(render
, vec
, session
);
859 gen6_draw_clip(render
, vec
, session
);
860 gen6_draw_sf(render
, vec
, session
);
861 gen6_draw_wm(render
, vec
, session
);
862 gen6_draw_common_pointers_3(render
, vec
, session
);
863 gen6_draw_wm_depth(render
, vec
, session
);
864 gen6_draw_wm_raster(render
, vec
, session
);
865 gen6_draw_sf_rect(render
, vec
, session
);
866 gen6_draw_vf(render
, vec
, session
);
867 gen6_draw_vf_draw(render
, vec
, session
);
871 gen6_rectlist_vs_to_sf(struct ilo_render
*r
,
872 const struct ilo_blitter
*blitter
)
874 gen6_3DSTATE_CONSTANT_VS(r
->builder
, NULL
, NULL
, 0);
875 gen6_3DSTATE_VS(r
->builder
, NULL
, 0);
877 gen6_wa_post_3dstate_constant_vs(r
);
879 gen6_3DSTATE_CONSTANT_GS(r
->builder
, NULL
, NULL
, 0);
880 gen6_3DSTATE_GS(r
->builder
, NULL
, NULL
, 0);
882 gen6_3DSTATE_CLIP(r
->builder
, NULL
, NULL
, false, 0);
883 gen6_3DSTATE_SF(r
->builder
, NULL
, NULL
);
887 gen6_rectlist_wm(struct ilo_render
*r
,
888 const struct ilo_blitter
*blitter
)
892 switch (blitter
->op
) {
893 case ILO_BLITTER_RECTLIST_CLEAR_ZS
:
894 hiz_op
= GEN6_WM_DW4_DEPTH_CLEAR
;
896 case ILO_BLITTER_RECTLIST_RESOLVE_Z
:
897 hiz_op
= GEN6_WM_DW4_DEPTH_RESOLVE
;
899 case ILO_BLITTER_RECTLIST_RESOLVE_HIZ
:
900 hiz_op
= GEN6_WM_DW4_HIZ_RESOLVE
;
907 gen6_3DSTATE_CONSTANT_PS(r
->builder
, NULL
, NULL
, 0);
909 gen6_wa_pre_3dstate_wm_max_threads(r
);
910 gen6_3DSTATE_WM(r
->builder
, NULL
, 0, NULL
, false, false, hiz_op
);
914 gen6_rectlist_wm_depth(struct ilo_render
*r
,
915 const struct ilo_blitter
*blitter
)
917 gen6_wa_pre_depth(r
);
919 if (blitter
->uses
& (ILO_BLITTER_USE_FB_DEPTH
|
920 ILO_BLITTER_USE_FB_STENCIL
)) {
921 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
,
922 &blitter
->fb
.dst
.u
.zs
);
925 if (blitter
->uses
& ILO_BLITTER_USE_FB_DEPTH
) {
926 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
,
927 &blitter
->fb
.dst
.u
.zs
);
930 if (blitter
->uses
& ILO_BLITTER_USE_FB_STENCIL
) {
931 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
,
932 &blitter
->fb
.dst
.u
.zs
);
935 gen6_3DSTATE_CLEAR_PARAMS(r
->builder
,
936 blitter
->depth_clear_value
);
940 gen6_rectlist_wm_multisample(struct ilo_render
*r
,
941 const struct ilo_blitter
*blitter
)
943 const uint32_t *packed_sample_pos
= (blitter
->fb
.num_samples
> 1) ?
944 &r
->packed_sample_position_4x
: &r
->packed_sample_position_1x
;
946 gen6_wa_pre_3dstate_multisample(r
);
948 gen6_3DSTATE_MULTISAMPLE(r
->builder
, blitter
->fb
.num_samples
,
949 packed_sample_pos
, true);
951 gen6_3DSTATE_SAMPLE_MASK(r
->builder
,
952 (1 << blitter
->fb
.num_samples
) - 1);
956 ilo_render_get_rectlist_commands_len_gen6(const struct ilo_render
*render
,
957 const struct ilo_blitter
*blitter
)
959 ILO_DEV_ASSERT(render
->dev
, 6, 7.5);
965 ilo_render_emit_rectlist_commands_gen6(struct ilo_render
*r
,
966 const struct ilo_blitter
*blitter
)
968 ILO_DEV_ASSERT(r
->dev
, 6, 6);
970 gen6_wa_pre_non_pipelined(r
);
972 gen6_rectlist_wm_multisample(r
, blitter
);
974 gen6_state_base_address(r
->builder
, true);
976 gen6_3DSTATE_VERTEX_BUFFERS(r
->builder
,
977 &blitter
->ve
, &blitter
->vb
);
979 gen6_3DSTATE_VERTEX_ELEMENTS(r
->builder
,
980 &blitter
->ve
, false, false);
982 gen6_3DSTATE_URB(r
->builder
,
983 r
->dev
->urb_size
, 0, blitter
->ve
.count
* 4 * sizeof(float), 0);
984 /* 3DSTATE_URB workaround */
985 if (r
->state
.gs
.active
) {
986 ilo_render_emit_flush(r
);
987 r
->state
.gs
.active
= false;
991 (ILO_BLITTER_USE_DSA
| ILO_BLITTER_USE_CC
)) {
992 gen6_3DSTATE_CC_STATE_POINTERS(r
->builder
, 0,
993 r
->state
.DEPTH_STENCIL_STATE
, r
->state
.COLOR_CALC_STATE
);
996 gen6_rectlist_vs_to_sf(r
, blitter
);
997 gen6_rectlist_wm(r
, blitter
);
999 if (blitter
->uses
& ILO_BLITTER_USE_VIEWPORT
) {
1000 gen6_3DSTATE_VIEWPORT_STATE_POINTERS(r
->builder
,
1001 0, 0, r
->state
.CC_VIEWPORT
);
1004 gen6_rectlist_wm_depth(r
, blitter
);
1006 gen6_3DSTATE_DRAWING_RECTANGLE(r
->builder
, 0, 0,
1007 blitter
->fb
.width
, blitter
->fb
.height
);
1009 gen6_3DPRIMITIVE(r
->builder
, &blitter
->draw
, NULL
);
1013 ilo_render_get_draw_commands_len_gen6(const struct ilo_render
*render
,
1014 const struct ilo_state_vector
*vec
)
1018 ILO_DEV_ASSERT(render
->dev
, 6, 6);
1021 len
+= GEN6_3DSTATE_CONSTANT_ANY__SIZE
* 3;
1022 len
+= GEN6_3DSTATE_GS_SVB_INDEX__SIZE
* 4;
1023 len
+= GEN6_PIPE_CONTROL__SIZE
* 5;
1026 GEN6_STATE_BASE_ADDRESS__SIZE
+
1027 GEN6_STATE_SIP__SIZE
+
1028 GEN6_3DSTATE_VF_STATISTICS__SIZE
+
1029 GEN6_PIPELINE_SELECT__SIZE
+
1030 GEN6_3DSTATE_BINDING_TABLE_POINTERS__SIZE
+
1031 GEN6_3DSTATE_SAMPLER_STATE_POINTERS__SIZE
+
1032 GEN6_3DSTATE_URB__SIZE
+
1033 GEN6_3DSTATE_VERTEX_BUFFERS__SIZE
+
1034 GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE
+
1035 GEN6_3DSTATE_INDEX_BUFFER__SIZE
+
1036 GEN6_3DSTATE_VIEWPORT_STATE_POINTERS__SIZE
+
1037 GEN6_3DSTATE_CC_STATE_POINTERS__SIZE
+
1038 GEN6_3DSTATE_SCISSOR_STATE_POINTERS__SIZE
+
1039 GEN6_3DSTATE_VS__SIZE
+
1040 GEN6_3DSTATE_GS__SIZE
+
1041 GEN6_3DSTATE_CLIP__SIZE
+
1042 GEN6_3DSTATE_SF__SIZE
+
1043 GEN6_3DSTATE_WM__SIZE
+
1044 GEN6_3DSTATE_SAMPLE_MASK__SIZE
+
1045 GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE
+
1046 GEN6_3DSTATE_DEPTH_BUFFER__SIZE
+
1047 GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE
+
1048 GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE
+
1049 GEN6_3DSTATE_LINE_STIPPLE__SIZE
+
1050 GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE
+
1051 GEN6_3DSTATE_MULTISAMPLE__SIZE
+
1052 GEN6_3DSTATE_STENCIL_BUFFER__SIZE
+
1053 GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE
+
1054 GEN6_3DSTATE_CLEAR_PARAMS__SIZE
+
1055 GEN6_3DPRIMITIVE__SIZE
;