2 * Mesa 3-D graphics library
4 * Copyright (C) 2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "genhw/genhw.h"
29 #include "util/u_dual_blend.h"
30 #include "util/u_prim.h"
32 #include "ilo_blitter.h"
33 #include "ilo_builder_3d.h"
34 #include "ilo_builder_mi.h"
35 #include "ilo_builder_render.h"
36 #include "ilo_query.h"
37 #include "ilo_shader.h"
38 #include "ilo_state.h"
39 #include "ilo_render.h"
40 #include "ilo_render_gen.h"
43 * A wrapper for gen6_PIPE_CONTROL().
46 gen6_pipe_control(struct ilo_render
*r
, uint32_t dw1
)
48 struct intel_bo
*bo
= (dw1
& GEN6_PIPE_CONTROL_WRITE__MASK
) ?
49 r
->workaround_bo
: NULL
;
51 ILO_DEV_ASSERT(r
->dev
, 6, 6);
53 gen6_PIPE_CONTROL(r
->builder
, dw1
, bo
, 0, false);
55 r
->state
.current_pipe_control_dw1
|= dw1
;
57 assert(!r
->state
.deferred_pipe_control_dw1
);
61 * This should be called before PIPE_CONTROL.
64 gen6_wa_pre_pipe_control(struct ilo_render
*r
, uint32_t dw1
)
67 * From the Sandy Bridge PRM, volume 2 part 1, page 60:
69 * "Pipe-control with CS-stall bit set must be sent BEFORE the
70 * pipe-control with a post-sync op and no write-cache flushes."
72 * This WA may also be triggered indirectly by the other two WAs on the
75 * "Before any depth stall flush (including those produced by
76 * non-pipelined state commands), software needs to first send a
77 * PIPE_CONTROL with no bits set except Post-Sync Operation != 0."
79 * "Before a PIPE_CONTROL with Write Cache Flush Enable =1, a
80 * PIPE_CONTROL with any non-zero post-sync-op is required."
82 const bool direct_wa_cond
= (dw1
& GEN6_PIPE_CONTROL_WRITE__MASK
) &&
83 !(dw1
& GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH
);
84 const bool indirect_wa_cond
= (dw1
& GEN6_PIPE_CONTROL_DEPTH_STALL
) |
85 (dw1
& GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH
);
87 ILO_DEV_ASSERT(r
->dev
, 6, 6);
89 if (!direct_wa_cond
&& !indirect_wa_cond
)
92 if (!(r
->state
.current_pipe_control_dw1
& GEN6_PIPE_CONTROL_CS_STALL
)) {
94 * From the Sandy Bridge PRM, volume 2 part 1, page 73:
96 * "1 of the following must also be set (when CS stall is set):
98 * - Depth Cache Flush Enable ([0] of DW1)
99 * - Stall at Pixel Scoreboard ([1] of DW1)
100 * - Depth Stall ([13] of DW1)
101 * - Post-Sync Operation ([13] of DW1)
102 * - Render Target Cache Flush Enable ([12] of DW1)
103 * - Notify Enable ([8] of DW1)"
105 * Because of the WAs above, we have to pick Stall at Pixel Scoreboard.
107 const uint32_t direct_wa
= GEN6_PIPE_CONTROL_CS_STALL
|
108 GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL
;
110 gen6_pipe_control(r
, direct_wa
);
113 if (indirect_wa_cond
&&
114 !(r
->state
.current_pipe_control_dw1
& GEN6_PIPE_CONTROL_WRITE__MASK
)) {
115 const uint32_t indirect_wa
= GEN6_PIPE_CONTROL_WRITE_IMM
;
117 gen6_pipe_control(r
, indirect_wa
);
122 * This should be called before any non-pipelined state command.
125 gen6_wa_pre_non_pipelined(struct ilo_render
*r
)
127 ILO_DEV_ASSERT(r
->dev
, 6, 6);
129 /* non-pipelined state commands produce depth stall */
130 gen6_wa_pre_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
134 gen6_wa_post_3dstate_constant_vs(struct ilo_render
*r
)
137 * According to upload_vs_state() of the classic driver, we need to emit a
138 * PIPE_CONTROL after 3DSTATE_CONSTANT_VS, otherwise the command is kept
139 * being buffered by VS FF, to the point that the FF dies.
141 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_STALL
|
142 GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
|
143 GEN6_PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
145 gen6_wa_pre_pipe_control(r
, dw1
);
147 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
148 gen6_pipe_control(r
, dw1
);
152 gen6_wa_pre_3dstate_wm_max_threads(struct ilo_render
*r
)
155 * From the Sandy Bridge PRM, volume 2 part 1, page 274:
157 * "A PIPE_CONTROL command, with only the Stall At Pixel Scoreboard
158 * field set (DW1 Bit 1), must be issued prior to any change to the
159 * value in this field (Maximum Number of Threads in 3DSTATE_WM)"
161 const uint32_t dw1
= GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL
;
163 ILO_DEV_ASSERT(r
->dev
, 6, 6);
165 gen6_wa_pre_pipe_control(r
, dw1
);
167 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
168 gen6_pipe_control(r
, dw1
);
172 gen6_wa_pre_3dstate_multisample(struct ilo_render
*r
)
175 * From the Sandy Bridge PRM, volume 2 part 1, page 305:
177 * "Driver must guarentee that all the caches in the depth pipe are
178 * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
179 * requires driver to send a PIPE_CONTROL with a CS stall along with a
180 * Depth Flush prior to this command."
182 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
183 GEN6_PIPE_CONTROL_CS_STALL
;
185 ILO_DEV_ASSERT(r
->dev
, 6, 6);
187 gen6_wa_pre_pipe_control(r
, dw1
);
189 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
190 gen6_pipe_control(r
, dw1
);
194 gen6_wa_pre_depth(struct ilo_render
*r
)
196 ILO_DEV_ASSERT(r
->dev
, 6, 6);
199 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
201 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
202 * any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
203 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
204 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
205 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
206 * Depth Flush Bit set, followed by another pipelined depth stall
207 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
208 * guarantee that the pipeline from WM onwards is already flushed
209 * (e.g., via a preceding MI_FLUSH)."
211 * According to the classic driver, it also applies for GEN6.
213 gen6_wa_pre_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
|
214 GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
216 gen6_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
217 gen6_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
218 gen6_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
221 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
224 gen6_draw_common_select(struct ilo_render
*r
,
225 const struct ilo_state_vector
*vec
,
226 struct gen6_draw_session
*session
)
228 /* PIPELINE_SELECT */
229 if (r
->hw_ctx_changed
) {
230 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
231 gen6_wa_pre_non_pipelined(r
);
233 gen6_PIPELINE_SELECT(r
->builder
, 0x0);
238 gen6_draw_common_sip(struct ilo_render
*r
,
239 const struct ilo_state_vector
*vec
,
240 struct gen6_draw_session
*session
)
243 if (r
->hw_ctx_changed
) {
244 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
245 gen6_wa_pre_non_pipelined(r
);
247 gen6_STATE_SIP(r
->builder
, 0);
252 gen6_draw_common_base_address(struct ilo_render
*r
,
253 const struct ilo_state_vector
*vec
,
254 struct gen6_draw_session
*session
)
256 /* STATE_BASE_ADDRESS */
257 if (r
->state_bo_changed
|| r
->instruction_bo_changed
||
258 r
->batch_bo_changed
) {
259 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
260 gen6_wa_pre_non_pipelined(r
);
262 gen6_state_base_address(r
->builder
, r
->hw_ctx_changed
);
265 * From the Sandy Bridge PRM, volume 1 part 1, page 28:
267 * "The following commands must be reissued following any change to
268 * the base addresses:
270 * * 3DSTATE_BINDING_TABLE_POINTERS
271 * * 3DSTATE_SAMPLER_STATE_POINTERS
272 * * 3DSTATE_VIEWPORT_STATE_POINTERS
273 * * 3DSTATE_CC_POINTERS
274 * * MEDIA_STATE_POINTERS"
276 * 3DSTATE_SCISSOR_STATE_POINTERS is not on the list, but it is
277 * reasonable to also reissue the command. Same to PCB.
279 session
->viewport_changed
= true;
281 session
->scissor_changed
= true;
283 session
->blend_changed
= true;
284 session
->dsa_changed
= true;
285 session
->cc_changed
= true;
287 session
->sampler_vs_changed
= true;
288 session
->sampler_gs_changed
= true;
289 session
->sampler_fs_changed
= true;
291 session
->pcb_vs_changed
= true;
292 session
->pcb_gs_changed
= true;
293 session
->pcb_fs_changed
= true;
295 session
->binding_table_vs_changed
= true;
296 session
->binding_table_gs_changed
= true;
297 session
->binding_table_fs_changed
= true;
302 gen6_draw_common_urb(struct ilo_render
*r
,
303 const struct ilo_state_vector
*vec
,
304 struct gen6_draw_session
*session
)
307 if (DIRTY(VE
) || DIRTY(VS
) || DIRTY(GS
)) {
308 const bool gs_active
= (vec
->gs
|| (vec
->vs
&&
309 ilo_shader_get_kernel_param(vec
->vs
, ILO_KERNEL_VS_GEN6_SO
)));
310 int vs_entry_size
, gs_entry_size
;
311 int vs_total_size
, gs_total_size
;
313 vs_entry_size
= (vec
->vs
) ?
314 ilo_shader_get_kernel_param(vec
->vs
, ILO_KERNEL_OUTPUT_COUNT
) : 0;
317 * As indicated by 2e712e41db0c0676e9f30fc73172c0e8de8d84d4, VF and VS
318 * share VUE handles. The VUE allocation size must be large enough to
319 * store either VF outputs (number of VERTEX_ELEMENTs) and VS outputs.
321 * I am not sure if the PRM explicitly states that VF and VS share VUE
322 * handles. But here is a citation that implies so:
324 * From the Sandy Bridge PRM, volume 2 part 1, page 44:
326 * "Once a FF stage that spawn threads has sufficient input to
327 * initiate a thread, it must guarantee that it is safe to request
328 * the thread initiation. For all these FF stages, this check is
331 * - The availability of output URB entries:
332 * - VS: As the input URB entries are overwritten with the
333 * VS-generated output data, output URB availability isn't a
336 if (vs_entry_size
< vec
->ve
->count
)
337 vs_entry_size
= vec
->ve
->count
;
339 gs_entry_size
= (vec
->gs
) ?
340 ilo_shader_get_kernel_param(vec
->gs
, ILO_KERNEL_OUTPUT_COUNT
) :
341 (gs_active
) ? vs_entry_size
: 0;
344 vs_entry_size
*= sizeof(float) * 4;
345 gs_entry_size
*= sizeof(float) * 4;
346 vs_total_size
= r
->dev
->urb_size
;
350 gs_total_size
= vs_total_size
;
356 gen6_3DSTATE_URB(r
->builder
, vs_total_size
, gs_total_size
,
357 vs_entry_size
, gs_entry_size
);
360 * From the Sandy Bridge PRM, volume 2 part 1, page 27:
362 * "Because of a urb corruption caused by allocating a previous
363 * gsunit's urb entry to vsunit software is required to send a
364 * "GS NULL Fence" (Send URB fence with VS URB size == 1 and GS URB
365 * size == 0) plus a dummy DRAW call before any case where VS will
366 * be taking over GS URB space."
368 if (r
->state
.gs
.active
&& !gs_active
)
369 ilo_render_emit_flush(r
);
371 r
->state
.gs
.active
= gs_active
;
376 gen6_draw_common_pointers_1(struct ilo_render
*r
,
377 const struct ilo_state_vector
*vec
,
378 struct gen6_draw_session
*session
)
380 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
381 if (session
->viewport_changed
) {
382 gen6_3DSTATE_VIEWPORT_STATE_POINTERS(r
->builder
,
383 r
->state
.CLIP_VIEWPORT
,
384 r
->state
.SF_VIEWPORT
,
385 r
->state
.CC_VIEWPORT
);
390 gen6_draw_common_pointers_2(struct ilo_render
*r
,
391 const struct ilo_state_vector
*vec
,
392 struct gen6_draw_session
*session
)
394 /* 3DSTATE_CC_STATE_POINTERS */
395 if (session
->blend_changed
||
396 session
->dsa_changed
||
397 session
->cc_changed
) {
398 gen6_3DSTATE_CC_STATE_POINTERS(r
->builder
,
399 r
->state
.BLEND_STATE
,
400 r
->state
.DEPTH_STENCIL_STATE
,
401 r
->state
.COLOR_CALC_STATE
);
404 /* 3DSTATE_SAMPLER_STATE_POINTERS */
405 if (session
->sampler_vs_changed
||
406 session
->sampler_gs_changed
||
407 session
->sampler_fs_changed
) {
408 gen6_3DSTATE_SAMPLER_STATE_POINTERS(r
->builder
,
409 r
->state
.vs
.SAMPLER_STATE
,
411 r
->state
.wm
.SAMPLER_STATE
);
416 gen6_draw_common_pointers_3(struct ilo_render
*r
,
417 const struct ilo_state_vector
*vec
,
418 struct gen6_draw_session
*session
)
420 /* 3DSTATE_SCISSOR_STATE_POINTERS */
421 if (session
->scissor_changed
) {
422 gen6_3DSTATE_SCISSOR_STATE_POINTERS(r
->builder
,
423 r
->state
.SCISSOR_RECT
);
426 /* 3DSTATE_BINDING_TABLE_POINTERS */
427 if (session
->binding_table_vs_changed
||
428 session
->binding_table_gs_changed
||
429 session
->binding_table_fs_changed
) {
430 gen6_3DSTATE_BINDING_TABLE_POINTERS(r
->builder
,
431 r
->state
.vs
.BINDING_TABLE_STATE
,
432 r
->state
.gs
.BINDING_TABLE_STATE
,
433 r
->state
.wm
.BINDING_TABLE_STATE
);
438 gen6_draw_vf(struct ilo_render
*r
,
439 const struct ilo_state_vector
*vec
,
440 struct gen6_draw_session
*session
)
442 if (ilo_dev_gen(r
->dev
) >= ILO_GEN(7.5)) {
443 /* 3DSTATE_INDEX_BUFFER */
444 if (DIRTY(IB
) || r
->batch_bo_changed
) {
445 gen6_3DSTATE_INDEX_BUFFER(r
->builder
,
450 if (session
->primitive_restart_changed
) {
451 gen7_3DSTATE_VF(r
->builder
, vec
->draw
->primitive_restart
,
452 vec
->draw
->restart_index
);
456 /* 3DSTATE_INDEX_BUFFER */
457 if (DIRTY(IB
) || session
->primitive_restart_changed
||
458 r
->batch_bo_changed
) {
459 gen6_3DSTATE_INDEX_BUFFER(r
->builder
,
460 &vec
->ib
, vec
->draw
->primitive_restart
);
464 /* 3DSTATE_VERTEX_BUFFERS */
465 if (DIRTY(VB
) || DIRTY(VE
) || r
->batch_bo_changed
)
466 gen6_3DSTATE_VERTEX_BUFFERS(r
->builder
, vec
->ve
, &vec
->vb
);
468 /* 3DSTATE_VERTEX_ELEMENTS */
469 if (DIRTY(VE
) || DIRTY(VS
)) {
470 const struct ilo_ve_state
*ve
= vec
->ve
;
471 bool last_velement_edgeflag
= false;
472 bool prepend_generate_ids
= false;
475 if (ilo_shader_get_kernel_param(vec
->vs
,
476 ILO_KERNEL_VS_INPUT_EDGEFLAG
)) {
477 /* we rely on the state tracker here */
478 assert(ilo_shader_get_kernel_param(vec
->vs
,
479 ILO_KERNEL_INPUT_COUNT
) == ve
->count
);
481 last_velement_edgeflag
= true;
484 if (ilo_shader_get_kernel_param(vec
->vs
,
485 ILO_KERNEL_VS_INPUT_INSTANCEID
) ||
486 ilo_shader_get_kernel_param(vec
->vs
,
487 ILO_KERNEL_VS_INPUT_VERTEXID
))
488 prepend_generate_ids
= true;
491 gen6_3DSTATE_VERTEX_ELEMENTS(r
->builder
, ve
,
492 last_velement_edgeflag
, prepend_generate_ids
);
497 gen6_draw_vf_statistics(struct ilo_render
*r
,
498 const struct ilo_state_vector
*vec
,
499 struct gen6_draw_session
*session
)
501 /* 3DSTATE_VF_STATISTICS */
502 if (r
->hw_ctx_changed
)
503 gen6_3DSTATE_VF_STATISTICS(r
->builder
, false);
507 gen6_draw_vf_draw(struct ilo_render
*r
,
508 const struct ilo_state_vector
*vec
,
509 struct gen6_draw_session
*session
)
512 gen6_3DPRIMITIVE(r
->builder
, vec
->draw
, &vec
->ib
);
514 r
->state
.current_pipe_control_dw1
= 0;
515 assert(!r
->state
.deferred_pipe_control_dw1
);
519 gen6_draw_vs(struct ilo_render
*r
,
520 const struct ilo_state_vector
*vec
,
521 struct gen6_draw_session
*session
)
523 const bool emit_3dstate_vs
= (DIRTY(VS
) || DIRTY(SAMPLER_VS
) ||
524 r
->instruction_bo_changed
);
525 const bool emit_3dstate_constant_vs
= session
->pcb_vs_changed
;
528 * the classic i965 does this in upload_vs_state(), citing a spec that I
531 if (emit_3dstate_vs
&& ilo_dev_gen(r
->dev
) == ILO_GEN(6))
532 gen6_wa_pre_non_pipelined(r
);
534 /* 3DSTATE_CONSTANT_VS */
535 if (emit_3dstate_constant_vs
) {
536 gen6_3DSTATE_CONSTANT_VS(r
->builder
,
537 &r
->state
.vs
.PUSH_CONSTANT_BUFFER
,
538 &r
->state
.vs
.PUSH_CONSTANT_BUFFER_size
,
543 if (emit_3dstate_vs
) {
544 const int num_samplers
= vec
->sampler
[PIPE_SHADER_VERTEX
].count
;
546 gen6_3DSTATE_VS(r
->builder
, vec
->vs
, num_samplers
);
549 if (emit_3dstate_constant_vs
&& ilo_dev_gen(r
->dev
) == ILO_GEN(6))
550 gen6_wa_post_3dstate_constant_vs(r
);
554 gen6_draw_gs(struct ilo_render
*r
,
555 const struct ilo_state_vector
*vec
,
556 struct gen6_draw_session
*session
)
558 /* 3DSTATE_CONSTANT_GS */
559 if (session
->pcb_gs_changed
)
560 gen6_3DSTATE_CONSTANT_GS(r
->builder
, NULL
, NULL
, 0);
563 if (DIRTY(GS
) || DIRTY(VS
) ||
564 session
->prim_changed
|| r
->instruction_bo_changed
) {
565 const int verts_per_prim
= u_vertices_per_prim(session
->reduced_prim
);
567 gen6_3DSTATE_GS(r
->builder
, vec
->gs
, vec
->vs
, verts_per_prim
);
572 gen6_draw_update_max_svbi(struct ilo_render
*r
,
573 const struct ilo_state_vector
*vec
,
574 struct gen6_draw_session
*session
)
576 if (DIRTY(VS
) || DIRTY(GS
) || DIRTY(SO
)) {
577 const struct pipe_stream_output_info
*so_info
=
578 (vec
->gs
) ? ilo_shader_get_kernel_so_info(vec
->gs
) :
579 (vec
->vs
) ? ilo_shader_get_kernel_so_info(vec
->vs
) : NULL
;
580 unsigned max_svbi
= 0xffffffff;
583 for (i
= 0; i
< so_info
->num_outputs
; i
++) {
584 const int output_buffer
= so_info
->output
[i
].output_buffer
;
585 const struct pipe_stream_output_target
*so
=
586 vec
->so
.states
[output_buffer
];
587 const int struct_size
= so_info
->stride
[output_buffer
] * 4;
588 const int elem_size
= so_info
->output
[i
].num_components
* 4;
596 buf_size
= so
->buffer_size
- so_info
->output
[i
].dst_offset
* 4;
598 count
= buf_size
/ struct_size
;
599 if (buf_size
% struct_size
>= elem_size
)
602 if (count
< max_svbi
)
606 if (r
->state
.so_max_vertices
!= max_svbi
) {
607 r
->state
.so_max_vertices
= max_svbi
;
616 gen6_draw_gs_svbi(struct ilo_render
*r
,
617 const struct ilo_state_vector
*vec
,
618 struct gen6_draw_session
*session
)
620 const bool emit
= gen6_draw_update_max_svbi(r
, vec
, session
);
622 /* 3DSTATE_GS_SVB_INDEX */
624 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
625 gen6_wa_pre_non_pipelined(r
);
627 gen6_3DSTATE_GS_SVB_INDEX(r
->builder
,
628 0, 0, r
->state
.so_max_vertices
,
631 if (r
->hw_ctx_changed
) {
635 * From the Sandy Bridge PRM, volume 2 part 1, page 148:
637 * "If a buffer is not enabled then the SVBI must be set to 0x0
638 * in order to not cause overflow in that SVBI."
640 * "If a buffer is not enabled then the MaxSVBI must be set to
641 * 0xFFFFFFFF in order to not cause overflow in that SVBI."
643 for (i
= 1; i
< 4; i
++) {
644 gen6_3DSTATE_GS_SVB_INDEX(r
->builder
,
645 i
, 0, 0xffffffff, false);
652 gen6_draw_clip(struct ilo_render
*r
,
653 const struct ilo_state_vector
*vec
,
654 struct gen6_draw_session
*session
)
657 if (DIRTY(RASTERIZER
) || DIRTY(FS
) || DIRTY(VIEWPORT
) || DIRTY(FB
)) {
658 bool enable_guardband
= true;
662 * We do not do 2D clipping yet. Guard band test should only be enabled
663 * when the viewport is larger than the framebuffer.
665 for (i
= 0; i
< vec
->viewport
.count
; i
++) {
666 const struct ilo_viewport_cso
*vp
= &vec
->viewport
.cso
[i
];
668 if (vp
->min_x
> 0.0f
|| vp
->max_x
< vec
->fb
.state
.width
||
669 vp
->min_y
> 0.0f
|| vp
->max_y
< vec
->fb
.state
.height
) {
670 enable_guardband
= false;
675 gen6_3DSTATE_CLIP(r
->builder
, vec
->rasterizer
,
676 vec
->fs
, enable_guardband
, 1);
681 gen6_draw_sf(struct ilo_render
*r
,
682 const struct ilo_state_vector
*vec
,
683 struct gen6_draw_session
*session
)
686 if (DIRTY(RASTERIZER
) || DIRTY(FS
))
687 gen6_3DSTATE_SF(r
->builder
, vec
->rasterizer
, vec
->fs
);
691 gen6_draw_sf_rect(struct ilo_render
*r
,
692 const struct ilo_state_vector
*vec
,
693 struct gen6_draw_session
*session
)
695 /* 3DSTATE_DRAWING_RECTANGLE */
697 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
698 gen6_wa_pre_non_pipelined(r
);
700 gen6_3DSTATE_DRAWING_RECTANGLE(r
->builder
, 0, 0,
701 vec
->fb
.state
.width
, vec
->fb
.state
.height
);
706 gen6_draw_wm(struct ilo_render
*r
,
707 const struct ilo_state_vector
*vec
,
708 struct gen6_draw_session
*session
)
710 /* 3DSTATE_CONSTANT_PS */
711 if (session
->pcb_fs_changed
) {
712 gen6_3DSTATE_CONSTANT_PS(r
->builder
,
713 &r
->state
.wm
.PUSH_CONSTANT_BUFFER
,
714 &r
->state
.wm
.PUSH_CONSTANT_BUFFER_size
,
719 if (DIRTY(FS
) || DIRTY(SAMPLER_FS
) || DIRTY(BLEND
) || DIRTY(DSA
) ||
720 DIRTY(RASTERIZER
) || r
->instruction_bo_changed
) {
721 const int num_samplers
= vec
->sampler
[PIPE_SHADER_FRAGMENT
].count
;
722 const bool dual_blend
= vec
->blend
->dual_blend
;
723 const bool cc_may_kill
= (vec
->dsa
->dw_alpha
||
724 vec
->blend
->alpha_to_coverage
);
726 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6) && r
->hw_ctx_changed
)
727 gen6_wa_pre_3dstate_wm_max_threads(r
);
729 gen6_3DSTATE_WM(r
->builder
, vec
->fs
, num_samplers
,
730 vec
->rasterizer
, dual_blend
, cc_may_kill
, 0);
735 gen6_draw_wm_multisample(struct ilo_render
*r
,
736 const struct ilo_state_vector
*vec
,
737 struct gen6_draw_session
*session
)
739 /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
740 if (DIRTY(SAMPLE_MASK
) || DIRTY(FB
)) {
741 const uint32_t *packed_sample_pos
;
743 packed_sample_pos
= (vec
->fb
.num_samples
> 1) ?
744 &r
->packed_sample_position_4x
: &r
->packed_sample_position_1x
;
746 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6)) {
747 gen6_wa_pre_non_pipelined(r
);
748 gen6_wa_pre_3dstate_multisample(r
);
751 gen6_3DSTATE_MULTISAMPLE(r
->builder
,
752 vec
->fb
.num_samples
, packed_sample_pos
,
753 vec
->rasterizer
->state
.half_pixel_center
);
755 gen6_3DSTATE_SAMPLE_MASK(r
->builder
,
756 (vec
->fb
.num_samples
> 1) ? vec
->sample_mask
: 0x1);
761 gen6_draw_wm_depth(struct ilo_render
*r
,
762 const struct ilo_state_vector
*vec
,
763 struct gen6_draw_session
*session
)
765 /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
766 if (DIRTY(FB
) || r
->batch_bo_changed
) {
767 const struct ilo_zs_surface
*zs
;
768 uint32_t clear_params
;
770 if (vec
->fb
.state
.zsbuf
) {
771 const struct ilo_surface_cso
*surface
=
772 (const struct ilo_surface_cso
*) vec
->fb
.state
.zsbuf
;
773 const struct ilo_texture_slice
*slice
=
774 ilo_texture_get_slice(ilo_texture(surface
->base
.texture
),
775 surface
->base
.u
.tex
.level
, surface
->base
.u
.tex
.first_layer
);
777 assert(!surface
->is_rt
);
780 clear_params
= slice
->clear_value
;
783 zs
= &vec
->fb
.null_zs
;
787 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6)) {
788 gen6_wa_pre_non_pipelined(r
);
789 gen6_wa_pre_depth(r
);
792 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
, zs
);
793 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
, zs
);
794 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
, zs
);
795 gen6_3DSTATE_CLEAR_PARAMS(r
->builder
, clear_params
);
800 gen6_draw_wm_raster(struct ilo_render
*r
,
801 const struct ilo_state_vector
*vec
,
802 struct gen6_draw_session
*session
)
804 /* 3DSTATE_POLY_STIPPLE_PATTERN and 3DSTATE_POLY_STIPPLE_OFFSET */
805 if ((DIRTY(RASTERIZER
) || DIRTY(POLY_STIPPLE
)) &&
806 vec
->rasterizer
->state
.poly_stipple_enable
) {
807 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
808 gen6_wa_pre_non_pipelined(r
);
810 gen6_3DSTATE_POLY_STIPPLE_PATTERN(r
->builder
,
813 gen6_3DSTATE_POLY_STIPPLE_OFFSET(r
->builder
, 0, 0);
816 /* 3DSTATE_LINE_STIPPLE */
817 if (DIRTY(RASTERIZER
) && vec
->rasterizer
->state
.line_stipple_enable
) {
818 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
819 gen6_wa_pre_non_pipelined(r
);
821 gen6_3DSTATE_LINE_STIPPLE(r
->builder
,
822 vec
->rasterizer
->state
.line_stipple_pattern
,
823 vec
->rasterizer
->state
.line_stipple_factor
+ 1);
826 /* 3DSTATE_AA_LINE_PARAMETERS */
827 if (DIRTY(RASTERIZER
) && vec
->rasterizer
->state
.line_smooth
) {
828 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
829 gen6_wa_pre_non_pipelined(r
);
831 gen6_3DSTATE_AA_LINE_PARAMETERS(r
->builder
);
838 gen6_draw_commands(struct ilo_render
*render
,
839 const struct ilo_state_vector
*vec
,
840 struct gen6_draw_session
*session
)
843 * We try to keep the order of the commands match, as closely as possible,
844 * that of the classic i965 driver. It allows us to compare the command
847 gen6_draw_common_select(render
, vec
, session
);
848 gen6_draw_gs_svbi(render
, vec
, session
);
849 gen6_draw_common_sip(render
, vec
, session
);
850 gen6_draw_vf_statistics(render
, vec
, session
);
851 gen6_draw_common_base_address(render
, vec
, session
);
852 gen6_draw_common_pointers_1(render
, vec
, session
);
853 gen6_draw_common_urb(render
, vec
, session
);
854 gen6_draw_common_pointers_2(render
, vec
, session
);
855 gen6_draw_wm_multisample(render
, vec
, session
);
856 gen6_draw_vs(render
, vec
, session
);
857 gen6_draw_gs(render
, vec
, session
);
858 gen6_draw_clip(render
, vec
, session
);
859 gen6_draw_sf(render
, vec
, session
);
860 gen6_draw_wm(render
, vec
, session
);
861 gen6_draw_common_pointers_3(render
, vec
, session
);
862 gen6_draw_wm_depth(render
, vec
, session
);
863 gen6_draw_wm_raster(render
, vec
, session
);
864 gen6_draw_sf_rect(render
, vec
, session
);
865 gen6_draw_vf(render
, vec
, session
);
866 gen6_draw_vf_draw(render
, vec
, session
);
870 gen6_draw_prepare(struct ilo_render
*render
,
871 const struct ilo_state_vector
*vec
,
872 struct gen6_draw_session
*session
)
874 memset(session
, 0, sizeof(*session
));
875 session
->pipe_dirty
= vec
->dirty
;
876 session
->reduced_prim
= u_reduced_prim(vec
->draw
->mode
);
878 if (render
->hw_ctx_changed
) {
879 /* these should be enough to make everything uploaded */
880 render
->batch_bo_changed
= true;
881 render
->state_bo_changed
= true;
882 render
->instruction_bo_changed
= true;
884 session
->prim_changed
= true;
885 session
->primitive_restart_changed
= true;
887 session
->prim_changed
=
888 (render
->state
.reduced_prim
!= session
->reduced_prim
);
889 session
->primitive_restart_changed
=
890 (render
->state
.primitive_restart
!= vec
->draw
->primitive_restart
);
895 gen6_draw_emit(struct ilo_render
*render
,
896 const struct ilo_state_vector
*vec
,
897 struct gen6_draw_session
*session
)
899 /* force all states to be uploaded if the state bo changed */
900 if (render
->state_bo_changed
)
901 session
->pipe_dirty
= ILO_DIRTY_ALL
;
903 session
->pipe_dirty
= vec
->dirty
;
905 ilo_render_emit_draw_dynamic_states(render
, vec
, session
);
906 ilo_render_emit_draw_surface_states(render
, vec
, session
);
908 /* force all commands to be uploaded if the HW context changed */
909 if (render
->hw_ctx_changed
)
910 session
->pipe_dirty
= ILO_DIRTY_ALL
;
912 session
->pipe_dirty
= vec
->dirty
;
914 session
->emit_draw_commands(render
, vec
, session
);
918 gen6_draw_end(struct ilo_render
*render
,
919 const struct ilo_state_vector
*vec
,
920 struct gen6_draw_session
*session
)
922 render
->hw_ctx_changed
= false;
924 render
->batch_bo_changed
= false;
925 render
->state_bo_changed
= false;
926 render
->instruction_bo_changed
= false;
928 render
->state
.reduced_prim
= session
->reduced_prim
;
929 render
->state
.primitive_restart
= vec
->draw
->primitive_restart
;
933 ilo_render_emit_draw_gen6(struct ilo_render
*render
,
934 const struct ilo_state_vector
*vec
)
936 struct gen6_draw_session session
;
938 gen6_draw_prepare(render
, vec
, &session
);
940 session
.emit_draw_commands
= gen6_draw_commands
;
942 gen6_draw_emit(render
, vec
, &session
);
943 gen6_draw_end(render
, vec
, &session
);
947 gen6_rectlist_vs_to_sf(struct ilo_render
*r
,
948 const struct ilo_blitter
*blitter
)
950 gen6_3DSTATE_CONSTANT_VS(r
->builder
, NULL
, NULL
, 0);
951 gen6_3DSTATE_VS(r
->builder
, NULL
, 0);
953 gen6_wa_post_3dstate_constant_vs(r
);
955 gen6_3DSTATE_CONSTANT_GS(r
->builder
, NULL
, NULL
, 0);
956 gen6_3DSTATE_GS(r
->builder
, NULL
, NULL
, 0);
958 gen6_3DSTATE_CLIP(r
->builder
, NULL
, NULL
, false, 0);
959 gen6_3DSTATE_SF(r
->builder
, NULL
, NULL
);
963 gen6_rectlist_wm(struct ilo_render
*r
,
964 const struct ilo_blitter
*blitter
)
968 switch (blitter
->op
) {
969 case ILO_BLITTER_RECTLIST_CLEAR_ZS
:
970 hiz_op
= GEN6_WM_DW4_DEPTH_CLEAR
;
972 case ILO_BLITTER_RECTLIST_RESOLVE_Z
:
973 hiz_op
= GEN6_WM_DW4_DEPTH_RESOLVE
;
975 case ILO_BLITTER_RECTLIST_RESOLVE_HIZ
:
976 hiz_op
= GEN6_WM_DW4_HIZ_RESOLVE
;
983 gen6_3DSTATE_CONSTANT_PS(r
->builder
, NULL
, NULL
, 0);
985 gen6_wa_pre_3dstate_wm_max_threads(r
);
986 gen6_3DSTATE_WM(r
->builder
, NULL
, 0, NULL
, false, false, hiz_op
);
990 gen6_rectlist_wm_depth(struct ilo_render
*r
,
991 const struct ilo_blitter
*blitter
)
993 gen6_wa_pre_depth(r
);
995 if (blitter
->uses
& (ILO_BLITTER_USE_FB_DEPTH
|
996 ILO_BLITTER_USE_FB_STENCIL
)) {
997 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
,
998 &blitter
->fb
.dst
.u
.zs
);
1001 if (blitter
->uses
& ILO_BLITTER_USE_FB_DEPTH
) {
1002 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
,
1003 &blitter
->fb
.dst
.u
.zs
);
1006 if (blitter
->uses
& ILO_BLITTER_USE_FB_STENCIL
) {
1007 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
,
1008 &blitter
->fb
.dst
.u
.zs
);
1011 gen6_3DSTATE_CLEAR_PARAMS(r
->builder
,
1012 blitter
->depth_clear_value
);
1016 gen6_rectlist_wm_multisample(struct ilo_render
*r
,
1017 const struct ilo_blitter
*blitter
)
1019 const uint32_t *packed_sample_pos
= (blitter
->fb
.num_samples
> 1) ?
1020 &r
->packed_sample_position_4x
: &r
->packed_sample_position_1x
;
1022 gen6_wa_pre_3dstate_multisample(r
);
1024 gen6_3DSTATE_MULTISAMPLE(r
->builder
, blitter
->fb
.num_samples
,
1025 packed_sample_pos
, true);
1027 gen6_3DSTATE_SAMPLE_MASK(r
->builder
,
1028 (1 << blitter
->fb
.num_samples
) - 1);
1032 gen6_rectlist_commands(struct ilo_render
*r
,
1033 const struct ilo_blitter
*blitter
)
1035 gen6_wa_pre_non_pipelined(r
);
1037 gen6_rectlist_wm_multisample(r
, blitter
);
1039 gen6_state_base_address(r
->builder
, true);
1041 gen6_3DSTATE_VERTEX_BUFFERS(r
->builder
,
1042 &blitter
->ve
, &blitter
->vb
);
1044 gen6_3DSTATE_VERTEX_ELEMENTS(r
->builder
,
1045 &blitter
->ve
, false, false);
1047 gen6_3DSTATE_URB(r
->builder
,
1048 r
->dev
->urb_size
, 0, blitter
->ve
.count
* 4 * sizeof(float), 0);
1049 /* 3DSTATE_URB workaround */
1050 if (r
->state
.gs
.active
) {
1051 ilo_render_emit_flush(r
);
1052 r
->state
.gs
.active
= false;
1056 (ILO_BLITTER_USE_DSA
| ILO_BLITTER_USE_CC
)) {
1057 gen6_3DSTATE_CC_STATE_POINTERS(r
->builder
, 0,
1058 r
->state
.DEPTH_STENCIL_STATE
, r
->state
.COLOR_CALC_STATE
);
1061 gen6_rectlist_vs_to_sf(r
, blitter
);
1062 gen6_rectlist_wm(r
, blitter
);
1064 if (blitter
->uses
& ILO_BLITTER_USE_VIEWPORT
) {
1065 gen6_3DSTATE_VIEWPORT_STATE_POINTERS(r
->builder
,
1066 0, 0, r
->state
.CC_VIEWPORT
);
1069 gen6_rectlist_wm_depth(r
, blitter
);
1071 gen6_3DSTATE_DRAWING_RECTANGLE(r
->builder
, 0, 0,
1072 blitter
->fb
.width
, blitter
->fb
.height
);
1074 gen6_3DPRIMITIVE(r
->builder
, &blitter
->draw
, NULL
);
1078 ilo_render_emit_rectlist_gen6(struct ilo_render
*render
,
1079 const struct ilo_blitter
*blitter
)
1081 ilo_render_emit_rectlist_dynamic_states(render
, blitter
);
1082 gen6_rectlist_commands(render
, blitter
);
1086 gen6_render_max_command_size(const struct ilo_render
*render
)
1091 size
+= GEN6_3DSTATE_CONSTANT_ANY__SIZE
* 3;
1092 size
+= GEN6_3DSTATE_GS_SVB_INDEX__SIZE
* 4;
1093 size
+= GEN6_PIPE_CONTROL__SIZE
* 5;
1096 GEN6_STATE_BASE_ADDRESS__SIZE
+
1097 GEN6_STATE_SIP__SIZE
+
1098 GEN6_3DSTATE_VF_STATISTICS__SIZE
+
1099 GEN6_PIPELINE_SELECT__SIZE
+
1100 GEN6_3DSTATE_BINDING_TABLE_POINTERS__SIZE
+
1101 GEN6_3DSTATE_SAMPLER_STATE_POINTERS__SIZE
+
1102 GEN6_3DSTATE_URB__SIZE
+
1103 GEN6_3DSTATE_VERTEX_BUFFERS__SIZE
+
1104 GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE
+
1105 GEN6_3DSTATE_INDEX_BUFFER__SIZE
+
1106 GEN6_3DSTATE_VIEWPORT_STATE_POINTERS__SIZE
+
1107 GEN6_3DSTATE_CC_STATE_POINTERS__SIZE
+
1108 GEN6_3DSTATE_SCISSOR_STATE_POINTERS__SIZE
+
1109 GEN6_3DSTATE_VS__SIZE
+
1110 GEN6_3DSTATE_GS__SIZE
+
1111 GEN6_3DSTATE_CLIP__SIZE
+
1112 GEN6_3DSTATE_SF__SIZE
+
1113 GEN6_3DSTATE_WM__SIZE
+
1114 GEN6_3DSTATE_SAMPLE_MASK__SIZE
+
1115 GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE
+
1116 GEN6_3DSTATE_DEPTH_BUFFER__SIZE
+
1117 GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE
+
1118 GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE
+
1119 GEN6_3DSTATE_LINE_STIPPLE__SIZE
+
1120 GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE
+
1121 GEN6_3DSTATE_MULTISAMPLE__SIZE
+
1122 GEN6_3DSTATE_STENCIL_BUFFER__SIZE
+
1123 GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE
+
1124 GEN6_3DSTATE_CLEAR_PARAMS__SIZE
+
1125 GEN6_3DPRIMITIVE__SIZE
;
1132 ilo_render_estimate_size_gen6(struct ilo_render
*render
,
1133 enum ilo_render_action action
,
1139 case ILO_RENDER_DRAW
:
1141 const struct ilo_state_vector
*vec
= arg
;
1143 size
= gen6_render_max_command_size(render
) +
1144 ilo_render_get_draw_dynamic_states_len(render
, vec
) +
1145 ilo_render_get_draw_surface_states_len(render
, vec
);
1148 case ILO_RENDER_RECTLIST
:
1150 const struct ilo_blitter
*blitter
= arg
;
1152 size
= ilo_render_get_rectlist_dynamic_states_len(render
, blitter
);
1153 size
+= 256; /* commands */
1157 assert(!"unknown render action");
1166 ilo_render_init_gen6(struct ilo_render
*render
)
1168 render
->estimate_size
= ilo_render_estimate_size_gen6
;
1169 render
->emit_draw
= ilo_render_emit_draw_gen6
;
1170 render
->emit_rectlist
= ilo_render_emit_rectlist_gen6
;