2 * Mesa 3-D graphics library
4 * Copyright (C) 2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "genhw/genhw.h"
29 #include "util/u_dual_blend.h"
30 #include "util/u_prim.h"
32 #include "ilo_blitter.h"
33 #include "ilo_builder_3d.h"
34 #include "ilo_builder_mi.h"
35 #include "ilo_builder_render.h"
36 #include "ilo_query.h"
37 #include "ilo_shader.h"
38 #include "ilo_state.h"
39 #include "ilo_render_gen.h"
42 * A wrapper for gen6_PIPE_CONTROL().
45 gen6_pipe_control(struct ilo_render
*r
, uint32_t dw1
)
47 struct intel_bo
*bo
= (dw1
& GEN6_PIPE_CONTROL_WRITE__MASK
) ?
48 r
->workaround_bo
: NULL
;
50 ILO_DEV_ASSERT(r
->dev
, 6, 6);
52 gen6_PIPE_CONTROL(r
->builder
, dw1
, bo
, 0, 0);
54 r
->state
.current_pipe_control_dw1
|= dw1
;
56 assert(!r
->state
.deferred_pipe_control_dw1
);
60 * This should be called before PIPE_CONTROL.
63 gen6_wa_pre_pipe_control(struct ilo_render
*r
, uint32_t dw1
)
66 * From the Sandy Bridge PRM, volume 2 part 1, page 60:
68 * "Pipe-control with CS-stall bit set must be sent BEFORE the
69 * pipe-control with a post-sync op and no write-cache flushes."
71 * This WA may also be triggered indirectly by the other two WAs on the
74 * "Before any depth stall flush (including those produced by
75 * non-pipelined state commands), software needs to first send a
76 * PIPE_CONTROL with no bits set except Post-Sync Operation != 0."
78 * "Before a PIPE_CONTROL with Write Cache Flush Enable =1, a
79 * PIPE_CONTROL with any non-zero post-sync-op is required."
81 const bool direct_wa_cond
= (dw1
& GEN6_PIPE_CONTROL_WRITE__MASK
) &&
82 !(dw1
& GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH
);
83 const bool indirect_wa_cond
= (dw1
& GEN6_PIPE_CONTROL_DEPTH_STALL
) |
84 (dw1
& GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH
);
86 ILO_DEV_ASSERT(r
->dev
, 6, 6);
88 if (!direct_wa_cond
&& !indirect_wa_cond
)
91 if (!(r
->state
.current_pipe_control_dw1
& GEN6_PIPE_CONTROL_CS_STALL
)) {
93 * From the Sandy Bridge PRM, volume 2 part 1, page 73:
95 * "1 of the following must also be set (when CS stall is set):
97 * - Depth Cache Flush Enable ([0] of DW1)
98 * - Stall at Pixel Scoreboard ([1] of DW1)
99 * - Depth Stall ([13] of DW1)
100 * - Post-Sync Operation ([13] of DW1)
101 * - Render Target Cache Flush Enable ([12] of DW1)
102 * - Notify Enable ([8] of DW1)"
104 * Because of the WAs above, we have to pick Stall at Pixel Scoreboard.
106 const uint32_t direct_wa
= GEN6_PIPE_CONTROL_CS_STALL
|
107 GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL
;
109 gen6_pipe_control(r
, direct_wa
);
112 if (indirect_wa_cond
&&
113 !(r
->state
.current_pipe_control_dw1
& GEN6_PIPE_CONTROL_WRITE__MASK
)) {
114 const uint32_t indirect_wa
= GEN6_PIPE_CONTROL_WRITE_IMM
;
116 gen6_pipe_control(r
, indirect_wa
);
121 * This should be called before any non-pipelined state command.
124 gen6_wa_pre_non_pipelined(struct ilo_render
*r
)
126 ILO_DEV_ASSERT(r
->dev
, 6, 6);
128 /* non-pipelined state commands produce depth stall */
129 gen6_wa_pre_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
133 gen6_wa_post_3dstate_constant_vs(struct ilo_render
*r
)
136 * According to upload_vs_state() of the classic driver, we need to emit a
137 * PIPE_CONTROL after 3DSTATE_CONSTANT_VS, otherwise the command is kept
138 * being buffered by VS FF, to the point that the FF dies.
140 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_STALL
|
141 GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
|
142 GEN6_PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
144 gen6_wa_pre_pipe_control(r
, dw1
);
146 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
147 gen6_pipe_control(r
, dw1
);
151 gen6_wa_pre_3dstate_wm_max_threads(struct ilo_render
*r
)
154 * From the Sandy Bridge PRM, volume 2 part 1, page 274:
156 * "A PIPE_CONTROL command, with only the Stall At Pixel Scoreboard
157 * field set (DW1 Bit 1), must be issued prior to any change to the
158 * value in this field (Maximum Number of Threads in 3DSTATE_WM)"
160 const uint32_t dw1
= GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL
;
162 ILO_DEV_ASSERT(r
->dev
, 6, 6);
164 gen6_wa_pre_pipe_control(r
, dw1
);
166 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
167 gen6_pipe_control(r
, dw1
);
171 gen6_wa_pre_3dstate_multisample(struct ilo_render
*r
)
174 * From the Sandy Bridge PRM, volume 2 part 1, page 305:
176 * "Driver must guarentee that all the caches in the depth pipe are
177 * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
178 * requires driver to send a PIPE_CONTROL with a CS stall along with a
179 * Depth Flush prior to this command."
181 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
182 GEN6_PIPE_CONTROL_CS_STALL
;
184 ILO_DEV_ASSERT(r
->dev
, 6, 6);
186 gen6_wa_pre_pipe_control(r
, dw1
);
188 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
189 gen6_pipe_control(r
, dw1
);
193 gen6_wa_pre_depth(struct ilo_render
*r
)
195 ILO_DEV_ASSERT(r
->dev
, 6, 6);
198 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
200 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
201 * any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
202 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
203 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
204 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
205 * Depth Flush Bit set, followed by another pipelined depth stall
206 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
207 * guarantee that the pipeline from WM onwards is already flushed
208 * (e.g., via a preceding MI_FLUSH)."
210 * According to the classic driver, it also applies for GEN6.
212 gen6_wa_pre_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
|
213 GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
215 gen6_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
216 gen6_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
217 gen6_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
220 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
223 gen6_draw_common_select(struct ilo_render
*r
,
224 const struct ilo_state_vector
*vec
,
225 struct ilo_render_draw_session
*session
)
227 /* PIPELINE_SELECT */
228 if (r
->hw_ctx_changed
) {
229 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
230 gen6_wa_pre_non_pipelined(r
);
232 gen6_PIPELINE_SELECT(r
->builder
, 0x0);
237 gen6_draw_common_sip(struct ilo_render
*r
,
238 const struct ilo_state_vector
*vec
,
239 struct ilo_render_draw_session
*session
)
242 if (r
->hw_ctx_changed
) {
243 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
244 gen6_wa_pre_non_pipelined(r
);
246 gen6_STATE_SIP(r
->builder
, 0);
251 gen6_draw_common_base_address(struct ilo_render
*r
,
252 const struct ilo_state_vector
*vec
,
253 struct ilo_render_draw_session
*session
)
255 /* STATE_BASE_ADDRESS */
256 if (r
->state_bo_changed
|| r
->instruction_bo_changed
||
257 r
->batch_bo_changed
) {
258 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
259 gen6_wa_pre_non_pipelined(r
);
261 if (ilo_dev_gen(r
->dev
) >= ILO_GEN(8))
262 gen8_state_base_address(r
->builder
, r
->hw_ctx_changed
);
264 gen6_state_base_address(r
->builder
, r
->hw_ctx_changed
);
267 * From the Sandy Bridge PRM, volume 1 part 1, page 28:
269 * "The following commands must be reissued following any change to
270 * the base addresses:
272 * * 3DSTATE_BINDING_TABLE_POINTERS
273 * * 3DSTATE_SAMPLER_STATE_POINTERS
274 * * 3DSTATE_VIEWPORT_STATE_POINTERS
275 * * 3DSTATE_CC_POINTERS
276 * * MEDIA_STATE_POINTERS"
278 * 3DSTATE_SCISSOR_STATE_POINTERS is not on the list, but it is
279 * reasonable to also reissue the command. Same to PCB.
281 session
->viewport_changed
= true;
283 session
->scissor_changed
= true;
285 session
->blend_changed
= true;
286 session
->dsa_changed
= true;
287 session
->cc_changed
= true;
289 session
->sampler_vs_changed
= true;
290 session
->sampler_gs_changed
= true;
291 session
->sampler_fs_changed
= true;
293 session
->pcb_vs_changed
= true;
294 session
->pcb_gs_changed
= true;
295 session
->pcb_fs_changed
= true;
297 session
->binding_table_vs_changed
= true;
298 session
->binding_table_gs_changed
= true;
299 session
->binding_table_fs_changed
= true;
304 gen6_draw_common_urb(struct ilo_render
*r
,
305 const struct ilo_state_vector
*vec
,
306 struct ilo_render_draw_session
*session
)
309 if (DIRTY(VE
) || DIRTY(VS
) || DIRTY(GS
)) {
310 const bool gs_active
= (vec
->gs
|| (vec
->vs
&&
311 ilo_shader_get_kernel_param(vec
->vs
, ILO_KERNEL_VS_GEN6_SO
)));
312 int vs_entry_size
, gs_entry_size
;
313 int vs_total_size
, gs_total_size
;
315 vs_entry_size
= (vec
->vs
) ?
316 ilo_shader_get_kernel_param(vec
->vs
, ILO_KERNEL_OUTPUT_COUNT
) : 0;
319 * As indicated by 2e712e41db0c0676e9f30fc73172c0e8de8d84d4, VF and VS
320 * share VUE handles. The VUE allocation size must be large enough to
321 * store either VF outputs (number of VERTEX_ELEMENTs) and VS outputs.
323 * I am not sure if the PRM explicitly states that VF and VS share VUE
324 * handles. But here is a citation that implies so:
326 * From the Sandy Bridge PRM, volume 2 part 1, page 44:
328 * "Once a FF stage that spawn threads has sufficient input to
329 * initiate a thread, it must guarantee that it is safe to request
330 * the thread initiation. For all these FF stages, this check is
333 * - The availability of output URB entries:
334 * - VS: As the input URB entries are overwritten with the
335 * VS-generated output data, output URB availability isn't a
338 if (vs_entry_size
< vec
->ve
->count
+ vec
->ve
->prepend_nosrc_cso
)
339 vs_entry_size
= vec
->ve
->count
+ vec
->ve
->prepend_nosrc_cso
;
341 gs_entry_size
= (vec
->gs
) ?
342 ilo_shader_get_kernel_param(vec
->gs
, ILO_KERNEL_OUTPUT_COUNT
) :
343 (gs_active
) ? vs_entry_size
: 0;
346 vs_entry_size
*= sizeof(float) * 4;
347 gs_entry_size
*= sizeof(float) * 4;
348 vs_total_size
= r
->dev
->urb_size
;
352 gs_total_size
= vs_total_size
;
358 gen6_3DSTATE_URB(r
->builder
, vs_total_size
, gs_total_size
,
359 vs_entry_size
, gs_entry_size
);
362 * From the Sandy Bridge PRM, volume 2 part 1, page 27:
364 * "Because of a urb corruption caused by allocating a previous
365 * gsunit's urb entry to vsunit software is required to send a
366 * "GS NULL Fence" (Send URB fence with VS URB size == 1 and GS URB
367 * size == 0) plus a dummy DRAW call before any case where VS will
368 * be taking over GS URB space."
370 if (r
->state
.gs
.active
&& !gs_active
)
371 ilo_render_emit_flush(r
);
373 r
->state
.gs
.active
= gs_active
;
378 gen6_draw_common_pointers_1(struct ilo_render
*r
,
379 const struct ilo_state_vector
*vec
,
380 struct ilo_render_draw_session
*session
)
382 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
383 if (session
->viewport_changed
) {
384 gen6_3DSTATE_VIEWPORT_STATE_POINTERS(r
->builder
,
385 r
->state
.CLIP_VIEWPORT
,
386 r
->state
.SF_VIEWPORT
,
387 r
->state
.CC_VIEWPORT
);
392 gen6_draw_common_pointers_2(struct ilo_render
*r
,
393 const struct ilo_state_vector
*vec
,
394 struct ilo_render_draw_session
*session
)
396 /* 3DSTATE_CC_STATE_POINTERS */
397 if (session
->blend_changed
||
398 session
->dsa_changed
||
399 session
->cc_changed
) {
400 gen6_3DSTATE_CC_STATE_POINTERS(r
->builder
,
401 r
->state
.BLEND_STATE
,
402 r
->state
.DEPTH_STENCIL_STATE
,
403 r
->state
.COLOR_CALC_STATE
);
406 /* 3DSTATE_SAMPLER_STATE_POINTERS */
407 if (session
->sampler_vs_changed
||
408 session
->sampler_gs_changed
||
409 session
->sampler_fs_changed
) {
410 gen6_3DSTATE_SAMPLER_STATE_POINTERS(r
->builder
,
411 r
->state
.vs
.SAMPLER_STATE
,
413 r
->state
.wm
.SAMPLER_STATE
);
418 gen6_draw_common_pointers_3(struct ilo_render
*r
,
419 const struct ilo_state_vector
*vec
,
420 struct ilo_render_draw_session
*session
)
422 /* 3DSTATE_SCISSOR_STATE_POINTERS */
423 if (session
->scissor_changed
) {
424 gen6_3DSTATE_SCISSOR_STATE_POINTERS(r
->builder
,
425 r
->state
.SCISSOR_RECT
);
428 /* 3DSTATE_BINDING_TABLE_POINTERS */
429 if (session
->binding_table_vs_changed
||
430 session
->binding_table_gs_changed
||
431 session
->binding_table_fs_changed
) {
432 gen6_3DSTATE_BINDING_TABLE_POINTERS(r
->builder
,
433 r
->state
.vs
.BINDING_TABLE_STATE
,
434 r
->state
.gs
.BINDING_TABLE_STATE
,
435 r
->state
.wm
.BINDING_TABLE_STATE
);
440 gen6_draw_vf(struct ilo_render
*r
,
441 const struct ilo_state_vector
*vec
,
442 struct ilo_render_draw_session
*session
)
444 if (ilo_dev_gen(r
->dev
) >= ILO_GEN(7.5)) {
445 /* 3DSTATE_INDEX_BUFFER */
446 if (DIRTY(IB
) || r
->batch_bo_changed
) {
447 gen6_3DSTATE_INDEX_BUFFER(r
->builder
,
452 if (session
->primitive_restart_changed
) {
453 gen75_3DSTATE_VF(r
->builder
, vec
->draw
->primitive_restart
,
454 vec
->draw
->restart_index
);
458 /* 3DSTATE_INDEX_BUFFER */
459 if (DIRTY(IB
) || session
->primitive_restart_changed
||
460 r
->batch_bo_changed
) {
461 gen6_3DSTATE_INDEX_BUFFER(r
->builder
,
462 &vec
->ib
, vec
->draw
->primitive_restart
);
466 /* 3DSTATE_VERTEX_BUFFERS */
467 if (DIRTY(VB
) || DIRTY(VE
) || r
->batch_bo_changed
)
468 gen6_3DSTATE_VERTEX_BUFFERS(r
->builder
, vec
->ve
, &vec
->vb
);
470 /* 3DSTATE_VERTEX_ELEMENTS */
472 gen6_3DSTATE_VERTEX_ELEMENTS(r
->builder
, vec
->ve
);
476 gen6_draw_vf_statistics(struct ilo_render
*r
,
477 const struct ilo_state_vector
*vec
,
478 struct ilo_render_draw_session
*session
)
480 /* 3DSTATE_VF_STATISTICS */
481 if (r
->hw_ctx_changed
)
482 gen6_3DSTATE_VF_STATISTICS(r
->builder
, false);
486 gen6_draw_vf_draw(struct ilo_render
*r
,
487 const struct ilo_state_vector
*vec
,
488 struct ilo_render_draw_session
*session
)
491 gen6_3DPRIMITIVE(r
->builder
, vec
->draw
, &vec
->ib
);
493 r
->state
.current_pipe_control_dw1
= 0;
494 assert(!r
->state
.deferred_pipe_control_dw1
);
498 gen6_draw_vs(struct ilo_render
*r
,
499 const struct ilo_state_vector
*vec
,
500 struct ilo_render_draw_session
*session
)
502 const bool emit_3dstate_vs
= (DIRTY(VS
) || r
->instruction_bo_changed
);
503 const bool emit_3dstate_constant_vs
= session
->pcb_vs_changed
;
506 * the classic i965 does this in upload_vs_state(), citing a spec that I
509 if (emit_3dstate_vs
&& ilo_dev_gen(r
->dev
) == ILO_GEN(6))
510 gen6_wa_pre_non_pipelined(r
);
512 /* 3DSTATE_CONSTANT_VS */
513 if (emit_3dstate_constant_vs
) {
514 gen6_3DSTATE_CONSTANT_VS(r
->builder
,
515 &r
->state
.vs
.PUSH_CONSTANT_BUFFER
,
516 &r
->state
.vs
.PUSH_CONSTANT_BUFFER_size
,
522 gen6_3DSTATE_VS(r
->builder
, vec
->vs
);
524 if (emit_3dstate_constant_vs
&& ilo_dev_gen(r
->dev
) == ILO_GEN(6))
525 gen6_wa_post_3dstate_constant_vs(r
);
529 gen6_draw_gs(struct ilo_render
*r
,
530 const struct ilo_state_vector
*vec
,
531 struct ilo_render_draw_session
*session
)
533 /* 3DSTATE_CONSTANT_GS */
534 if (session
->pcb_gs_changed
)
535 gen6_3DSTATE_CONSTANT_GS(r
->builder
, NULL
, NULL
, 0);
538 if (DIRTY(GS
) || DIRTY(VS
) ||
539 session
->prim_changed
|| r
->instruction_bo_changed
) {
541 gen6_3DSTATE_GS(r
->builder
, vec
->gs
);
542 } else if (vec
->vs
&&
543 ilo_shader_get_kernel_param(vec
->vs
, ILO_KERNEL_VS_GEN6_SO
)) {
544 const int verts_per_prim
= u_vertices_per_prim(session
->reduced_prim
);
545 gen6_so_3DSTATE_GS(r
->builder
, vec
->vs
, verts_per_prim
);
547 gen6_disable_3DSTATE_GS(r
->builder
);
553 gen6_draw_update_max_svbi(struct ilo_render
*r
,
554 const struct ilo_state_vector
*vec
,
555 struct ilo_render_draw_session
*session
)
557 if (DIRTY(VS
) || DIRTY(GS
) || DIRTY(SO
)) {
558 const struct pipe_stream_output_info
*so_info
=
559 (vec
->gs
) ? ilo_shader_get_kernel_so_info(vec
->gs
) :
560 (vec
->vs
) ? ilo_shader_get_kernel_so_info(vec
->vs
) : NULL
;
561 unsigned max_svbi
= 0xffffffff;
564 for (i
= 0; i
< so_info
->num_outputs
; i
++) {
565 const int output_buffer
= so_info
->output
[i
].output_buffer
;
566 const struct pipe_stream_output_target
*so
=
567 vec
->so
.states
[output_buffer
];
568 const int struct_size
= so_info
->stride
[output_buffer
] * 4;
569 const int elem_size
= so_info
->output
[i
].num_components
* 4;
577 buf_size
= so
->buffer_size
- so_info
->output
[i
].dst_offset
* 4;
579 count
= buf_size
/ struct_size
;
580 if (buf_size
% struct_size
>= elem_size
)
583 if (count
< max_svbi
)
587 if (r
->state
.so_max_vertices
!= max_svbi
) {
588 r
->state
.so_max_vertices
= max_svbi
;
597 gen6_draw_gs_svbi(struct ilo_render
*r
,
598 const struct ilo_state_vector
*vec
,
599 struct ilo_render_draw_session
*session
)
601 const bool emit
= gen6_draw_update_max_svbi(r
, vec
, session
);
603 /* 3DSTATE_GS_SVB_INDEX */
605 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
606 gen6_wa_pre_non_pipelined(r
);
608 gen6_3DSTATE_GS_SVB_INDEX(r
->builder
,
609 0, 0, r
->state
.so_max_vertices
,
612 if (r
->hw_ctx_changed
) {
616 * From the Sandy Bridge PRM, volume 2 part 1, page 148:
618 * "If a buffer is not enabled then the SVBI must be set to 0x0
619 * in order to not cause overflow in that SVBI."
621 * "If a buffer is not enabled then the MaxSVBI must be set to
622 * 0xFFFFFFFF in order to not cause overflow in that SVBI."
624 for (i
= 1; i
< 4; i
++) {
625 gen6_3DSTATE_GS_SVB_INDEX(r
->builder
,
626 i
, 0, 0xffffffff, false);
633 gen6_draw_clip(struct ilo_render
*r
,
634 const struct ilo_state_vector
*vec
,
635 struct ilo_render_draw_session
*session
)
638 if (DIRTY(RASTERIZER
) || DIRTY(FS
) || DIRTY(VIEWPORT
) || DIRTY(FB
)) {
639 bool enable_guardband
= true;
643 * Gen8+ has viewport extent test. Guard band test can be enabled on
644 * prior Gens only when the viewport is larger than the framebuffer,
645 * unless we emulate viewport extent test on them.
647 if (ilo_dev_gen(r
->dev
) < ILO_GEN(8)) {
648 for (i
= 0; i
< vec
->viewport
.count
; i
++) {
649 const struct ilo_viewport_cso
*vp
= &vec
->viewport
.cso
[i
];
651 if (vp
->min_x
> 0.0f
|| vp
->max_x
< vec
->fb
.state
.width
||
652 vp
->min_y
> 0.0f
|| vp
->max_y
< vec
->fb
.state
.height
) {
653 enable_guardband
= false;
659 gen6_3DSTATE_CLIP(r
->builder
, vec
->rasterizer
,
660 vec
->fs
, enable_guardband
, 1);
665 gen6_draw_sf(struct ilo_render
*r
,
666 const struct ilo_state_vector
*vec
,
667 struct ilo_render_draw_session
*session
)
670 if (DIRTY(RASTERIZER
) || DIRTY(FS
) || DIRTY(FB
)) {
671 gen6_3DSTATE_SF(r
->builder
, vec
->rasterizer
, vec
->fs
,
672 vec
->fb
.num_samples
);
677 gen6_draw_sf_rect(struct ilo_render
*r
,
678 const struct ilo_state_vector
*vec
,
679 struct ilo_render_draw_session
*session
)
681 /* 3DSTATE_DRAWING_RECTANGLE */
683 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
684 gen6_wa_pre_non_pipelined(r
);
686 gen6_3DSTATE_DRAWING_RECTANGLE(r
->builder
, 0, 0,
687 vec
->fb
.state
.width
, vec
->fb
.state
.height
);
692 gen6_draw_wm(struct ilo_render
*r
,
693 const struct ilo_state_vector
*vec
,
694 struct ilo_render_draw_session
*session
)
696 /* 3DSTATE_CONSTANT_PS */
697 if (session
->pcb_fs_changed
) {
698 gen6_3DSTATE_CONSTANT_PS(r
->builder
,
699 &r
->state
.wm
.PUSH_CONSTANT_BUFFER
,
700 &r
->state
.wm
.PUSH_CONSTANT_BUFFER_size
,
705 if (DIRTY(FS
) || DIRTY(BLEND
) || DIRTY(DSA
) ||
706 DIRTY(RASTERIZER
) || r
->instruction_bo_changed
) {
707 const bool dual_blend
= vec
->blend
->dual_blend
;
708 const bool cc_may_kill
= (vec
->dsa
->dw_blend_alpha
||
709 vec
->blend
->alpha_to_coverage
);
711 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6) && r
->hw_ctx_changed
)
712 gen6_wa_pre_3dstate_wm_max_threads(r
);
714 gen6_3DSTATE_WM(r
->builder
, vec
->fs
,
715 vec
->rasterizer
, dual_blend
, cc_may_kill
);
720 gen6_draw_wm_multisample(struct ilo_render
*r
,
721 const struct ilo_state_vector
*vec
,
722 struct ilo_render_draw_session
*session
)
724 /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
725 if (DIRTY(SAMPLE_MASK
) || DIRTY(FB
)) {
726 const uint32_t *pattern
;
728 pattern
= (vec
->fb
.num_samples
> 1) ?
729 &r
->sample_pattern_4x
: &r
->sample_pattern_1x
;
731 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6)) {
732 gen6_wa_pre_non_pipelined(r
);
733 gen6_wa_pre_3dstate_multisample(r
);
736 gen6_3DSTATE_MULTISAMPLE(r
->builder
,
737 vec
->fb
.num_samples
, pattern
,
738 vec
->rasterizer
->state
.half_pixel_center
);
740 gen6_3DSTATE_SAMPLE_MASK(r
->builder
,
741 (vec
->fb
.num_samples
> 1) ? vec
->sample_mask
: 0x1);
746 gen6_draw_wm_depth(struct ilo_render
*r
,
747 const struct ilo_state_vector
*vec
,
748 struct ilo_render_draw_session
*session
)
750 /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
751 if (DIRTY(FB
) || r
->batch_bo_changed
) {
752 const struct ilo_zs_surface
*zs
;
753 uint32_t clear_params
;
755 if (vec
->fb
.state
.zsbuf
) {
756 const struct ilo_surface_cso
*surface
=
757 (const struct ilo_surface_cso
*) vec
->fb
.state
.zsbuf
;
758 const struct ilo_texture_slice
*slice
=
759 ilo_texture_get_slice(ilo_texture(surface
->base
.texture
),
760 surface
->base
.u
.tex
.level
, surface
->base
.u
.tex
.first_layer
);
762 assert(!surface
->is_rt
);
765 clear_params
= slice
->clear_value
;
768 zs
= &vec
->fb
.null_zs
;
772 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6)) {
773 gen6_wa_pre_non_pipelined(r
);
774 gen6_wa_pre_depth(r
);
777 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
, zs
, false);
778 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
, zs
);
779 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
, zs
);
780 gen6_3DSTATE_CLEAR_PARAMS(r
->builder
, clear_params
);
785 gen6_draw_wm_raster(struct ilo_render
*r
,
786 const struct ilo_state_vector
*vec
,
787 struct ilo_render_draw_session
*session
)
789 /* 3DSTATE_POLY_STIPPLE_PATTERN and 3DSTATE_POLY_STIPPLE_OFFSET */
790 if ((DIRTY(RASTERIZER
) || DIRTY(POLY_STIPPLE
)) &&
791 vec
->rasterizer
->state
.poly_stipple_enable
) {
792 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
793 gen6_wa_pre_non_pipelined(r
);
795 gen6_3DSTATE_POLY_STIPPLE_PATTERN(r
->builder
,
798 gen6_3DSTATE_POLY_STIPPLE_OFFSET(r
->builder
, 0, 0);
801 /* 3DSTATE_LINE_STIPPLE */
802 if (DIRTY(RASTERIZER
) && vec
->rasterizer
->state
.line_stipple_enable
) {
803 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
804 gen6_wa_pre_non_pipelined(r
);
806 gen6_3DSTATE_LINE_STIPPLE(r
->builder
,
807 vec
->rasterizer
->state
.line_stipple_pattern
,
808 vec
->rasterizer
->state
.line_stipple_factor
+ 1);
811 /* 3DSTATE_AA_LINE_PARAMETERS */
812 if (DIRTY(RASTERIZER
) && vec
->rasterizer
->state
.line_smooth
) {
813 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
814 gen6_wa_pre_non_pipelined(r
);
816 gen6_3DSTATE_AA_LINE_PARAMETERS(r
->builder
);
823 ilo_render_emit_draw_commands_gen6(struct ilo_render
*render
,
824 const struct ilo_state_vector
*vec
,
825 struct ilo_render_draw_session
*session
)
827 ILO_DEV_ASSERT(render
->dev
, 6, 6);
830 * We try to keep the order of the commands match, as closely as possible,
831 * that of the classic i965 driver. It allows us to compare the command
834 gen6_draw_common_select(render
, vec
, session
);
835 gen6_draw_gs_svbi(render
, vec
, session
);
836 gen6_draw_common_sip(render
, vec
, session
);
837 gen6_draw_vf_statistics(render
, vec
, session
);
838 gen6_draw_common_base_address(render
, vec
, session
);
839 gen6_draw_common_pointers_1(render
, vec
, session
);
840 gen6_draw_common_urb(render
, vec
, session
);
841 gen6_draw_common_pointers_2(render
, vec
, session
);
842 gen6_draw_wm_multisample(render
, vec
, session
);
843 gen6_draw_vs(render
, vec
, session
);
844 gen6_draw_gs(render
, vec
, session
);
845 gen6_draw_clip(render
, vec
, session
);
846 gen6_draw_sf(render
, vec
, session
);
847 gen6_draw_wm(render
, vec
, session
);
848 gen6_draw_common_pointers_3(render
, vec
, session
);
849 gen6_draw_wm_depth(render
, vec
, session
);
850 gen6_draw_wm_raster(render
, vec
, session
);
851 gen6_draw_sf_rect(render
, vec
, session
);
852 gen6_draw_vf(render
, vec
, session
);
853 gen6_draw_vf_draw(render
, vec
, session
);
857 gen6_rectlist_vs_to_sf(struct ilo_render
*r
,
858 const struct ilo_blitter
*blitter
)
860 gen6_3DSTATE_CONSTANT_VS(r
->builder
, NULL
, NULL
, 0);
861 gen6_disable_3DSTATE_VS(r
->builder
);
863 gen6_wa_post_3dstate_constant_vs(r
);
865 gen6_3DSTATE_CONSTANT_GS(r
->builder
, NULL
, NULL
, 0);
866 gen6_disable_3DSTATE_GS(r
->builder
);
868 gen6_disable_3DSTATE_CLIP(r
->builder
);
869 gen6_3DSTATE_SF(r
->builder
, NULL
, NULL
, blitter
->fb
.num_samples
);
873 gen6_rectlist_wm(struct ilo_render
*r
,
874 const struct ilo_blitter
*blitter
)
878 switch (blitter
->op
) {
879 case ILO_BLITTER_RECTLIST_CLEAR_ZS
:
880 hiz_op
= GEN6_WM_DW4_DEPTH_CLEAR
;
882 case ILO_BLITTER_RECTLIST_RESOLVE_Z
:
883 hiz_op
= GEN6_WM_DW4_DEPTH_RESOLVE
;
885 case ILO_BLITTER_RECTLIST_RESOLVE_HIZ
:
886 hiz_op
= GEN6_WM_DW4_HIZ_RESOLVE
;
893 gen6_3DSTATE_CONSTANT_PS(r
->builder
, NULL
, NULL
, 0);
895 gen6_wa_pre_3dstate_wm_max_threads(r
);
896 gen6_hiz_3DSTATE_WM(r
->builder
, hiz_op
);
900 gen6_rectlist_wm_depth(struct ilo_render
*r
,
901 const struct ilo_blitter
*blitter
)
903 gen6_wa_pre_depth(r
);
905 if (blitter
->uses
& (ILO_BLITTER_USE_FB_DEPTH
|
906 ILO_BLITTER_USE_FB_STENCIL
)) {
907 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
,
908 &blitter
->fb
.dst
.u
.zs
, true);
911 if (blitter
->uses
& ILO_BLITTER_USE_FB_DEPTH
) {
912 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
,
913 &blitter
->fb
.dst
.u
.zs
);
916 if (blitter
->uses
& ILO_BLITTER_USE_FB_STENCIL
) {
917 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
,
918 &blitter
->fb
.dst
.u
.zs
);
921 gen6_3DSTATE_CLEAR_PARAMS(r
->builder
,
922 blitter
->depth_clear_value
);
926 gen6_rectlist_wm_multisample(struct ilo_render
*r
,
927 const struct ilo_blitter
*blitter
)
929 const uint32_t *pattern
= (blitter
->fb
.num_samples
> 1) ?
930 &r
->sample_pattern_4x
: &r
->sample_pattern_1x
;
932 gen6_wa_pre_3dstate_multisample(r
);
934 gen6_3DSTATE_MULTISAMPLE(r
->builder
, blitter
->fb
.num_samples
,
937 gen6_3DSTATE_SAMPLE_MASK(r
->builder
,
938 (1 << blitter
->fb
.num_samples
) - 1);
942 ilo_render_get_rectlist_commands_len_gen6(const struct ilo_render
*render
,
943 const struct ilo_blitter
*blitter
)
945 ILO_DEV_ASSERT(render
->dev
, 6, 7.5);
951 ilo_render_emit_rectlist_commands_gen6(struct ilo_render
*r
,
952 const struct ilo_blitter
*blitter
,
953 const struct ilo_render_rectlist_session
*session
)
955 ILO_DEV_ASSERT(r
->dev
, 6, 6);
957 gen6_wa_pre_non_pipelined(r
);
959 gen6_rectlist_wm_multisample(r
, blitter
);
961 gen6_state_base_address(r
->builder
, true);
963 gen6_user_3DSTATE_VERTEX_BUFFERS(r
->builder
,
964 session
->vb_start
, session
->vb_end
,
965 sizeof(blitter
->vertices
[0]));
967 gen6_3DSTATE_VERTEX_ELEMENTS(r
->builder
, &blitter
->ve
);
969 gen6_3DSTATE_URB(r
->builder
, r
->dev
->urb_size
, 0,
970 (blitter
->ve
.count
+ blitter
->ve
.prepend_nosrc_cso
) * 4 * sizeof(float),
973 /* 3DSTATE_URB workaround */
974 if (r
->state
.gs
.active
) {
975 ilo_render_emit_flush(r
);
976 r
->state
.gs
.active
= false;
980 (ILO_BLITTER_USE_DSA
| ILO_BLITTER_USE_CC
)) {
981 gen6_3DSTATE_CC_STATE_POINTERS(r
->builder
, 0,
982 r
->state
.DEPTH_STENCIL_STATE
, r
->state
.COLOR_CALC_STATE
);
985 gen6_rectlist_vs_to_sf(r
, blitter
);
986 gen6_rectlist_wm(r
, blitter
);
988 if (blitter
->uses
& ILO_BLITTER_USE_VIEWPORT
) {
989 gen6_3DSTATE_VIEWPORT_STATE_POINTERS(r
->builder
,
990 0, 0, r
->state
.CC_VIEWPORT
);
993 gen6_rectlist_wm_depth(r
, blitter
);
995 gen6_3DSTATE_DRAWING_RECTANGLE(r
->builder
, 0, 0,
996 blitter
->fb
.width
, blitter
->fb
.height
);
998 gen6_3DPRIMITIVE(r
->builder
, &blitter
->draw
, NULL
);
1002 ilo_render_get_draw_commands_len_gen6(const struct ilo_render
*render
,
1003 const struct ilo_state_vector
*vec
)
1007 ILO_DEV_ASSERT(render
->dev
, 6, 6);
1010 len
+= GEN6_3DSTATE_CONSTANT_ANY__SIZE
* 3;
1011 len
+= GEN6_3DSTATE_GS_SVB_INDEX__SIZE
* 4;
1012 len
+= GEN6_PIPE_CONTROL__SIZE
* 5;
1015 GEN6_STATE_BASE_ADDRESS__SIZE
+
1016 GEN6_STATE_SIP__SIZE
+
1017 GEN6_3DSTATE_VF_STATISTICS__SIZE
+
1018 GEN6_PIPELINE_SELECT__SIZE
+
1019 GEN6_3DSTATE_BINDING_TABLE_POINTERS__SIZE
+
1020 GEN6_3DSTATE_SAMPLER_STATE_POINTERS__SIZE
+
1021 GEN6_3DSTATE_URB__SIZE
+
1022 GEN6_3DSTATE_VERTEX_BUFFERS__SIZE
+
1023 GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE
+
1024 GEN6_3DSTATE_INDEX_BUFFER__SIZE
+
1025 GEN6_3DSTATE_VIEWPORT_STATE_POINTERS__SIZE
+
1026 GEN6_3DSTATE_CC_STATE_POINTERS__SIZE
+
1027 GEN6_3DSTATE_SCISSOR_STATE_POINTERS__SIZE
+
1028 GEN6_3DSTATE_VS__SIZE
+
1029 GEN6_3DSTATE_GS__SIZE
+
1030 GEN6_3DSTATE_CLIP__SIZE
+
1031 GEN6_3DSTATE_SF__SIZE
+
1032 GEN6_3DSTATE_WM__SIZE
+
1033 GEN6_3DSTATE_SAMPLE_MASK__SIZE
+
1034 GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE
+
1035 GEN6_3DSTATE_DEPTH_BUFFER__SIZE
+
1036 GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE
+
1037 GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE
+
1038 GEN6_3DSTATE_LINE_STIPPLE__SIZE
+
1039 GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE
+
1040 GEN6_3DSTATE_MULTISAMPLE__SIZE
+
1041 GEN6_3DSTATE_STENCIL_BUFFER__SIZE
+
1042 GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE
+
1043 GEN6_3DSTATE_CLEAR_PARAMS__SIZE
+
1044 GEN6_3DPRIMITIVE__SIZE
;