2 * Mesa 3-D graphics library
4 * Copyright (C) 2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "genhw/genhw.h"
29 #include "core/ilo_builder_3d.h"
30 #include "core/ilo_builder_mi.h"
31 #include "core/ilo_builder_render.h"
32 #include "util/u_dual_blend.h"
33 #include "util/u_prim.h"
35 #include "ilo_blitter.h"
36 #include "ilo_query.h"
37 #include "ilo_shader.h"
38 #include "ilo_state.h"
39 #include "ilo_render_gen.h"
42 * This should be called before PIPE_CONTROL.
45 gen6_wa_pre_pipe_control(struct ilo_render
*r
, uint32_t dw1
)
48 * From the Sandy Bridge PRM, volume 2 part 1, page 60:
50 * "Pipe-control with CS-stall bit set must be sent BEFORE the
51 * pipe-control with a post-sync op and no write-cache flushes."
53 * This WA may also be triggered indirectly by the other two WAs on the
56 * "Before any depth stall flush (including those produced by
57 * non-pipelined state commands), software needs to first send a
58 * PIPE_CONTROL with no bits set except Post-Sync Operation != 0."
60 * "Before a PIPE_CONTROL with Write Cache Flush Enable =1, a
61 * PIPE_CONTROL with any non-zero post-sync-op is required."
63 const bool direct_wa_cond
= (dw1
& GEN6_PIPE_CONTROL_WRITE__MASK
) &&
64 !(dw1
& GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH
);
65 const bool indirect_wa_cond
= (dw1
& GEN6_PIPE_CONTROL_DEPTH_STALL
) |
66 (dw1
& GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH
);
68 ILO_DEV_ASSERT(r
->dev
, 6, 6);
70 if (!direct_wa_cond
&& !indirect_wa_cond
)
73 if (!(r
->state
.current_pipe_control_dw1
& GEN6_PIPE_CONTROL_CS_STALL
)) {
75 * From the Sandy Bridge PRM, volume 2 part 1, page 73:
77 * "1 of the following must also be set (when CS stall is set):
79 * - Depth Cache Flush Enable ([0] of DW1)
80 * - Stall at Pixel Scoreboard ([1] of DW1)
81 * - Depth Stall ([13] of DW1)
82 * - Post-Sync Operation ([13] of DW1)
83 * - Render Target Cache Flush Enable ([12] of DW1)
84 * - Notify Enable ([8] of DW1)"
86 * Because of the WAs above, we have to pick Stall at Pixel Scoreboard.
88 const uint32_t direct_wa
= GEN6_PIPE_CONTROL_CS_STALL
|
89 GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL
;
91 ilo_render_pipe_control(r
, direct_wa
);
94 if (indirect_wa_cond
&&
95 !(r
->state
.current_pipe_control_dw1
& GEN6_PIPE_CONTROL_WRITE__MASK
)) {
96 const uint32_t indirect_wa
= GEN6_PIPE_CONTROL_WRITE_IMM
;
98 ilo_render_pipe_control(r
, indirect_wa
);
103 * This should be called before any non-pipelined state command.
106 gen6_wa_pre_non_pipelined(struct ilo_render
*r
)
108 ILO_DEV_ASSERT(r
->dev
, 6, 6);
110 /* non-pipelined state commands produce depth stall */
111 gen6_wa_pre_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
115 gen6_wa_post_3dstate_urb_no_gs(struct ilo_render
*r
)
118 * From the Sandy Bridge PRM, volume 2 part 1, page 27:
120 * "Because of a urb corruption caused by allocating a previous
121 * gsunit's urb entry to vsunit software is required to send a
122 * "GS NULL Fence" (Send URB fence with VS URB size == 1 and GS URB
123 * size == 0) plus a dummy DRAW call before any case where VS will
124 * be taking over GS URB space."
126 const uint32_t dw1
= GEN6_PIPE_CONTROL_CS_STALL
;
128 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
129 gen6_wa_pre_pipe_control(r
, dw1
);
130 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
131 ilo_render_pipe_control(r
, dw1
);
135 gen6_wa_post_3dstate_constant_vs(struct ilo_render
*r
)
138 * According to upload_vs_state() of the classic driver, we need to emit a
139 * PIPE_CONTROL after 3DSTATE_CONSTANT_VS, otherwise the command is kept
140 * being buffered by VS FF, to the point that the FF dies.
142 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_STALL
|
143 GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
|
144 GEN6_PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
146 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
147 gen6_wa_pre_pipe_control(r
, dw1
);
148 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
149 ilo_render_pipe_control(r
, dw1
);
153 gen6_wa_pre_3dstate_vs_toggle(struct ilo_render
*r
)
156 * The classic driver has this undocumented WA:
158 * From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
159 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
161 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
162 * command that causes the VS Function Enable to toggle. Pipeline
163 * flush can be executed by sending a PIPE_CONTROL command with CS
164 * stall bit set and a post sync operation.
166 const uint32_t dw1
= GEN6_PIPE_CONTROL_WRITE_IMM
|
167 GEN6_PIPE_CONTROL_CS_STALL
;
169 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
170 gen6_wa_pre_pipe_control(r
, dw1
);
171 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
172 ilo_render_pipe_control(r
, dw1
);
176 gen6_wa_pre_3dstate_wm_max_threads(struct ilo_render
*r
)
179 * From the Sandy Bridge PRM, volume 2 part 1, page 274:
181 * "A PIPE_CONTROL command, with only the Stall At Pixel Scoreboard
182 * field set (DW1 Bit 1), must be issued prior to any change to the
183 * value in this field (Maximum Number of Threads in 3DSTATE_WM)"
185 const uint32_t dw1
= GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL
;
187 ILO_DEV_ASSERT(r
->dev
, 6, 6);
189 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
190 gen6_wa_pre_pipe_control(r
, dw1
);
191 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
192 ilo_render_pipe_control(r
, dw1
);
196 gen6_wa_pre_3dstate_multisample(struct ilo_render
*r
)
199 * From the Sandy Bridge PRM, volume 2 part 1, page 305:
201 * "Driver must guarentee that all the caches in the depth pipe are
202 * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
203 * requires driver to send a PIPE_CONTROL with a CS stall along with a
204 * Depth Flush prior to this command."
206 const uint32_t dw1
= GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
207 GEN6_PIPE_CONTROL_CS_STALL
;
209 ILO_DEV_ASSERT(r
->dev
, 6, 6);
211 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
212 gen6_wa_pre_pipe_control(r
, dw1
);
213 if ((r
->state
.current_pipe_control_dw1
& dw1
) != dw1
)
214 ilo_render_pipe_control(r
, dw1
);
218 gen6_wa_pre_depth(struct ilo_render
*r
)
220 ILO_DEV_ASSERT(r
->dev
, 6, 6);
223 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
225 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
226 * any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
227 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
228 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
229 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
230 * Depth Flush Bit set, followed by another pipelined depth stall
231 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
232 * guarantee that the pipeline from WM onwards is already flushed
233 * (e.g., via a preceding MI_FLUSH)."
235 * According to the classic driver, it also applies for GEN6.
237 gen6_wa_pre_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
|
238 GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
240 ilo_render_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
241 ilo_render_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
242 ilo_render_pipe_control(r
, GEN6_PIPE_CONTROL_DEPTH_STALL
);
245 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
248 gen6_draw_common_select(struct ilo_render
*r
,
249 const struct ilo_state_vector
*vec
,
250 struct ilo_render_draw_session
*session
)
252 /* PIPELINE_SELECT */
253 if (r
->hw_ctx_changed
) {
254 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
255 gen6_wa_pre_non_pipelined(r
);
257 gen6_PIPELINE_SELECT(r
->builder
, 0x0);
262 gen6_draw_common_sip(struct ilo_render
*r
,
263 const struct ilo_state_vector
*vec
,
264 struct ilo_render_draw_session
*session
)
267 if (r
->hw_ctx_changed
) {
268 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
269 gen6_wa_pre_non_pipelined(r
);
271 gen6_STATE_SIP(r
->builder
, 0);
276 gen6_draw_common_base_address(struct ilo_render
*r
,
277 const struct ilo_state_vector
*vec
,
278 struct ilo_render_draw_session
*session
)
280 /* STATE_BASE_ADDRESS */
281 if (r
->state_bo_changed
|| r
->instruction_bo_changed
||
282 r
->batch_bo_changed
) {
283 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
284 gen6_wa_pre_non_pipelined(r
);
286 if (ilo_dev_gen(r
->dev
) >= ILO_GEN(8))
287 gen8_state_base_address(r
->builder
, r
->hw_ctx_changed
);
289 gen6_state_base_address(r
->builder
, r
->hw_ctx_changed
);
292 * From the Sandy Bridge PRM, volume 1 part 1, page 28:
294 * "The following commands must be reissued following any change to
295 * the base addresses:
297 * * 3DSTATE_BINDING_TABLE_POINTERS
298 * * 3DSTATE_SAMPLER_STATE_POINTERS
299 * * 3DSTATE_VIEWPORT_STATE_POINTERS
300 * * 3DSTATE_CC_POINTERS
301 * * MEDIA_STATE_POINTERS"
303 * 3DSTATE_SCISSOR_STATE_POINTERS is not on the list, but it is
304 * reasonable to also reissue the command. Same to PCB.
306 session
->viewport_changed
= true;
308 session
->scissor_changed
= true;
310 session
->blend_changed
= true;
311 session
->dsa_changed
= true;
312 session
->cc_changed
= true;
314 session
->sampler_vs_changed
= true;
315 session
->sampler_gs_changed
= true;
316 session
->sampler_fs_changed
= true;
318 session
->pcb_vs_changed
= true;
319 session
->pcb_gs_changed
= true;
320 session
->pcb_fs_changed
= true;
322 session
->binding_table_vs_changed
= true;
323 session
->binding_table_gs_changed
= true;
324 session
->binding_table_fs_changed
= true;
329 gen6_draw_common_urb(struct ilo_render
*r
,
330 const struct ilo_state_vector
*vec
,
331 struct ilo_render_draw_session
*session
)
334 if (DIRTY(VE
) || DIRTY(VS
) || DIRTY(GS
)) {
335 const bool gs_active
= (vec
->gs
|| (vec
->vs
&&
336 ilo_shader_get_kernel_param(vec
->vs
, ILO_KERNEL_VS_GEN6_SO
)));
337 int vs_entry_size
, gs_entry_size
;
338 int vs_total_size
, gs_total_size
;
340 vs_entry_size
= (vec
->vs
) ?
341 ilo_shader_get_kernel_param(vec
->vs
, ILO_KERNEL_OUTPUT_COUNT
) : 0;
344 * As indicated by 2e712e41db0c0676e9f30fc73172c0e8de8d84d4, VF and VS
345 * share VUE handles. The VUE allocation size must be large enough to
346 * store either VF outputs (number of VERTEX_ELEMENTs) and VS outputs.
348 * I am not sure if the PRM explicitly states that VF and VS share VUE
349 * handles. But here is a citation that implies so:
351 * From the Sandy Bridge PRM, volume 2 part 1, page 44:
353 * "Once a FF stage that spawn threads has sufficient input to
354 * initiate a thread, it must guarantee that it is safe to request
355 * the thread initiation. For all these FF stages, this check is
358 * - The availability of output URB entries:
359 * - VS: As the input URB entries are overwritten with the
360 * VS-generated output data, output URB availability isn't a
363 if (vs_entry_size
< vec
->ve
->count
+ vec
->ve
->prepend_nosrc_cso
)
364 vs_entry_size
= vec
->ve
->count
+ vec
->ve
->prepend_nosrc_cso
;
366 gs_entry_size
= (vec
->gs
) ?
367 ilo_shader_get_kernel_param(vec
->gs
, ILO_KERNEL_OUTPUT_COUNT
) :
368 (gs_active
) ? vs_entry_size
: 0;
371 vs_entry_size
*= sizeof(float) * 4;
372 gs_entry_size
*= sizeof(float) * 4;
373 vs_total_size
= r
->dev
->urb_size
;
377 gs_total_size
= vs_total_size
;
383 gen6_3DSTATE_URB(r
->builder
, vs_total_size
, gs_total_size
,
384 vs_entry_size
, gs_entry_size
);
386 if (r
->state
.gs
.active
&& !gs_active
)
387 gen6_wa_post_3dstate_urb_no_gs(r
);
389 r
->state
.gs
.active
= gs_active
;
394 gen6_draw_common_pointers_1(struct ilo_render
*r
,
395 const struct ilo_state_vector
*vec
,
396 struct ilo_render_draw_session
*session
)
398 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
399 if (session
->viewport_changed
) {
400 gen6_3DSTATE_VIEWPORT_STATE_POINTERS(r
->builder
,
401 r
->state
.CLIP_VIEWPORT
,
402 r
->state
.SF_VIEWPORT
,
403 r
->state
.CC_VIEWPORT
);
408 gen6_draw_common_pointers_2(struct ilo_render
*r
,
409 const struct ilo_state_vector
*vec
,
410 struct ilo_render_draw_session
*session
)
412 /* 3DSTATE_CC_STATE_POINTERS */
413 if (session
->blend_changed
||
414 session
->dsa_changed
||
415 session
->cc_changed
) {
416 gen6_3DSTATE_CC_STATE_POINTERS(r
->builder
,
417 r
->state
.BLEND_STATE
,
418 r
->state
.DEPTH_STENCIL_STATE
,
419 r
->state
.COLOR_CALC_STATE
);
422 /* 3DSTATE_SAMPLER_STATE_POINTERS */
423 if (session
->sampler_vs_changed
||
424 session
->sampler_gs_changed
||
425 session
->sampler_fs_changed
) {
426 gen6_3DSTATE_SAMPLER_STATE_POINTERS(r
->builder
,
427 r
->state
.vs
.SAMPLER_STATE
,
429 r
->state
.wm
.SAMPLER_STATE
);
434 gen6_draw_common_pointers_3(struct ilo_render
*r
,
435 const struct ilo_state_vector
*vec
,
436 struct ilo_render_draw_session
*session
)
438 /* 3DSTATE_SCISSOR_STATE_POINTERS */
439 if (session
->scissor_changed
) {
440 gen6_3DSTATE_SCISSOR_STATE_POINTERS(r
->builder
,
441 r
->state
.SCISSOR_RECT
);
444 /* 3DSTATE_BINDING_TABLE_POINTERS */
445 if (session
->binding_table_vs_changed
||
446 session
->binding_table_gs_changed
||
447 session
->binding_table_fs_changed
) {
448 gen6_3DSTATE_BINDING_TABLE_POINTERS(r
->builder
,
449 r
->state
.vs
.BINDING_TABLE_STATE
,
450 r
->state
.gs
.BINDING_TABLE_STATE
,
451 r
->state
.wm
.BINDING_TABLE_STATE
);
456 gen6_draw_vf(struct ilo_render
*r
,
457 const struct ilo_state_vector
*vec
,
458 struct ilo_render_draw_session
*session
)
460 if (ilo_dev_gen(r
->dev
) >= ILO_GEN(7.5)) {
461 /* 3DSTATE_INDEX_BUFFER */
462 if (DIRTY(IB
) || r
->batch_bo_changed
) {
463 gen6_3DSTATE_INDEX_BUFFER(r
->builder
,
468 if (session
->primitive_restart_changed
) {
469 gen75_3DSTATE_VF(r
->builder
, vec
->draw
->primitive_restart
,
470 vec
->draw
->restart_index
);
474 /* 3DSTATE_INDEX_BUFFER */
475 if (DIRTY(IB
) || session
->primitive_restart_changed
||
476 r
->batch_bo_changed
) {
477 gen6_3DSTATE_INDEX_BUFFER(r
->builder
,
478 &vec
->ib
, vec
->draw
->primitive_restart
);
482 /* 3DSTATE_VERTEX_BUFFERS */
483 if (DIRTY(VB
) || DIRTY(VE
) || r
->batch_bo_changed
)
484 gen6_3DSTATE_VERTEX_BUFFERS(r
->builder
, vec
->ve
, &vec
->vb
);
486 /* 3DSTATE_VERTEX_ELEMENTS */
488 gen6_3DSTATE_VERTEX_ELEMENTS(r
->builder
, vec
->ve
);
492 gen6_draw_vf_statistics(struct ilo_render
*r
,
493 const struct ilo_state_vector
*vec
,
494 struct ilo_render_draw_session
*session
)
496 /* 3DSTATE_VF_STATISTICS */
497 if (r
->hw_ctx_changed
)
498 gen6_3DSTATE_VF_STATISTICS(r
->builder
, false);
502 gen6_draw_vs(struct ilo_render
*r
,
503 const struct ilo_state_vector
*vec
,
504 struct ilo_render_draw_session
*session
)
506 /* 3DSTATE_CONSTANT_VS */
507 if (session
->pcb_vs_changed
) {
508 gen6_3DSTATE_CONSTANT_VS(r
->builder
,
509 &r
->state
.vs
.PUSH_CONSTANT_BUFFER
,
510 &r
->state
.vs
.PUSH_CONSTANT_BUFFER_size
,
513 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
514 gen6_wa_post_3dstate_constant_vs(r
);
518 if (DIRTY(VS
) || r
->instruction_bo_changed
) {
519 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
520 gen6_wa_pre_3dstate_vs_toggle(r
);
522 gen6_3DSTATE_VS(r
->builder
, vec
->vs
);
527 gen6_draw_gs(struct ilo_render
*r
,
528 const struct ilo_state_vector
*vec
,
529 struct ilo_render_draw_session
*session
)
531 /* 3DSTATE_CONSTANT_GS */
532 if (session
->pcb_gs_changed
)
533 gen6_3DSTATE_CONSTANT_GS(r
->builder
, NULL
, NULL
, 0);
536 if (DIRTY(GS
) || DIRTY(VS
) ||
537 session
->prim_changed
|| r
->instruction_bo_changed
) {
539 gen6_3DSTATE_GS(r
->builder
, vec
->gs
);
540 } else if (vec
->vs
&&
541 ilo_shader_get_kernel_param(vec
->vs
, ILO_KERNEL_VS_GEN6_SO
)) {
542 const int verts_per_prim
= u_vertices_per_prim(session
->reduced_prim
);
543 gen6_so_3DSTATE_GS(r
->builder
, vec
->vs
, verts_per_prim
);
545 gen6_disable_3DSTATE_GS(r
->builder
);
551 gen6_draw_update_max_svbi(struct ilo_render
*r
,
552 const struct ilo_state_vector
*vec
,
553 struct ilo_render_draw_session
*session
)
555 if (DIRTY(VS
) || DIRTY(GS
) || DIRTY(SO
)) {
556 const struct pipe_stream_output_info
*so_info
=
557 (vec
->gs
) ? ilo_shader_get_kernel_so_info(vec
->gs
) :
558 (vec
->vs
) ? ilo_shader_get_kernel_so_info(vec
->vs
) : NULL
;
559 unsigned max_svbi
= 0xffffffff;
562 for (i
= 0; i
< so_info
->num_outputs
; i
++) {
563 const int output_buffer
= so_info
->output
[i
].output_buffer
;
564 const struct pipe_stream_output_target
*so
=
565 vec
->so
.states
[output_buffer
];
566 const int struct_size
= so_info
->stride
[output_buffer
] * 4;
567 const int elem_size
= so_info
->output
[i
].num_components
* 4;
575 buf_size
= so
->buffer_size
- so_info
->output
[i
].dst_offset
* 4;
577 count
= buf_size
/ struct_size
;
578 if (buf_size
% struct_size
>= elem_size
)
581 if (count
< max_svbi
)
585 if (r
->state
.so_max_vertices
!= max_svbi
) {
586 r
->state
.so_max_vertices
= max_svbi
;
595 gen6_draw_gs_svbi(struct ilo_render
*r
,
596 const struct ilo_state_vector
*vec
,
597 struct ilo_render_draw_session
*session
)
599 const bool emit
= gen6_draw_update_max_svbi(r
, vec
, session
);
601 /* 3DSTATE_GS_SVB_INDEX */
603 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
604 gen6_wa_pre_non_pipelined(r
);
606 gen6_3DSTATE_GS_SVB_INDEX(r
->builder
,
607 0, 0, r
->state
.so_max_vertices
,
610 if (r
->hw_ctx_changed
) {
614 * From the Sandy Bridge PRM, volume 2 part 1, page 148:
616 * "If a buffer is not enabled then the SVBI must be set to 0x0
617 * in order to not cause overflow in that SVBI."
619 * "If a buffer is not enabled then the MaxSVBI must be set to
620 * 0xFFFFFFFF in order to not cause overflow in that SVBI."
622 for (i
= 1; i
< 4; i
++) {
623 gen6_3DSTATE_GS_SVB_INDEX(r
->builder
,
624 i
, 0, 0xffffffff, false);
631 gen6_draw_clip(struct ilo_render
*r
,
632 const struct ilo_state_vector
*vec
,
633 struct ilo_render_draw_session
*session
)
636 if (DIRTY(RASTERIZER
) || DIRTY(FS
) || DIRTY(VIEWPORT
) || DIRTY(FB
)) {
637 bool enable_guardband
= true;
641 * Gen8+ has viewport extent test. Guard band test can be enabled on
642 * prior Gens only when the viewport is larger than the framebuffer,
643 * unless we emulate viewport extent test on them.
645 if (ilo_dev_gen(r
->dev
) < ILO_GEN(8)) {
646 for (i
= 0; i
< vec
->viewport
.count
; i
++) {
647 const struct ilo_viewport_cso
*vp
= &vec
->viewport
.cso
[i
];
649 if (vp
->min_x
> 0.0f
|| vp
->max_x
< vec
->fb
.state
.width
||
650 vp
->min_y
> 0.0f
|| vp
->max_y
< vec
->fb
.state
.height
) {
651 enable_guardband
= false;
657 gen6_3DSTATE_CLIP(r
->builder
, vec
->rasterizer
,
658 vec
->fs
, enable_guardband
, 1);
663 gen6_draw_sf(struct ilo_render
*r
,
664 const struct ilo_state_vector
*vec
,
665 struct ilo_render_draw_session
*session
)
668 if (DIRTY(RASTERIZER
) || DIRTY(FS
) || DIRTY(FB
)) {
669 gen6_3DSTATE_SF(r
->builder
, vec
->rasterizer
, vec
->fs
,
670 vec
->fb
.num_samples
);
675 gen6_draw_sf_rect(struct ilo_render
*r
,
676 const struct ilo_state_vector
*vec
,
677 struct ilo_render_draw_session
*session
)
679 /* 3DSTATE_DRAWING_RECTANGLE */
681 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
682 gen6_wa_pre_non_pipelined(r
);
684 gen6_3DSTATE_DRAWING_RECTANGLE(r
->builder
, 0, 0,
685 vec
->fb
.state
.width
, vec
->fb
.state
.height
);
690 gen6_draw_wm(struct ilo_render
*r
,
691 const struct ilo_state_vector
*vec
,
692 struct ilo_render_draw_session
*session
)
694 /* 3DSTATE_CONSTANT_PS */
695 if (session
->pcb_fs_changed
) {
696 gen6_3DSTATE_CONSTANT_PS(r
->builder
,
697 &r
->state
.wm
.PUSH_CONSTANT_BUFFER
,
698 &r
->state
.wm
.PUSH_CONSTANT_BUFFER_size
,
703 if (DIRTY(FS
) || DIRTY(BLEND
) || DIRTY(DSA
) ||
704 DIRTY(RASTERIZER
) || r
->instruction_bo_changed
) {
705 const bool dual_blend
= vec
->blend
->dual_blend
;
706 const bool cc_may_kill
= (vec
->dsa
->dw_blend_alpha
||
707 vec
->blend
->alpha_to_coverage
);
709 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6) && r
->hw_ctx_changed
)
710 gen6_wa_pre_3dstate_wm_max_threads(r
);
712 gen6_3DSTATE_WM(r
->builder
, vec
->fs
,
713 vec
->rasterizer
, dual_blend
, cc_may_kill
);
718 gen6_draw_wm_multisample(struct ilo_render
*r
,
719 const struct ilo_state_vector
*vec
,
720 struct ilo_render_draw_session
*session
)
722 /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
723 if (DIRTY(SAMPLE_MASK
) || DIRTY(FB
)) {
724 const uint32_t *pattern
;
726 pattern
= (vec
->fb
.num_samples
> 1) ?
727 &r
->sample_pattern_4x
: &r
->sample_pattern_1x
;
729 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6)) {
730 gen6_wa_pre_non_pipelined(r
);
731 gen6_wa_pre_3dstate_multisample(r
);
734 gen6_3DSTATE_MULTISAMPLE(r
->builder
,
735 vec
->fb
.num_samples
, pattern
,
736 vec
->rasterizer
->state
.half_pixel_center
);
738 gen6_3DSTATE_SAMPLE_MASK(r
->builder
,
739 (vec
->fb
.num_samples
> 1) ? vec
->sample_mask
: 0x1);
744 gen6_draw_wm_depth(struct ilo_render
*r
,
745 const struct ilo_state_vector
*vec
,
746 struct ilo_render_draw_session
*session
)
748 /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
749 if (DIRTY(FB
) || r
->batch_bo_changed
) {
750 const struct ilo_state_zs
*zs
;
751 uint32_t clear_params
;
753 if (vec
->fb
.state
.zsbuf
) {
754 const struct ilo_surface_cso
*surface
=
755 (const struct ilo_surface_cso
*) vec
->fb
.state
.zsbuf
;
756 const struct ilo_texture_slice
*slice
=
757 ilo_texture_get_slice(ilo_texture(surface
->base
.texture
),
758 surface
->base
.u
.tex
.level
, surface
->base
.u
.tex
.first_layer
);
760 assert(!surface
->is_rt
);
763 clear_params
= slice
->clear_value
;
766 zs
= &vec
->fb
.null_zs
;
770 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6)) {
771 gen6_wa_pre_non_pipelined(r
);
772 gen6_wa_pre_depth(r
);
775 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
, zs
);
776 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
, zs
);
777 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
, zs
);
778 gen6_3DSTATE_CLEAR_PARAMS(r
->builder
, clear_params
);
783 gen6_draw_wm_raster(struct ilo_render
*r
,
784 const struct ilo_state_vector
*vec
,
785 struct ilo_render_draw_session
*session
)
787 /* 3DSTATE_POLY_STIPPLE_PATTERN and 3DSTATE_POLY_STIPPLE_OFFSET */
788 if ((DIRTY(RASTERIZER
) || DIRTY(POLY_STIPPLE
)) &&
789 vec
->rasterizer
->state
.poly_stipple_enable
) {
790 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
791 gen6_wa_pre_non_pipelined(r
);
793 gen6_3DSTATE_POLY_STIPPLE_PATTERN(r
->builder
,
796 gen6_3DSTATE_POLY_STIPPLE_OFFSET(r
->builder
, 0, 0);
799 /* 3DSTATE_LINE_STIPPLE */
800 if (DIRTY(RASTERIZER
) && vec
->rasterizer
->state
.line_stipple_enable
) {
801 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
802 gen6_wa_pre_non_pipelined(r
);
804 gen6_3DSTATE_LINE_STIPPLE(r
->builder
,
805 vec
->rasterizer
->state
.line_stipple_pattern
,
806 vec
->rasterizer
->state
.line_stipple_factor
+ 1);
809 /* 3DSTATE_AA_LINE_PARAMETERS */
810 if (DIRTY(RASTERIZER
) && vec
->rasterizer
->state
.line_smooth
) {
811 if (ilo_dev_gen(r
->dev
) == ILO_GEN(6))
812 gen6_wa_pre_non_pipelined(r
);
814 gen6_3DSTATE_AA_LINE_PARAMETERS(r
->builder
);
821 ilo_render_emit_draw_commands_gen6(struct ilo_render
*render
,
822 const struct ilo_state_vector
*vec
,
823 struct ilo_render_draw_session
*session
)
825 ILO_DEV_ASSERT(render
->dev
, 6, 6);
828 * We try to keep the order of the commands match, as closely as possible,
829 * that of the classic i965 driver. It allows us to compare the command
832 gen6_draw_common_select(render
, vec
, session
);
833 gen6_draw_gs_svbi(render
, vec
, session
);
834 gen6_draw_common_sip(render
, vec
, session
);
835 gen6_draw_vf_statistics(render
, vec
, session
);
836 gen6_draw_common_base_address(render
, vec
, session
);
837 gen6_draw_common_pointers_1(render
, vec
, session
);
838 gen6_draw_common_urb(render
, vec
, session
);
839 gen6_draw_common_pointers_2(render
, vec
, session
);
840 gen6_draw_wm_multisample(render
, vec
, session
);
841 gen6_draw_vs(render
, vec
, session
);
842 gen6_draw_gs(render
, vec
, session
);
843 gen6_draw_clip(render
, vec
, session
);
844 gen6_draw_sf(render
, vec
, session
);
845 gen6_draw_wm(render
, vec
, session
);
846 gen6_draw_common_pointers_3(render
, vec
, session
);
847 gen6_draw_wm_depth(render
, vec
, session
);
848 gen6_draw_wm_raster(render
, vec
, session
);
849 gen6_draw_sf_rect(render
, vec
, session
);
850 gen6_draw_vf(render
, vec
, session
);
852 ilo_render_3dprimitive(render
, vec
->draw
, &vec
->ib
);
856 gen6_rectlist_vs_to_sf(struct ilo_render
*r
,
857 const struct ilo_blitter
*blitter
)
859 gen6_3DSTATE_CONSTANT_VS(r
->builder
, NULL
, NULL
, 0);
860 gen6_wa_post_3dstate_constant_vs(r
);
862 gen6_wa_pre_3dstate_vs_toggle(r
);
863 gen6_disable_3DSTATE_VS(r
->builder
);
865 gen6_3DSTATE_CONSTANT_GS(r
->builder
, NULL
, NULL
, 0);
866 gen6_disable_3DSTATE_GS(r
->builder
);
868 gen6_disable_3DSTATE_CLIP(r
->builder
);
869 gen6_3DSTATE_SF(r
->builder
, NULL
, NULL
, blitter
->fb
.num_samples
);
873 gen6_rectlist_wm(struct ilo_render
*r
,
874 const struct ilo_blitter
*blitter
)
878 switch (blitter
->op
) {
879 case ILO_BLITTER_RECTLIST_CLEAR_ZS
:
880 hiz_op
= GEN6_WM_DW4_DEPTH_CLEAR
;
882 case ILO_BLITTER_RECTLIST_RESOLVE_Z
:
883 hiz_op
= GEN6_WM_DW4_DEPTH_RESOLVE
;
885 case ILO_BLITTER_RECTLIST_RESOLVE_HIZ
:
886 hiz_op
= GEN6_WM_DW4_HIZ_RESOLVE
;
893 gen6_3DSTATE_CONSTANT_PS(r
->builder
, NULL
, NULL
, 0);
895 gen6_wa_pre_3dstate_wm_max_threads(r
);
896 gen6_hiz_3DSTATE_WM(r
->builder
, hiz_op
);
900 gen6_rectlist_wm_depth(struct ilo_render
*r
,
901 const struct ilo_blitter
*blitter
)
903 gen6_wa_pre_depth(r
);
905 if (blitter
->uses
& (ILO_BLITTER_USE_FB_DEPTH
|
906 ILO_BLITTER_USE_FB_STENCIL
))
907 gen6_3DSTATE_DEPTH_BUFFER(r
->builder
, &blitter
->fb
.dst
.u
.zs
);
909 if (blitter
->uses
& ILO_BLITTER_USE_FB_DEPTH
) {
910 gen6_3DSTATE_HIER_DEPTH_BUFFER(r
->builder
,
911 &blitter
->fb
.dst
.u
.zs
);
914 if (blitter
->uses
& ILO_BLITTER_USE_FB_STENCIL
) {
915 gen6_3DSTATE_STENCIL_BUFFER(r
->builder
,
916 &blitter
->fb
.dst
.u
.zs
);
919 gen6_3DSTATE_CLEAR_PARAMS(r
->builder
,
920 blitter
->depth_clear_value
);
924 gen6_rectlist_wm_multisample(struct ilo_render
*r
,
925 const struct ilo_blitter
*blitter
)
927 const uint32_t *pattern
= (blitter
->fb
.num_samples
> 1) ?
928 &r
->sample_pattern_4x
: &r
->sample_pattern_1x
;
930 gen6_wa_pre_3dstate_multisample(r
);
932 gen6_3DSTATE_MULTISAMPLE(r
->builder
, blitter
->fb
.num_samples
,
935 gen6_3DSTATE_SAMPLE_MASK(r
->builder
,
936 (1 << blitter
->fb
.num_samples
) - 1);
940 ilo_render_get_rectlist_commands_len_gen6(const struct ilo_render
*render
,
941 const struct ilo_blitter
*blitter
)
943 ILO_DEV_ASSERT(render
->dev
, 6, 7.5);
949 ilo_render_emit_rectlist_commands_gen6(struct ilo_render
*r
,
950 const struct ilo_blitter
*blitter
,
951 const struct ilo_render_rectlist_session
*session
)
953 ILO_DEV_ASSERT(r
->dev
, 6, 6);
955 gen6_wa_pre_non_pipelined(r
);
957 gen6_rectlist_wm_multisample(r
, blitter
);
959 gen6_state_base_address(r
->builder
, true);
961 gen6_user_3DSTATE_VERTEX_BUFFERS(r
->builder
,
962 session
->vb_start
, session
->vb_end
,
963 sizeof(blitter
->vertices
[0]));
965 gen6_3DSTATE_VERTEX_ELEMENTS(r
->builder
, &blitter
->ve
);
967 gen6_3DSTATE_URB(r
->builder
, r
->dev
->urb_size
, 0,
968 (blitter
->ve
.count
+ blitter
->ve
.prepend_nosrc_cso
) * 4 * sizeof(float),
971 if (r
->state
.gs
.active
) {
972 gen6_wa_post_3dstate_urb_no_gs(r
);
973 r
->state
.gs
.active
= false;
977 (ILO_BLITTER_USE_DSA
| ILO_BLITTER_USE_CC
)) {
978 gen6_3DSTATE_CC_STATE_POINTERS(r
->builder
, 0,
979 r
->state
.DEPTH_STENCIL_STATE
, r
->state
.COLOR_CALC_STATE
);
982 gen6_rectlist_vs_to_sf(r
, blitter
);
983 gen6_rectlist_wm(r
, blitter
);
985 if (blitter
->uses
& ILO_BLITTER_USE_VIEWPORT
) {
986 gen6_3DSTATE_VIEWPORT_STATE_POINTERS(r
->builder
,
987 0, 0, r
->state
.CC_VIEWPORT
);
990 gen6_rectlist_wm_depth(r
, blitter
);
992 gen6_3DSTATE_DRAWING_RECTANGLE(r
->builder
, 0, 0,
993 blitter
->fb
.width
, blitter
->fb
.height
);
995 ilo_render_3dprimitive(r
, &blitter
->draw
, NULL
);
999 ilo_render_get_draw_commands_len_gen6(const struct ilo_render
*render
,
1000 const struct ilo_state_vector
*vec
)
1004 ILO_DEV_ASSERT(render
->dev
, 6, 6);
1007 len
+= GEN6_3DSTATE_CONSTANT_ANY__SIZE
* 3;
1008 len
+= GEN6_3DSTATE_GS_SVB_INDEX__SIZE
* 4;
1009 len
+= GEN6_PIPE_CONTROL__SIZE
* 5;
1012 GEN6_STATE_BASE_ADDRESS__SIZE
+
1013 GEN6_STATE_SIP__SIZE
+
1014 GEN6_3DSTATE_VF_STATISTICS__SIZE
+
1015 GEN6_PIPELINE_SELECT__SIZE
+
1016 GEN6_3DSTATE_BINDING_TABLE_POINTERS__SIZE
+
1017 GEN6_3DSTATE_SAMPLER_STATE_POINTERS__SIZE
+
1018 GEN6_3DSTATE_URB__SIZE
+
1019 GEN6_3DSTATE_VERTEX_BUFFERS__SIZE
+
1020 GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE
+
1021 GEN6_3DSTATE_INDEX_BUFFER__SIZE
+
1022 GEN6_3DSTATE_VIEWPORT_STATE_POINTERS__SIZE
+
1023 GEN6_3DSTATE_CC_STATE_POINTERS__SIZE
+
1024 GEN6_3DSTATE_SCISSOR_STATE_POINTERS__SIZE
+
1025 GEN6_3DSTATE_VS__SIZE
+
1026 GEN6_3DSTATE_GS__SIZE
+
1027 GEN6_3DSTATE_CLIP__SIZE
+
1028 GEN6_3DSTATE_SF__SIZE
+
1029 GEN6_3DSTATE_WM__SIZE
+
1030 GEN6_3DSTATE_SAMPLE_MASK__SIZE
+
1031 GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE
+
1032 GEN6_3DSTATE_DEPTH_BUFFER__SIZE
+
1033 GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE
+
1034 GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE
+
1035 GEN6_3DSTATE_LINE_STIPPLE__SIZE
+
1036 GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE
+
1037 GEN6_3DSTATE_MULTISAMPLE__SIZE
+
1038 GEN6_3DSTATE_STENCIL_BUFFER__SIZE
+
1039 GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE
+
1040 GEN6_3DSTATE_CLEAR_PARAMS__SIZE
+
1041 GEN6_3DPRIMITIVE__SIZE
;