2 * Mesa 3-D graphics library
4 * Copyright (C) 2012-2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "pipe/p_state.h"
29 #include "os/os_misc.h"
30 #include "util/u_format_s3tc.h"
31 #include "vl/vl_decoder.h"
32 #include "vl/vl_video_buffer.h"
33 #include "genhw/genhw.h" /* for GEN6_REG_TIMESTAMP */
34 #include "core/intel_winsys.h"
36 #include "ilo_context.h"
37 #include "ilo_format.h"
38 #include "ilo_resource.h"
39 #include "ilo_transfer.h" /* for ILO_TRANSFER_MAP_BUFFER_ALIGNMENT */
40 #include "ilo_public.h"
41 #include "ilo_screen.h"
43 struct pipe_fence_handle
{
44 struct pipe_reference reference
;
45 struct intel_bo
*seqno_bo
;
49 ilo_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
52 case PIPE_CAPF_MAX_LINE_WIDTH
:
53 /* in U3.7, defined in 3DSTATE_SF */
55 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
56 /* line width minus one, which is reserved for AA region */
58 case PIPE_CAPF_MAX_POINT_WIDTH
:
59 /* in U8.3, defined in 3DSTATE_SF */
61 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
62 /* same as point width, as we ignore rasterizer->point_smooth */
64 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
65 /* [2.0, 16.0], defined in SAMPLER_STATE */
67 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
68 /* [-16.0, 16.0), defined in SAMPLER_STATE */
70 case PIPE_CAPF_GUARD_BAND_LEFT
:
71 case PIPE_CAPF_GUARD_BAND_TOP
:
72 case PIPE_CAPF_GUARD_BAND_RIGHT
:
73 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
74 /* what are these for? */
83 ilo_get_shader_param(struct pipe_screen
*screen
, unsigned shader
,
84 enum pipe_shader_cap param
)
87 case PIPE_SHADER_FRAGMENT
:
88 case PIPE_SHADER_VERTEX
:
89 case PIPE_SHADER_GEOMETRY
:
96 /* the limits are copied from the classic driver */
97 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
98 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 16384;
99 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
100 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 0;
101 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
102 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 0;
103 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
104 return (shader
== PIPE_SHADER_FRAGMENT
) ? 1024 : 0;
105 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
107 case PIPE_SHADER_CAP_MAX_INPUTS
:
108 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
109 /* this is limited by how many attributes SF can remap */
111 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
112 return 1024 * sizeof(float[4]);
113 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
114 return ILO_MAX_CONST_BUFFERS
;
115 case PIPE_SHADER_CAP_MAX_TEMPS
:
117 case PIPE_SHADER_CAP_MAX_PREDS
:
119 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
121 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
123 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
125 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
126 return (shader
== PIPE_SHADER_FRAGMENT
) ? 0 : 1;
127 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
129 case PIPE_SHADER_CAP_SUBROUTINES
:
131 case PIPE_SHADER_CAP_INTEGERS
:
133 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
134 return ILO_MAX_SAMPLERS
;
135 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
136 return ILO_MAX_SAMPLER_VIEWS
;
137 case PIPE_SHADER_CAP_PREFERRED_IR
:
138 return PIPE_SHADER_IR_TGSI
;
139 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
141 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
143 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
152 ilo_get_video_param(struct pipe_screen
*screen
,
153 enum pipe_video_profile profile
,
154 enum pipe_video_entrypoint entrypoint
,
155 enum pipe_video_cap param
)
158 case PIPE_VIDEO_CAP_SUPPORTED
:
159 return vl_profile_supported(screen
, profile
, entrypoint
);
160 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
162 case PIPE_VIDEO_CAP_MAX_WIDTH
:
163 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
164 return vl_video_buffer_max_size(screen
);
165 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
166 return PIPE_FORMAT_NV12
;
167 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
169 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
171 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
173 case PIPE_VIDEO_CAP_MAX_LEVEL
:
174 return vl_level_supported(screen
, profile
);
181 ilo_get_compute_param(struct pipe_screen
*screen
,
182 enum pipe_shader_ir ir_type
,
183 enum pipe_compute_cap param
,
186 struct ilo_screen
*is
= ilo_screen(screen
);
188 const char *ir_target
;
189 uint64_t grid_dimension
;
190 uint64_t max_grid_size
[3];
191 uint64_t max_block_size
[3];
192 uint64_t max_threads_per_block
;
193 uint64_t max_global_size
;
194 uint64_t max_local_size
;
195 uint64_t max_private_size
;
196 uint64_t max_input_size
;
197 uint64_t max_mem_alloc_size
;
198 uint32_t max_clock_frequency
;
199 uint32_t max_compute_units
;
200 uint32_t images_supported
;
201 uint32_t subgroup_size
;
202 uint32_t address_bits
;
208 case PIPE_COMPUTE_CAP_IR_TARGET
:
209 val
.ir_target
= "ilog";
212 size
= strlen(val
.ir_target
) + 1;
214 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
215 val
.grid_dimension
= ARRAY_SIZE(val
.max_grid_size
);
217 ptr
= &val
.grid_dimension
;
218 size
= sizeof(val
.grid_dimension
);
220 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
221 val
.max_grid_size
[0] = 0xffffffffu
;
222 val
.max_grid_size
[1] = 0xffffffffu
;
223 val
.max_grid_size
[2] = 0xffffffffu
;
225 ptr
= &val
.max_grid_size
;
226 size
= sizeof(val
.max_grid_size
);
228 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
229 val
.max_block_size
[0] = 1024;
230 val
.max_block_size
[1] = 1024;
231 val
.max_block_size
[2] = 1024;
233 ptr
= &val
.max_block_size
;
234 size
= sizeof(val
.max_block_size
);
237 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
238 val
.max_threads_per_block
= 1024;
240 ptr
= &val
.max_threads_per_block
;
241 size
= sizeof(val
.max_threads_per_block
);
243 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
244 /* \see ilo_max_resource_size */
245 val
.max_global_size
= 1u << 31;
247 ptr
= &val
.max_global_size
;
248 size
= sizeof(val
.max_global_size
);
250 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
251 /* Shared Local Memory Size of INTERFACE_DESCRIPTOR_DATA */
252 val
.max_local_size
= 64 * 1024;
254 ptr
= &val
.max_local_size
;
255 size
= sizeof(val
.max_local_size
);
257 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
259 val
.max_private_size
= 12 * 1024;
261 ptr
= &val
.max_private_size
;
262 size
= sizeof(val
.max_private_size
);
264 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
265 val
.max_input_size
= 1024;
267 ptr
= &val
.max_input_size
;
268 size
= sizeof(val
.max_input_size
);
270 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
271 val
.address_bits
= 32;
272 ptr
= &val
.address_bits
;
273 size
= sizeof(val
.address_bits
);
275 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
276 val
.max_mem_alloc_size
= 1u << 31;
278 ptr
= &val
.max_mem_alloc_size
;
279 size
= sizeof(val
.max_mem_alloc_size
);
281 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
282 val
.max_clock_frequency
= 1000;
284 ptr
= &val
.max_clock_frequency
;
285 size
= sizeof(val
.max_clock_frequency
);
287 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
288 val
.max_compute_units
= is
->dev
.eu_count
;
290 ptr
= &val
.max_compute_units
;
291 size
= sizeof(val
.max_compute_units
);
293 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
294 val
.images_supported
= 1;
296 ptr
= &val
.images_supported
;
297 size
= sizeof(val
.images_supported
);
299 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
300 /* best case is actually SIMD32 */
301 val
.subgroup_size
= 16;
303 ptr
= &val
.subgroup_size
;
304 size
= sizeof(val
.subgroup_size
);
306 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
315 memcpy(ret
, ptr
, size
);
321 ilo_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
323 struct ilo_screen
*is
= ilo_screen(screen
);
326 case PIPE_CAP_NPOT_TEXTURES
:
327 case PIPE_CAP_TWO_SIDED_STENCIL
:
329 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
331 case PIPE_CAP_ANISOTROPIC_FILTER
:
332 case PIPE_CAP_POINT_SPRITE
:
334 case PIPE_CAP_MAX_RENDER_TARGETS
:
335 return ILO_MAX_DRAW_BUFFERS
;
336 case PIPE_CAP_OCCLUSION_QUERY
:
337 case PIPE_CAP_QUERY_TIME_ELAPSED
:
338 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
339 case PIPE_CAP_TEXTURE_SWIZZLE
: /* must be supported for shadow map */
341 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
343 * As defined in SURFACE_STATE, we have
345 * Max WxHxD for 2D and CUBE Max WxHxD for 3D
346 * GEN6 8192x8192x512 2048x2048x2048
347 * GEN7 16384x16384x2048 2048x2048x2048
349 return (ilo_dev_gen(&is
->dev
) >= ILO_GEN(7)) ? 15 : 14;
350 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
352 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
353 return (ilo_dev_gen(&is
->dev
) >= ILO_GEN(7)) ? 15 : 14;
354 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
356 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
359 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
360 if (ilo_dev_gen(&is
->dev
) >= ILO_GEN(7) && !is
->dev
.has_gen7_sol_reset
)
362 return ILO_MAX_SO_BUFFERS
;
363 case PIPE_CAP_PRIMITIVE_RESTART
:
365 case PIPE_CAP_INDEP_BLEND_ENABLE
:
366 case PIPE_CAP_INDEP_BLEND_FUNC
:
368 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
369 return (ilo_dev_gen(&is
->dev
) >= ILO_GEN(7.5)) ? 2048 : 512;
370 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
371 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
372 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
373 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
374 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
376 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
378 case PIPE_CAP_TGSI_INSTANCEID
:
379 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
381 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
383 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
385 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
386 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
388 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
389 case PIPE_CAP_MIN_TEXEL_OFFSET
:
391 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
392 case PIPE_CAP_MAX_TEXEL_OFFSET
:
394 case PIPE_CAP_CONDITIONAL_RENDER
:
395 case PIPE_CAP_TEXTURE_BARRIER
:
397 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
398 return ILO_MAX_SO_BINDINGS
/ ILO_MAX_SO_BUFFERS
;
399 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
400 return ILO_MAX_SO_BINDINGS
;
401 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
402 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
403 if (ilo_dev_gen(&is
->dev
) >= ILO_GEN(7))
404 return is
->dev
.has_gen7_sol_reset
;
406 return false; /* TODO */
407 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
409 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
411 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
413 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
415 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
416 case PIPE_CAP_USER_VERTEX_BUFFERS
:
418 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
419 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
420 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
422 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
424 case PIPE_CAP_COMPUTE
:
425 return false; /* TODO */
426 case PIPE_CAP_USER_INDEX_BUFFERS
:
427 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
429 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
430 /* imposed by OWord (Dual) Block Read */
432 case PIPE_CAP_START_INSTANCE
:
434 case PIPE_CAP_QUERY_TIMESTAMP
:
435 return is
->dev
.has_timestamp
;
436 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
437 return false; /* TODO */
438 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
439 return ILO_TRANSFER_MAP_BUFFER_ALIGNMENT
;
440 case PIPE_CAP_CUBE_MAP_ARRAY
:
441 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
443 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
445 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
447 case PIPE_CAP_TGSI_TEXCOORD
:
449 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
450 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
452 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
454 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
455 /* a GEN6_SURFTYPE_BUFFER can have up to 2^27 elements */
457 case PIPE_CAP_MAX_VIEWPORTS
:
458 return ILO_MAX_VIEWPORTS
;
459 case PIPE_CAP_ENDIANNESS
:
460 return PIPE_ENDIAN_LITTLE
;
461 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
462 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
464 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
465 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
466 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
467 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
468 case PIPE_CAP_TEXTURE_GATHER_SM5
:
470 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
471 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
472 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
474 case PIPE_CAP_FAKE_SW_MSAA
:
475 case PIPE_CAP_TEXTURE_QUERY_LOD
:
476 case PIPE_CAP_SAMPLE_SHADING
:
477 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
478 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
479 case PIPE_CAP_MAX_VERTEX_STREAMS
:
480 case PIPE_CAP_DRAW_INDIRECT
:
481 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
482 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
483 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
484 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
485 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
486 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
487 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
488 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
489 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
490 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
491 case PIPE_CAP_TGSI_TXQS
:
492 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
493 case PIPE_CAP_SHAREABLE_SHADERS
:
494 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
495 case PIPE_CAP_CLEAR_TEXTURE
:
496 case PIPE_CAP_DRAW_PARAMETERS
:
497 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
498 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
499 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
500 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
501 case PIPE_CAP_INVALIDATE_BUFFER
:
502 case PIPE_CAP_GENERATE_MIPMAP
:
503 case PIPE_CAP_STRING_MARKER
:
504 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
505 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
506 case PIPE_CAP_QUERY_MEMORY_INFO
:
507 case PIPE_CAP_PCI_GROUP
:
508 case PIPE_CAP_PCI_BUS
:
509 case PIPE_CAP_PCI_DEVICE
:
510 case PIPE_CAP_PCI_FUNCTION
:
511 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
512 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
513 case PIPE_CAP_CULL_DISTANCE
:
514 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
515 case PIPE_CAP_TGSI_VOTE
:
516 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
517 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
518 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
519 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
520 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
521 case PIPE_CAP_NATIVE_FENCE_FD
:
522 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
525 case PIPE_CAP_VENDOR_ID
:
527 case PIPE_CAP_DEVICE_ID
:
528 return is
->dev
.devid
;
529 case PIPE_CAP_ACCELERATED
:
531 case PIPE_CAP_VIDEO_MEMORY
: {
532 /* Once a batch uses more than 75% of the maximum mappable size, we
533 * assume that there's some fragmentation, and we start doing extra
534 * flushing, etc. That's the big cliff apps will care about.
536 const uint64_t gpu_memory
= is
->dev
.aperture_total
* 3 / 4;
537 uint64_t system_memory
;
539 if (!os_get_total_physical_memory(&system_memory
))
542 return (int) (MIN2(gpu_memory
, system_memory
) >> 20);
546 case PIPE_CAP_CLIP_HALFZ
:
548 case PIPE_CAP_VERTEXID_NOBASE
:
550 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
559 ilo_get_vendor(struct pipe_screen
*screen
)
561 return "LunarG, Inc.";
565 ilo_get_device_vendor(struct pipe_screen
*screen
)
571 ilo_get_name(struct pipe_screen
*screen
)
573 struct ilo_screen
*is
= ilo_screen(screen
);
574 const char *chipset
= NULL
;
576 if (gen_is_chv(is
->dev
.devid
)) {
577 chipset
= "Intel(R) Cherryview";
578 } else if (gen_is_bdw(is
->dev
.devid
)) {
579 /* this is likely wrong */
580 if (gen_is_desktop(is
->dev
.devid
))
581 chipset
= "Intel(R) Broadwell Desktop";
582 else if (gen_is_mobile(is
->dev
.devid
))
583 chipset
= "Intel(R) Broadwell Mobile";
584 else if (gen_is_server(is
->dev
.devid
))
585 chipset
= "Intel(R) Broadwell Server";
586 } else if (gen_is_vlv(is
->dev
.devid
)) {
587 chipset
= "Intel(R) Bay Trail";
588 } else if (gen_is_hsw(is
->dev
.devid
)) {
589 if (gen_is_desktop(is
->dev
.devid
))
590 chipset
= "Intel(R) Haswell Desktop";
591 else if (gen_is_mobile(is
->dev
.devid
))
592 chipset
= "Intel(R) Haswell Mobile";
593 else if (gen_is_server(is
->dev
.devid
))
594 chipset
= "Intel(R) Haswell Server";
595 } else if (gen_is_ivb(is
->dev
.devid
)) {
596 if (gen_is_desktop(is
->dev
.devid
))
597 chipset
= "Intel(R) Ivybridge Desktop";
598 else if (gen_is_mobile(is
->dev
.devid
))
599 chipset
= "Intel(R) Ivybridge Mobile";
600 else if (gen_is_server(is
->dev
.devid
))
601 chipset
= "Intel(R) Ivybridge Server";
602 } else if (gen_is_snb(is
->dev
.devid
)) {
603 if (gen_is_desktop(is
->dev
.devid
))
604 chipset
= "Intel(R) Sandybridge Desktop";
605 else if (gen_is_mobile(is
->dev
.devid
))
606 chipset
= "Intel(R) Sandybridge Mobile";
607 else if (gen_is_server(is
->dev
.devid
))
608 chipset
= "Intel(R) Sandybridge Server";
612 chipset
= "Unknown Intel Chipset";
618 ilo_get_timestamp(struct pipe_screen
*screen
)
620 struct ilo_screen
*is
= ilo_screen(screen
);
626 intel_winsys_read_reg(is
->dev
.winsys
, GEN6_REG_TIMESTAMP
, ×tamp
.val
);
629 * From the Ivy Bridge PRM, volume 1 part 3, page 107:
631 * "Note: This timestamp register reflects the value of the PCU TSC.
632 * The PCU TSC counts 10ns increments; this timestamp reflects bits
633 * 38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5
636 * However, it seems dw[0] is garbage and dw[1] contains the lower 32 bits
637 * of the timestamp. We will have to live with a timestamp that rolls over
638 * every ~343 seconds.
640 * See also brw_get_timestamp().
642 return (uint64_t) timestamp
.dw
[1] * 80;
646 ilo_is_format_supported(struct pipe_screen
*screen
,
647 enum pipe_format format
,
648 enum pipe_texture_target target
,
649 unsigned sample_count
,
652 struct ilo_screen
*is
= ilo_screen(screen
);
653 const struct ilo_dev
*dev
= &is
->dev
;
655 if (!util_format_is_supported(format
, bindings
))
658 /* no MSAA support yet */
659 if (sample_count
> 1)
662 if ((bindings
& PIPE_BIND_DEPTH_STENCIL
) &&
663 !ilo_format_support_zs(dev
, format
))
666 if ((bindings
& PIPE_BIND_RENDER_TARGET
) &&
667 !ilo_format_support_rt(dev
, format
))
670 if ((bindings
& PIPE_BIND_SAMPLER_VIEW
) &&
671 !ilo_format_support_sampler(dev
, format
))
674 if ((bindings
& PIPE_BIND_VERTEX_BUFFER
) &&
675 !ilo_format_support_vb(dev
, format
))
682 ilo_is_video_format_supported(struct pipe_screen
*screen
,
683 enum pipe_format format
,
684 enum pipe_video_profile profile
,
685 enum pipe_video_entrypoint entrypoint
)
687 return vl_video_buffer_is_format_supported(screen
, format
, profile
, entrypoint
);
691 ilo_screen_fence_reference(struct pipe_screen
*screen
,
692 struct pipe_fence_handle
**ptr
,
693 struct pipe_fence_handle
*fence
)
695 struct pipe_fence_handle
*old
;
704 STATIC_ASSERT(&((struct pipe_fence_handle
*) NULL
)->reference
== NULL
);
705 if (pipe_reference(&old
->reference
, &fence
->reference
)) {
706 intel_bo_unref(old
->seqno_bo
);
712 ilo_screen_fence_finish(struct pipe_screen
*screen
,
713 struct pipe_context
*ctx
,
714 struct pipe_fence_handle
*fence
,
717 const int64_t wait_timeout
= (timeout
> INT64_MAX
) ? -1 : timeout
;
720 signaled
= (!fence
->seqno_bo
||
721 intel_bo_wait(fence
->seqno_bo
, wait_timeout
) == 0);
723 /* XXX not thread safe */
724 if (signaled
&& fence
->seqno_bo
) {
725 intel_bo_unref(fence
->seqno_bo
);
726 fence
->seqno_bo
= NULL
;
733 * Create a fence for \p bo. When \p bo is not NULL, it must be submitted
734 * before waited on or checked.
736 struct pipe_fence_handle
*
737 ilo_screen_fence_create(struct pipe_screen
*screen
, struct intel_bo
*bo
)
739 struct pipe_fence_handle
*fence
;
741 fence
= CALLOC_STRUCT(pipe_fence_handle
);
745 pipe_reference_init(&fence
->reference
, 1);
747 fence
->seqno_bo
= intel_bo_ref(bo
);
753 ilo_screen_destroy(struct pipe_screen
*screen
)
755 struct ilo_screen
*is
= ilo_screen(screen
);
757 intel_winsys_destroy(is
->dev
.winsys
);
763 ilo_screen_create(struct intel_winsys
*ws
)
765 struct ilo_screen
*is
;
767 ilo_debug_init("ILO_DEBUG");
769 is
= CALLOC_STRUCT(ilo_screen
);
773 if (!ilo_dev_init(&is
->dev
, ws
)) {
778 util_format_s3tc_init();
780 is
->base
.destroy
= ilo_screen_destroy
;
781 is
->base
.get_name
= ilo_get_name
;
782 is
->base
.get_vendor
= ilo_get_vendor
;
783 is
->base
.get_device_vendor
= ilo_get_device_vendor
;
784 is
->base
.get_param
= ilo_get_param
;
785 is
->base
.get_paramf
= ilo_get_paramf
;
786 is
->base
.get_shader_param
= ilo_get_shader_param
;
787 is
->base
.get_video_param
= ilo_get_video_param
;
788 is
->base
.get_compute_param
= ilo_get_compute_param
;
790 is
->base
.get_timestamp
= ilo_get_timestamp
;
792 is
->base
.is_format_supported
= ilo_is_format_supported
;
793 is
->base
.is_video_format_supported
= ilo_is_video_format_supported
;
795 is
->base
.flush_frontbuffer
= NULL
;
797 is
->base
.fence_reference
= ilo_screen_fence_reference
;
798 is
->base
.fence_finish
= ilo_screen_fence_finish
;
800 is
->base
.get_driver_query_info
= NULL
;
802 ilo_init_context_functions(is
);
803 ilo_init_resource_functions(is
);