src/gallium/drivers/iris/iris_batch.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef IRIS_BATCH_DOT_H
  25 #define IRIS_BATCH_DOT_H
  26
  27 #include <stdint.h>
  28 #include <stdbool.h>
  29 #include <string.h>
  30
  31 #include "util/u_dynarray.h"
  32
  33 #include "drm-uapi/i915_drm.h"
  34 #include "common/gen_decoder.h"
  35
  36 #include "iris_fence.h"
  37
  38 /* The kernel assumes batchbuffers are smaller than 256kB. */
  39 #define MAX_BATCH_SIZE (256 * 1024)
  40
  41 /* Our target batch size - flush approximately at this point. */
  42 #define BATCH_SZ (20 * 1024)
  43
  44 enum iris_batch_name {
  45    IRIS_BATCH_RENDER,
  46    IRIS_BATCH_COMPUTE,
  47 };
  48
  49 #define IRIS_BATCH_COUNT 2
  50
  51 struct iris_address {
  52    struct iris_bo *bo;
  53    uint64_t offset;
  54    bool write;
  55 };
  56
  57 struct iris_batch {
  58    struct iris_screen *screen;
  59    struct iris_vtable *vtbl;
  60    struct pipe_debug_callback *dbg;
  61    struct pipe_device_reset_callback *reset;
  62
  63    /** What batch is this? (e.g. IRIS_BATCH_RENDER/COMPUTE) */
  64    enum iris_batch_name name;
  65
  66    /** Current batchbuffer being queued up. */
  67    struct iris_bo *bo;
  68    void *map;
  69    void *map_next;
  70    /** Size of the primary batch if we've moved on to a secondary. */
  71    unsigned primary_batch_size;
  72
  73    /** Last Surface State Base Address set in this hardware context. */
  74    uint64_t last_surface_base_address;
  75
  76    uint32_t hw_ctx_id;
  77
  78    /** Which engine this batch targets - a I915_EXEC_RING_MASK value */
  79    uint8_t engine;
  80
  81    /** The validation list */
  82    struct drm_i915_gem_exec_object2 *validation_list;
  83    struct iris_bo **exec_bos;
  84    int exec_count;
  85    int exec_array_size;
  86
  87    /**
  88     * A list of iris_syncpts associated with this batch.
  89     *
  90     * The first list entry will always be a signalling sync-point, indicating
  91     * that this batch has completed.  The others are likely to be sync-points
  92     * to wait on before executing the batch.
  93     */
  94    struct util_dynarray syncpts;
  95
  96    /** A list of drm_i915_exec_fences to have execbuf signal or wait on */
  97    struct util_dynarray exec_fences;
  98
  99    /** The amount of aperture space (in bytes) used by all exec_bos */
 100    int aperture_space;
 101
 102    /** A sync-point for the last batch that was submitted. */
 103    struct iris_syncpt *last_syncpt;
 104
 105    /** List of other batches which we might need to flush to use a BO */
 106    struct iris_batch *other_batches[IRIS_BATCH_COUNT - 1];
 107
 108    struct {
 109       /**
 110        * Set of struct brw_bo * that have been rendered to within this
 111        * batchbuffer and would need flushing before being used from another
 112        * cache domain that isn't coherent with it (i.e. the sampler).
 113        */
 114       struct hash_table *render;
 115
 116       /**
 117        * Set of struct brw_bo * that have been used as a depth buffer within
 118        * this batchbuffer and would need flushing before being used from
 119        * another cache domain that isn't coherent with it (i.e. the sampler).
 120        */
 121       struct set *depth;
 122    } cache;
 123
 124    struct gen_batch_decode_ctx decoder;
 125
 126    /** Have we emitted any draw calls to this batch? */
 127    bool contains_draw;
 128 };
 129
 130 void iris_init_batch(struct iris_batch *batch,
 131                      struct iris_screen *screen,
 132                      struct iris_vtable *vtbl,
 133                      struct pipe_debug_callback *dbg,
 134                      struct pipe_device_reset_callback *reset,
 135                      struct iris_batch *all_batches,
 136                      enum iris_batch_name name,
 137                      uint8_t ring,
 138                      int priority);
 139 void iris_chain_to_new_batch(struct iris_batch *batch);
 140 void iris_batch_free(struct iris_batch *batch);
 141 void iris_batch_maybe_flush(struct iris_batch *batch, unsigned estimate);
 142
 143 void _iris_batch_flush(struct iris_batch *batch, const char *file, int line);
 144 #define iris_batch_flush(batch) _iris_batch_flush((batch), __FILE__, __LINE__)
 145
 146 bool iris_batch_references(struct iris_batch *batch, struct iris_bo *bo);
 147
 148 #define RELOC_WRITE EXEC_OBJECT_WRITE
 149
 150 void iris_use_pinned_bo(struct iris_batch *batch, struct iris_bo *bo,
 151                         bool writable);
 152
 153 static inline unsigned
 154 iris_batch_bytes_used(struct iris_batch *batch)
 155 {
 156    return batch->map_next - batch->map;
 157 }
 158
 159 /**
 160  * Ensure the current command buffer has \param size bytes of space
 161  * remaining.  If not, this creates a secondary batch buffer and emits
 162  * a jump from the primary batch to the start of the secondary.
 163  *
 164  * Most callers want iris_get_command_space() instead.
 165  */
 166 static inline void
 167 iris_require_command_space(struct iris_batch *batch, unsigned size)
 168 {
 169    const unsigned required_bytes = iris_batch_bytes_used(batch) + size;
 170
 171    if (required_bytes >= BATCH_SZ) {
 172       iris_chain_to_new_batch(batch);
 173    }
 174 }
 175
 176 /**
 177  * Allocate space in the current command buffer, and return a pointer
 178  * to the mapped area so the caller can write commands there.
 179  *
 180  * This should be called whenever emitting commands.
 181  */
 182 static inline void *
 183 iris_get_command_space(struct iris_batch *batch, unsigned bytes)
 184 {
 185    iris_require_command_space(batch, bytes);
 186    void *map = batch->map_next;
 187    batch->map_next += bytes;
 188    return map;
 189 }
 190
 191 /**
 192  * Helper to emit GPU commands - allocates space, copies them there.
 193  */
 194 static inline void
 195 iris_batch_emit(struct iris_batch *batch, const void *data, unsigned size)
 196 {
 197    void *map = iris_get_command_space(batch, size);
 198    memcpy(map, data, size);
 199 }
 200
 201 /**
 202  * Take a reference to the batch's signalling syncpt.
 203  *
 204  * Callers can use this to wait for the the current batch under construction
 205  * to complete (after flushing it).
 206  */
 207 static inline void
 208 iris_batch_reference_signal_syncpt(struct iris_batch *batch,
 209                                    struct iris_syncpt **out_syncpt)
 210 {
 211    /* The signalling syncpt is the first one in the list. */
 212    struct iris_syncpt *syncpt =
 213       ((struct iris_syncpt **) util_dynarray_begin(&batch->syncpts))[0];
 214    iris_syncpt_reference(batch->screen, out_syncpt, syncpt);
 215 }
 216
 217 #endif