src/gallium/drivers/iris/iris_blorp.c

   1 /*
   2  * Copyright © 2018 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 /**
  24  * @file iris_blorp.c
  25  *
  26  * ============================= GENXML CODE =============================
  27  *              [This file is compiled once per generation.]
  28  * =======================================================================
  29  *
  30  * GenX specific code for working with BLORP (blitting, resolves, clears
  31  * on the 3D engine).  This provides the driver-specific hooks needed to
  32  * implement the BLORP API.
  33  *
  34  * See iris_blit.c, iris_clear.c, and so on.
  35  */
  36
  37 #include <assert.h>
  38
  39 #include "iris_batch.h"
  40 #include "iris_resource.h"
  41 #include "iris_context.h"
  42
  43 #include "util/u_upload_mgr.h"
  44 #include "intel/common/gen_l3_config.h"
  45
  46 #define BLORP_USE_SOFTPIN
  47 #include "blorp/blorp_genX_exec.h"
  48
  49 static uint32_t *
  50 stream_state(struct iris_batch *batch,
  51              struct u_upload_mgr *uploader,
  52              unsigned size,
  53              unsigned alignment,
  54              uint32_t *out_offset,
  55              struct iris_bo **out_bo)
  56 {
  57    struct pipe_resource *res = NULL;
  58    void *ptr = NULL;
  59
  60    u_upload_alloc(uploader, 0, size, alignment, out_offset, &res, &ptr);
  61
  62    struct iris_bo *bo = iris_resource_bo(res);
  63    iris_use_pinned_bo(batch, bo, false, IRIS_DOMAIN_NONE);
  64
  65    iris_record_state_size(batch->state_sizes,
  66                           bo->gtt_offset + *out_offset, size);
  67
  68    /* If the caller has asked for a BO, we leave them the responsibility of
  69     * adding bo->gtt_offset (say, by handing an address to genxml).  If not,
  70     * we assume they want the offset from a base address.
  71     */
  72    if (out_bo)
  73       *out_bo = bo;
  74    else
  75       *out_offset += iris_bo_offset_from_base_address(bo);
  76
  77    pipe_resource_reference(&res, NULL);
  78
  79    return ptr;
  80 }
  81
  82 static void *
  83 blorp_emit_dwords(struct blorp_batch *blorp_batch, unsigned n)
  84 {
  85    struct iris_batch *batch = blorp_batch->driver_batch;
  86    return iris_get_command_space(batch, n * sizeof(uint32_t));
  87 }
  88
  89 static uint64_t
  90 combine_and_pin_address(struct blorp_batch *blorp_batch,
  91                         struct blorp_address addr)
  92 {
  93    struct iris_batch *batch = blorp_batch->driver_batch;
  94    struct iris_bo *bo = addr.buffer;
  95
  96    iris_use_pinned_bo(batch, bo, addr.reloc_flags & RELOC_WRITE,
  97                       IRIS_DOMAIN_NONE);
  98
  99    /* Assume this is a general address, not relative to a base. */
 100    return bo->gtt_offset + addr.offset;
 101 }
 102
 103 static uint64_t
 104 blorp_emit_reloc(struct blorp_batch *blorp_batch, UNUSED void *location,
 105                  struct blorp_address addr, uint32_t delta)
 106 {
 107    return combine_and_pin_address(blorp_batch, addr) + delta;
 108 }
 109
 110 static void
 111 blorp_surface_reloc(struct blorp_batch *blorp_batch, uint32_t ss_offset,
 112                     struct blorp_address addr, uint32_t delta)
 113 {
 114    /* Let blorp_get_surface_address do the pinning. */
 115 }
 116
 117 static uint64_t
 118 blorp_get_surface_address(struct blorp_batch *blorp_batch,
 119                           struct blorp_address addr)
 120 {
 121    return combine_and_pin_address(blorp_batch, addr);
 122 }
 123
 124 UNUSED static struct blorp_address
 125 blorp_get_surface_base_address(UNUSED struct blorp_batch *blorp_batch)
 126 {
 127    return (struct blorp_address) { .offset = IRIS_MEMZONE_BINDER_START };
 128 }
 129
 130 static void *
 131 blorp_alloc_dynamic_state(struct blorp_batch *blorp_batch,
 132                           uint32_t size,
 133                           uint32_t alignment,
 134                           uint32_t *offset)
 135 {
 136    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 137    struct iris_batch *batch = blorp_batch->driver_batch;
 138
 139    return stream_state(batch, ice->state.dynamic_uploader,
 140                        size, alignment, offset, NULL);
 141 }
 142
 143 static void
 144 blorp_alloc_binding_table(struct blorp_batch *blorp_batch,
 145                           unsigned num_entries,
 146                           unsigned state_size,
 147                           unsigned state_alignment,
 148                           uint32_t *bt_offset,
 149                           uint32_t *surface_offsets,
 150                           void **surface_maps)
 151 {
 152    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 153    struct iris_binder *binder = &ice->state.binder;
 154    struct iris_batch *batch = blorp_batch->driver_batch;
 155
 156    *bt_offset = iris_binder_reserve(ice, num_entries * sizeof(uint32_t));
 157    uint32_t *bt_map = binder->map + *bt_offset;
 158
 159    for (unsigned i = 0; i < num_entries; i++) {
 160       surface_maps[i] = stream_state(batch, ice->state.surface_uploader,
 161                                      state_size, state_alignment,
 162                                      &surface_offsets[i], NULL);
 163       bt_map[i] = surface_offsets[i] - (uint32_t) binder->bo->gtt_offset;
 164    }
 165
 166    iris_use_pinned_bo(batch, binder->bo, false, IRIS_DOMAIN_NONE);
 167
 168    batch->screen->vtbl.update_surface_base_address(batch, binder);
 169 }
 170
 171 static void *
 172 blorp_alloc_vertex_buffer(struct blorp_batch *blorp_batch,
 173                           uint32_t size,
 174                           struct blorp_address *addr)
 175 {
 176    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 177    struct iris_batch *batch = blorp_batch->driver_batch;
 178    struct iris_bo *bo;
 179    uint32_t offset;
 180
 181    void *map = stream_state(batch, ice->ctx.stream_uploader, size, 64,
 182                             &offset, &bo);
 183
 184    *addr = (struct blorp_address) {
 185       .buffer = bo,
 186       .offset = offset,
 187       .mocs = iris_mocs(bo, &batch->screen->isl_dev),
 188    };
 189
 190    return map;
 191 }
 192
 193 /**
 194  * See iris_upload_render_state's IRIS_DIRTY_VERTEX_BUFFERS handling for
 195  * a comment about why these VF invalidations are needed.
 196  */
 197 static void
 198 blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *blorp_batch,
 199                                            const struct blorp_address *addrs,
 200                                            UNUSED uint32_t *sizes,
 201                                            unsigned num_vbs)
 202 {
 203 #if GEN_GEN < 11
 204    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 205    struct iris_batch *batch = blorp_batch->driver_batch;
 206    bool need_invalidate = false;
 207
 208    for (unsigned i = 0; i < num_vbs; i++) {
 209       struct iris_bo *bo = addrs[i].buffer;
 210       uint16_t high_bits = bo->gtt_offset >> 32u;
 211
 212       if (high_bits != ice->state.last_vbo_high_bits[i]) {
 213          need_invalidate = true;
 214          ice->state.last_vbo_high_bits[i] = high_bits;
 215       }
 216    }
 217
 218    if (need_invalidate) {
 219       iris_emit_pipe_control_flush(batch,
 220                                    "workaround: VF cache 32-bit key [blorp]",
 221                                    PIPE_CONTROL_VF_CACHE_INVALIDATE |
 222                                    PIPE_CONTROL_CS_STALL);
 223    }
 224 #endif
 225 }
 226
 227 static struct blorp_address
 228 blorp_get_workaround_address(struct blorp_batch *blorp_batch)
 229 {
 230    struct iris_batch *batch = blorp_batch->driver_batch;
 231
 232    return (struct blorp_address) {
 233       .buffer = batch->screen->workaround_address.bo,
 234       .offset = batch->screen->workaround_address.offset,
 235    };
 236 }
 237
 238 static void
 239 blorp_flush_range(UNUSED struct blorp_batch *blorp_batch,
 240                   UNUSED void *start,
 241                   UNUSED size_t size)
 242 {
 243    /* All allocated states come from the batch which we will flush before we
 244     * submit it.  There's nothing for us to do here.
 245     */
 246 }
 247
 248 static const struct gen_l3_config *
 249 blorp_get_l3_config(struct blorp_batch *blorp_batch)
 250 {
 251    struct iris_batch *batch = blorp_batch->driver_batch;
 252    return batch->screen->l3_config_3d;
 253 }
 254
 255 static void
 256 iris_blorp_exec(struct blorp_batch *blorp_batch,
 257                 const struct blorp_params *params)
 258 {
 259    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 260    struct iris_batch *batch = blorp_batch->driver_batch;
 261
 262 #if GEN_GEN >= 11
 263    /* The PIPE_CONTROL command description says:
 264     *
 265     *    "Whenever a Binding Table Index (BTI) used by a Render Target Message
 266     *     points to a different RENDER_SURFACE_STATE, SW must issue a Render
 267     *     Target Cache Flush by enabling this bit. When render target flush
 268     *     is set due to new association of BTI, PS Scoreboard Stall bit must
 269     *     be set in this packet."
 270     */
 271    iris_emit_pipe_control_flush(batch,
 272                                 "workaround: RT BTI change [blorp]",
 273                                 PIPE_CONTROL_RENDER_TARGET_FLUSH |
 274                                 PIPE_CONTROL_STALL_AT_SCOREBOARD);
 275 #endif
 276
 277    /* Flush the sampler and render caches.  We definitely need to flush the
 278     * sampler cache so that we get updated contents from the render cache for
 279     * the glBlitFramebuffer() source.  Also, we are sometimes warned in the
 280     * docs to flush the cache between reinterpretations of the same surface
 281     * data with different formats, which blorp does for stencil and depth
 282     * data.
 283     */
 284    if (params->src.enabled)
 285       iris_cache_flush_for_read(batch, params->src.addr.buffer);
 286    if (params->dst.enabled) {
 287       iris_cache_flush_for_render(batch, params->dst.addr.buffer,
 288                                   params->dst.view.format,
 289                                   params->dst.aux_usage);
 290    }
 291    if (params->depth.enabled)
 292       iris_cache_flush_for_depth(batch, params->depth.addr.buffer);
 293    if (params->stencil.enabled)
 294       iris_cache_flush_for_depth(batch, params->stencil.addr.buffer);
 295
 296    iris_require_command_space(batch, 1400);
 297
 298 #if GEN_GEN == 8
 299    genX(update_pma_fix)(ice, batch, false);
 300 #endif
 301
 302    const unsigned scale = params->fast_clear_op ? UINT_MAX : 1;
 303    if (ice->state.current_hash_scale != scale) {
 304       genX(emit_hashing_mode)(ice, batch, params->x1 - params->x0,
 305                               params->y1 - params->y0, scale);
 306    }
 307
 308 #if GEN_GEN >= 12
 309    genX(invalidate_aux_map_state)(batch);
 310 #endif
 311
 312    iris_handle_always_flush_cache(batch);
 313
 314    blorp_exec(blorp_batch, params);
 315
 316    iris_handle_always_flush_cache(batch);
 317
 318    /* We've smashed all state compared to what the normal 3D pipeline
 319     * rendering tracks for GL.
 320     */
 321
 322    uint64_t skip_bits = (IRIS_DIRTY_POLYGON_STIPPLE |
 323                          IRIS_DIRTY_SO_BUFFERS |
 324                          IRIS_DIRTY_SO_DECL_LIST |
 325                          IRIS_DIRTY_LINE_STIPPLE |
 326                          IRIS_ALL_DIRTY_FOR_COMPUTE |
 327                          IRIS_DIRTY_SCISSOR_RECT |
 328                          IRIS_DIRTY_VF |
 329                          IRIS_DIRTY_SF_CL_VIEWPORT);
 330    uint64_t skip_stage_bits = (IRIS_ALL_STAGE_DIRTY_FOR_COMPUTE |
 331                                IRIS_STAGE_DIRTY_UNCOMPILED_VS |
 332                                IRIS_STAGE_DIRTY_UNCOMPILED_TCS |
 333                                IRIS_STAGE_DIRTY_UNCOMPILED_TES |
 334                                IRIS_STAGE_DIRTY_UNCOMPILED_GS |
 335                                IRIS_STAGE_DIRTY_UNCOMPILED_FS |
 336                                IRIS_STAGE_DIRTY_SAMPLER_STATES_VS |
 337                                IRIS_STAGE_DIRTY_SAMPLER_STATES_TCS |
 338                                IRIS_STAGE_DIRTY_SAMPLER_STATES_TES |
 339                                IRIS_STAGE_DIRTY_SAMPLER_STATES_GS);
 340
 341    if (!ice->shaders.uncompiled[MESA_SHADER_TESS_EVAL]) {
 342       /* BLORP disabled tessellation, that's fine for the next draw */
 343       skip_stage_bits |= IRIS_STAGE_DIRTY_TCS |
 344                          IRIS_STAGE_DIRTY_TES |
 345                          IRIS_STAGE_DIRTY_CONSTANTS_TCS |
 346                          IRIS_STAGE_DIRTY_CONSTANTS_TES |
 347                          IRIS_STAGE_DIRTY_BINDINGS_TCS |
 348                          IRIS_STAGE_DIRTY_BINDINGS_TES;
 349    }
 350
 351    if (!ice->shaders.uncompiled[MESA_SHADER_GEOMETRY]) {
 352       /* BLORP disabled geometry shaders, that's fine for the next draw */
 353       skip_stage_bits |= IRIS_STAGE_DIRTY_GS |
 354                          IRIS_STAGE_DIRTY_CONSTANTS_GS |
 355                          IRIS_STAGE_DIRTY_BINDINGS_GS;
 356    }
 357
 358    /* we can skip flagging IRIS_DIRTY_DEPTH_BUFFER, if
 359     * BLORP_BATCH_NO_EMIT_DEPTH_STENCIL is set.
 360     */
 361    if (blorp_batch->flags & BLORP_BATCH_NO_EMIT_DEPTH_STENCIL)
 362       skip_bits |= IRIS_DIRTY_DEPTH_BUFFER;
 363
 364    if (!params->wm_prog_data)
 365       skip_bits |= IRIS_DIRTY_BLEND_STATE | IRIS_DIRTY_PS_BLEND;
 366
 367    ice->state.dirty |= ~skip_bits;
 368    ice->state.stage_dirty |= ~skip_stage_bits;
 369
 370    if (params->dst.enabled) {
 371       iris_render_cache_add_bo(batch, params->dst.addr.buffer,
 372                                params->dst.view.format,
 373                                params->dst.aux_usage);
 374    }
 375    if (params->depth.enabled)
 376       iris_depth_cache_add_bo(batch, params->depth.addr.buffer);
 377    if (params->stencil.enabled)
 378       iris_depth_cache_add_bo(batch, params->stencil.addr.buffer);
 379
 380    if (params->src.enabled)
 381       iris_bo_bump_seqno(params->src.addr.buffer, batch->next_seqno,
 382                          IRIS_DOMAIN_OTHER_READ);
 383    if (params->dst.enabled)
 384       iris_bo_bump_seqno(params->dst.addr.buffer, batch->next_seqno,
 385                          IRIS_DOMAIN_RENDER_WRITE);
 386    if (params->depth.enabled)
 387       iris_bo_bump_seqno(params->depth.addr.buffer, batch->next_seqno,
 388                          IRIS_DOMAIN_DEPTH_WRITE);
 389    if (params->stencil.enabled)
 390       iris_bo_bump_seqno(params->stencil.addr.buffer, batch->next_seqno,
 391                          IRIS_DOMAIN_DEPTH_WRITE);
 392 }
 393
 394 void
 395 genX(init_blorp)(struct iris_context *ice)
 396 {
 397    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 398
 399    blorp_init(&ice->blorp, ice, &screen->isl_dev);
 400    ice->blorp.compiler = screen->compiler;
 401    ice->blorp.lookup_shader = iris_blorp_lookup_shader;
 402    ice->blorp.upload_shader = iris_blorp_upload_shader;
 403    ice->blorp.exec = iris_blorp_exec;
 404 }