src/gallium/drivers/iris/iris_blorp.c

   1 /*
   2  * Copyright © 2018 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <assert.h>
  24
  25 #include "iris_batch.h"
  26 #include "iris_resource.h"
  27 #include "iris_context.h"
  28
  29 #include "blorp/blorp_genX_exec.h"
  30 #include "util/u_upload_mgr.h"
  31
  32 static uint32_t *
  33 stream_state(struct iris_batch *batch,
  34              struct u_upload_mgr *uploader,
  35              unsigned size,
  36              unsigned alignment,
  37              uint32_t *out_offset,
  38              struct iris_bo **out_bo)
  39 {
  40    struct pipe_resource *res = NULL;
  41    void *ptr = NULL;
  42
  43    u_upload_alloc(uploader, 0, size, alignment, out_offset, &res, &ptr);
  44
  45    *out_bo = iris_resource_bo(res);
  46    iris_use_pinned_bo(batch, *out_bo, false);
  47
  48    *out_offset += iris_bo_offset_from_base_address(*out_bo);
  49
  50    pipe_resource_reference(&res, NULL);
  51
  52    return ptr;
  53 }
  54
  55 static void *
  56 blorp_emit_dwords(struct blorp_batch *blorp_batch, unsigned n)
  57 {
  58    struct iris_batch *batch = blorp_batch->driver_batch;
  59    return iris_get_command_space(batch, n * sizeof(uint32_t));
  60 }
  61
  62 static uint64_t
  63 blorp_emit_reloc(struct blorp_batch *blorp_batch, UNUSED void *location,
  64                  struct blorp_address addr, uint32_t delta)
  65 {
  66    struct iris_batch *batch = blorp_batch->driver_batch;
  67    struct iris_bo *bo = addr.buffer;
  68    uint64_t result = addr.offset + delta;
  69
  70    if (bo) {
  71       iris_use_pinned_bo(batch, bo, addr.reloc_flags & RELOC_WRITE);
  72       /* Assume this is a general address, not relative to a base. */
  73       result += bo->gtt_offset;
  74    }
  75
  76    return result;
  77 }
  78
  79 static void
  80 blorp_surface_reloc(struct blorp_batch *blorp_batch, uint32_t ss_offset,
  81                     struct blorp_address addr, uint32_t delta)
  82 {
  83    /* Don't do anything, blorp_alloc_binding_table already added the BO. */
  84 }
  85
  86 UNUSED static struct blorp_address
  87 blorp_get_surface_base_address(UNUSED struct blorp_batch *blorp_batch)
  88 {
  89    return (struct blorp_address) { .offset = IRIS_MEMZONE_SURFACE_START };
  90 }
  91
  92 static void *
  93 blorp_alloc_dynamic_state(struct blorp_batch *blorp_batch,
  94                           uint32_t size,
  95                           uint32_t alignment,
  96                           uint32_t *offset)
  97 {
  98    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
  99    struct iris_batch *batch = blorp_batch->driver_batch;
 100    struct iris_bo *bo;
 101
 102    return stream_state(batch, ice->state.dynamic_uploader,
 103                        size, alignment, offset, &bo);
 104 }
 105
 106 static void
 107 blorp_alloc_binding_table(struct blorp_batch *blorp_batch,
 108                           unsigned num_entries,
 109                           unsigned state_size,
 110                           unsigned state_alignment,
 111                           uint32_t *bt_offset,
 112                           uint32_t *surface_offsets,
 113                           void **surface_maps)
 114 {
 115    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 116    struct iris_batch *batch = blorp_batch->driver_batch;
 117    struct iris_bo *bo;
 118
 119    uint32_t *bt_map = iris_binder_reserve(&ice->state.binder,
 120                                           num_entries * sizeof(uint32_t),
 121                                           bt_offset);
 122
 123    for (unsigned i = 0; i < num_entries; i++) {
 124       surface_maps[i] = stream_state(batch, ice->state.surface_uploader,
 125                                      state_size, state_alignment,
 126                                      &surface_offsets[i], &bo);
 127       bt_map[i] = surface_offsets[i];
 128    }
 129 }
 130
 131 static void *
 132 blorp_alloc_vertex_buffer(struct blorp_batch *blorp_batch,
 133                           uint32_t size,
 134                           struct blorp_address *addr)
 135 {
 136    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 137    struct iris_batch *batch = blorp_batch->driver_batch;
 138    struct iris_bo *bo;
 139    uint32_t offset;
 140
 141    void *map = stream_state(batch, ice->ctx.stream_uploader, size, 64,
 142                             &offset, &bo);
 143
 144    *addr = (struct blorp_address) {
 145       .buffer = bo,
 146       .offset = offset,
 147       // XXX: Broadwell MOCS
 148       .mocs = I915_MOCS_CACHED,
 149    };
 150
 151    return map;
 152 }
 153
 154 static struct blorp_address
 155 blorp_get_workaround_page(struct blorp_batch *blorp_batch)
 156 {
 157    struct iris_batch *batch = blorp_batch->driver_batch;
 158
 159    return (struct blorp_address) { .buffer = batch->screen->workaround_bo };
 160 }
 161
 162 static void
 163 blorp_flush_range(UNUSED struct blorp_batch *blorp_batch,
 164                   UNUSED void *start,
 165                   UNUSED size_t size)
 166 {
 167    /* All allocated states come from the batch which we will flush before we
 168     * submit it.  There's nothing for us to do here.
 169     */
 170 }
 171
 172 static void
 173 blorp_emit_urb_config(struct blorp_batch *blorp_batch,
 174                       unsigned vs_entry_size,
 175                       UNUSED unsigned sf_entry_size)
 176 {
 177    // XXX: URB...
 178 #if 0
 179    if (ice->urb.vsize >= vs_entry_size)
 180       return;
 181
 182    gen7_upload_urb(ice, vs_entry_size, false, false);
 183 #endif
 184 }
 185
 186 static void
 187 iris_blorp_exec(struct blorp_batch *blorp_batch,
 188                 const struct blorp_params *params)
 189 {
 190    struct iris_context *ice = blorp_batch->blorp->driver_ctx;
 191    struct iris_batch *batch = blorp_batch->driver_batch;
 192
 193    /* Flush the sampler and render caches.  We definitely need to flush the
 194     * sampler cache so that we get updated contents from the render cache for
 195     * the glBlitFramebuffer() source.  Also, we are sometimes warned in the
 196     * docs to flush the cache between reinterpretations of the same surface
 197     * data with different formats, which blorp does for stencil and depth
 198     * data.
 199     */
 200    if (params->src.enabled)
 201       iris_cache_flush_for_read(batch, params->src.addr.buffer);
 202    if (params->dst.enabled) {
 203       iris_cache_flush_for_render(batch, params->dst.addr.buffer,
 204                                   params->dst.view.format,
 205                                   params->dst.aux_usage);
 206    }
 207    if (params->depth.enabled)
 208       iris_cache_flush_for_depth(batch, params->depth.addr.buffer);
 209    if (params->stencil.enabled)
 210       iris_cache_flush_for_depth(batch, params->stencil.addr.buffer);
 211
 212    iris_require_command_space(batch, 1400);
 213    //iris_require_statebuffer_space(ice, 600); // XXX: THIS.  Need this.
 214    batch->no_wrap = true;
 215
 216    // XXX: Emit L3 state
 217
 218 #if GEN_GEN == 8
 219    // XXX: PMA - gen8_write_pma_stall_bits(ice, 0);
 220 #endif
 221
 222    // XXX: knock this off...land Jason's i965 patches...
 223    blorp_emit(blorp_batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
 224       rect.ClippedDrawingRectangleXMax = MAX2(params->x1, params->x0) - 1;
 225       rect.ClippedDrawingRectangleYMax = MAX2(params->y1, params->y0) - 1;
 226    }
 227
 228    blorp_exec(blorp_batch, params);
 229
 230    batch->no_wrap = false;
 231
 232    // XXX: aperture checks?
 233
 234    /* We've smashed all state compared to what the normal 3D pipeline
 235     * rendering tracks for GL.
 236     */
 237    // XXX: skip some if (!(batch->flags & BLORP_BATCH_NO_EMIT_DEPTH_STENCIL))
 238    ice->state.dirty |= ~(IRIS_DIRTY_POLYGON_STIPPLE |
 239                          IRIS_DIRTY_LINE_STIPPLE);
 240
 241 #if 0
 242    ice->state.dirty |= IRIS_DIRTY_VERTEX_BUFFERS |
 243                        IRIS_DIRTY_COLOR_CALC_STATE |
 244                        IRIS_DIRTY_CONSTANTS_VS |
 245                        IRIS_DIRTY_CONSTANTS_TCS |
 246                        IRIS_DIRTY_CONSTANTS_TES |
 247                        IRIS_DIRTY_CONSTANTS_GS |
 248                        IRIS_DIRTY_CONSTANTS_PS |
 249                        IRIS_DIRTY_CONSTANTS_PS |
 250                        IRIS_DIRTY_SAMPLER_STATES_VS |
 251                        IRIS_DIRTY_SAMPLER_STATES_TCS |
 252                        IRIS_DIRTY_SAMPLER_STATES_TES |
 253                        IRIS_DIRTY_SAMPLER_STATES_GS |
 254                        IRIS_DIRTY_SAMPLER_STATES_PS |
 255                        IRIS_DIRTY_SAMPLER_STATES_PS |
 256                        IRIS_DIRTY_MULTISAMPLE |
 257                        IRIS_DIRTY_SAMPLE_MASK |
 258                        IRIS_DIRTY_VS |
 259                        IRIS_DIRTY_TCS |
 260                        IRIS_DIRTY_TES |
 261                        // IRIS_DIRTY_STREAMOUT |
 262                        IRIS_DIRTY_GS |
 263                        IRIS_DIRTY_CLIP |
 264                        IRIS_DIRTY_FS |
 265                        IRIS_DIRTY_CC_VIEWPORT |
 266 #endif
 267
 268    if (params->dst.enabled) {
 269       iris_render_cache_add_bo(batch, params->dst.addr.buffer,
 270                                params->dst.view.format,
 271                                params->dst.aux_usage);
 272    }
 273    if (params->depth.enabled)
 274       iris_depth_cache_add_bo(batch, params->depth.addr.buffer);
 275    if (params->stencil.enabled)
 276       iris_depth_cache_add_bo(batch, params->stencil.addr.buffer);
 277 }
 278
 279 void
 280 genX(init_blorp)(struct iris_context *ice)
 281 {
 282    ice->vtbl.blorp_exec = iris_blorp_exec;
 283 }