src/gallium/drivers/iris/iris_bufmgr.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef IRIS_BUFMGR_H
  25 #define IRIS_BUFMGR_H
  26
  27 #include <stdbool.h>
  28 #include <stdint.h>
  29 #include <stdio.h>
  30 #include <sys/types.h>
  31 #include "util/macros.h"
  32 #include "util/u_atomic.h"
  33 #include "util/list.h"
  34 #include "pipe/p_defines.h"
  35
  36 struct gen_device_info;
  37 struct pipe_debug_callback;
  38
  39 /**
  40  * Memory zones.  When allocating a buffer, you can request that it is
  41  * placed into a specific region of the virtual address space (PPGTT).
  42  *
  43  * Most buffers can go anywhere (IRIS_MEMZONE_OTHER).  Some buffers are
  44  * accessed via an offset from a base address.  STATE_BASE_ADDRESS has
  45  * a maximum 4GB size for each region, so we need to restrict those
  46  * buffers to be within 4GB of the base.  Each memory zone corresponds
  47  * to a particular base address.
  48  *
  49  * We lay out the virtual address space as follows:
  50  *
  51  * - [0,   4K): Nothing  (empty page for null address)
  52  * - [4K,  4G): Shaders  (Instruction Base Address)
  53  * - [4G,  8G): Surfaces (Surface State Base Address, Bindless ...)
  54  * - [8G, 12G): Dynamic  (Dynamic State Base Address)
  55  * - [12G, *):  Other    (everything else in the full 48-bit VMA)
  56  *
  57  * A special 64kB "binder" buffer lives at the start of the surface memory
  58  * zone, holding binding tables referring to objects in the rest of the zone.
  59  *
  60  * A special buffer for border color lives at the start of the dynamic state
  61  * memory zone.  This unfortunately has to be handled specially because the
  62  * SAMPLER_STATE "Indirect State Pointer" field is only a 24-bit pointer.
  63  *
  64  * Each GL context uses a separate GEM context, which technically gives them
  65  * each a separate VMA.  However, we assign address globally, so buffers will
  66  * have the same address in all GEM contexts.  This lets us have a single BO
  67  * field for the address, which is easy and cheap.
  68  *
  69  * One exception is the special "binder" BO.  Binders are context-local,
  70  * so while there are many of them, all binders are stored at the same
  71  * fixed address (in different VMAs).
  72  */
  73 enum iris_memory_zone {
  74    IRIS_MEMZONE_SHADER,
  75    IRIS_MEMZONE_SURFACE,
  76    IRIS_MEMZONE_DYNAMIC,
  77    IRIS_MEMZONE_OTHER,
  78
  79    IRIS_MEMZONE_BINDER,
  80    IRIS_MEMZONE_BORDER_COLOR_POOL,
  81 };
  82
  83 /* Intentionally exclude single buffer "zones" */
  84 #define IRIS_MEMZONE_COUNT (IRIS_MEMZONE_OTHER + 2)
  85
  86 #define IRIS_MEMZONE_SHADER_START     (0ull * (1ull << 32))
  87 #define IRIS_MEMZONE_SURFACE_START    (1ull * (1ull << 32))
  88 #define IRIS_MEMZONE_DYNAMIC_START    (2ull * (1ull << 32))
  89 #define IRIS_MEMZONE_OTHER_START      (3ull * (1ull << 32))
  90
  91 #define IRIS_BINDER_ADDRESS IRIS_MEMZONE_SURFACE_START
  92 #define IRIS_BINDER_SIZE (64 * 1024)
  93
  94 #define IRIS_BORDER_COLOR_POOL_ADDRESS IRIS_MEMZONE_DYNAMIC_START
  95 #define IRIS_BORDER_COLOR_POOL_SIZE (64 * 1024)
  96
  97 struct iris_bo {
  98    /**
  99     * Size in bytes of the buffer object.
 100     *
 101     * The size may be larger than the size originally requested for the
 102     * allocation, such as being aligned to page size.
 103     */
 104    uint64_t size;
 105
 106    /** Buffer manager context associated with this buffer object */
 107    struct iris_bufmgr *bufmgr;
 108
 109    /** The GEM handle for this buffer object. */
 110    uint32_t gem_handle;
 111
 112    /**
 113     * Virtual address of the buffer inside the PPGTT (Per-Process Graphics
 114     * Translation Table).
 115     *
 116     * Although each hardware context has its own VMA, we assign BO's to the
 117     * same address in all contexts, for simplicity.
 118     */
 119    uint64_t gtt_offset;
 120
 121    /**
 122     * The validation list index for this buffer, or -1 when not in a batch.
 123     * Note that a single buffer may be in multiple batches (contexts), and
 124     * this is a global field, which refers to the last batch using the BO.
 125     * It should not be considered authoritative, but can be used to avoid a
 126     * linear walk of the validation list in the common case by guessing that
 127     * exec_bos[bo->index] == bo and confirming whether that's the case.
 128     */
 129    unsigned index;
 130
 131    /**
 132     * Boolean of whether the GPU is definitely not accessing the buffer.
 133     *
 134     * This is only valid when reusable, since non-reusable
 135     * buffers are those that have been shared with other
 136     * processes, so we don't know their state.
 137     */
 138    bool idle;
 139
 140    int refcount;
 141    const char *name;
 142
 143    uint64_t kflags;
 144
 145    /**
 146     * Kenel-assigned global name for this object
 147     *
 148     * List contains both flink named and prime fd'd objects
 149     */
 150    unsigned global_name;
 151
 152    /**
 153     * Current tiling mode
 154     */
 155    uint32_t tiling_mode;
 156    uint32_t swizzle_mode;
 157    uint32_t stride;
 158
 159    time_t free_time;
 160
 161    /** Mapped address for the buffer, saved across map/unmap cycles */
 162    void *map_cpu;
 163    /** GTT virtual address for the buffer, saved across map/unmap cycles */
 164    void *map_gtt;
 165    /** WC CPU address for the buffer, saved across map/unmap cycles */
 166    void *map_wc;
 167
 168    /** BO cache list */
 169    struct list_head head;
 170
 171    /**
 172     * Boolean of whether this buffer can be re-used
 173     */
 174    bool reusable;
 175
 176    /**
 177     * Boolean of whether this buffer has been shared with an external client.
 178     */
 179    bool external;
 180
 181    /**
 182     * Boolean of whether this buffer is cache coherent
 183     */
 184    bool cache_coherent;
 185
 186    /**
 187     * Boolean of whether this buffer points into user memory
 188     */
 189    bool userptr;
 190
 191    /** Pre-computed hash using _mesa_hash_pointer for cache tracking sets */
 192    uint32_t hash;
 193 };
 194
 195 #define BO_ALLOC_ZEROED     (1<<0)
 196
 197 /**
 198  * Allocate a buffer object.
 199  *
 200  * Buffer objects are not necessarily initially mapped into CPU virtual
 201  * address space or graphics device aperture.  They must be mapped
 202  * using iris_bo_map() to be used by the CPU.
 203  */
 204 struct iris_bo *iris_bo_alloc(struct iris_bufmgr *bufmgr,
 205                               const char *name,
 206                               uint64_t size,
 207                               enum iris_memory_zone memzone);
 208
 209 /**
 210  * Allocate a tiled buffer object.
 211  *
 212  * Alignment for tiled objects is set automatically; the 'flags'
 213  * argument provides a hint about how the object will be used initially.
 214  *
 215  * Valid tiling formats are:
 216  *  I915_TILING_NONE
 217  *  I915_TILING_X
 218  *  I915_TILING_Y
 219  */
 220 struct iris_bo *iris_bo_alloc_tiled(struct iris_bufmgr *bufmgr,
 221                                     const char *name,
 222                                     uint64_t size,
 223                                     uint32_t tiling_mode,
 224                                     uint32_t pitch,
 225                                     unsigned flags,
 226                                     enum iris_memory_zone memzone);
 227
 228 struct iris_bo *
 229 iris_bo_create_userptr(struct iris_bufmgr *bufmgr, const char *name,
 230                        void *ptr, size_t size,
 231                        enum iris_memory_zone memzone);
 232
 233 /** Takes a reference on a buffer object */
 234 static inline void
 235 iris_bo_reference(struct iris_bo *bo)
 236 {
 237    p_atomic_inc(&bo->refcount);
 238 }
 239
 240 /**
 241  * Releases a reference on a buffer object, freeing the data if
 242  * no references remain.
 243  */
 244 void iris_bo_unreference(struct iris_bo *bo);
 245
 246 #define MAP_READ          PIPE_TRANSFER_READ
 247 #define MAP_WRITE         PIPE_TRANSFER_WRITE
 248 #define MAP_ASYNC         PIPE_TRANSFER_UNSYNCHRONIZED
 249 #define MAP_PERSISTENT    PIPE_TRANSFER_PERSISTENT
 250 #define MAP_COHERENT      PIPE_TRANSFER_COHERENT
 251 /* internal */
 252 #define MAP_INTERNAL_MASK (0xff << 24)
 253 #define MAP_RAW           (0x01 << 24)
 254
 255 /**
 256  * Maps the buffer into userspace.
 257  *
 258  * This function will block waiting for any existing execution on the
 259  * buffer to complete, first.  The resulting mapping is returned.
 260  */
 261 MUST_CHECK void *iris_bo_map(struct pipe_debug_callback *dbg,
 262                              struct iris_bo *bo, unsigned flags);
 263
 264 /**
 265  * Reduces the refcount on the userspace mapping of the buffer
 266  * object.
 267  */
 268 static inline int iris_bo_unmap(struct iris_bo *bo) { return 0; }
 269
 270 /**
 271  * Waits for rendering to an object by the GPU to have completed.
 272  *
 273  * This is not required for any access to the BO by bo_map,
 274  * bo_subdata, etc.  It is merely a way for the driver to implement
 275  * glFinish.
 276  */
 277 void iris_bo_wait_rendering(struct iris_bo *bo);
 278
 279 /**
 280  * Tears down the buffer manager instance.
 281  */
 282 void iris_bufmgr_destroy(struct iris_bufmgr *bufmgr);
 283
 284 /**
 285  * Get the current tiling (and resulting swizzling) mode for the bo.
 286  *
 287  * \param buf Buffer to get tiling mode for
 288  * \param tiling_mode returned tiling mode
 289  * \param swizzle_mode returned swizzling mode
 290  */
 291 int iris_bo_get_tiling(struct iris_bo *bo, uint32_t *tiling_mode,
 292                       uint32_t *swizzle_mode);
 293
 294 /**
 295  * Create a visible name for a buffer which can be used by other apps
 296  *
 297  * \param buf Buffer to create a name for
 298  * \param name Returned name
 299  */
 300 int iris_bo_flink(struct iris_bo *bo, uint32_t *name);
 301
 302 /**
 303  * Returns 1 if mapping the buffer for write could cause the process
 304  * to block, due to the object being active in the GPU.
 305  */
 306 int iris_bo_busy(struct iris_bo *bo);
 307
 308 /**
 309  * Specify the volatility of the buffer.
 310  * \param bo Buffer to create a name for
 311  * \param madv The purgeable status
 312  *
 313  * Use I915_MADV_DONTNEED to mark the buffer as purgeable, and it will be
 314  * reclaimed under memory pressure. If you subsequently require the buffer,
 315  * then you must pass I915_MADV_WILLNEED to mark the buffer as required.
 316  *
 317  * Returns 1 if the buffer was retained, or 0 if it was discarded whilst
 318  * marked as I915_MADV_DONTNEED.
 319  */
 320 int iris_bo_madvise(struct iris_bo *bo, int madv);
 321
 322 /* drm_bacon_bufmgr_gem.c */
 323 struct iris_bufmgr *iris_bufmgr_init(struct gen_device_info *devinfo, int fd);
 324 struct iris_bo *iris_bo_gem_create_from_name(struct iris_bufmgr *bufmgr,
 325                                              const char *name,
 326                                              unsigned handle);
 327 void iris_bufmgr_enable_reuse(struct iris_bufmgr *bufmgr);
 328
 329 int iris_bo_wait(struct iris_bo *bo, int64_t timeout_ns);
 330
 331 uint32_t iris_create_hw_context(struct iris_bufmgr *bufmgr);
 332
 333 #define IRIS_CONTEXT_LOW_PRIORITY    ((I915_CONTEXT_MIN_USER_PRIORITY-1)/2)
 334 #define IRIS_CONTEXT_MEDIUM_PRIORITY (I915_CONTEXT_DEFAULT_PRIORITY)
 335 #define IRIS_CONTEXT_HIGH_PRIORITY   ((I915_CONTEXT_MAX_USER_PRIORITY+1)/2)
 336
 337 int iris_hw_context_set_priority(struct iris_bufmgr *bufmgr,
 338                                  uint32_t ctx_id, int priority);
 339
 340 void iris_destroy_hw_context(struct iris_bufmgr *bufmgr, uint32_t ctx_id);
 341
 342 int iris_bo_export_dmabuf(struct iris_bo *bo, int *prime_fd);
 343 struct iris_bo *iris_bo_import_dmabuf(struct iris_bufmgr *bufmgr, int prime_fd);
 344
 345 uint32_t iris_bo_export_gem_handle(struct iris_bo *bo);
 346
 347 int iris_reg_read(struct iris_bufmgr *bufmgr, uint32_t offset, uint64_t *out);
 348
 349 int drm_ioctl(int fd, unsigned long request, void *arg);
 350
 351 /**
 352  * Returns the BO's address relative to the appropriate base address.
 353  *
 354  * All of our base addresses are programmed to the start of a 4GB region,
 355  * so simply returning the bottom 32 bits of the BO address will give us
 356  * the offset from whatever base address corresponds to that memory region.
 357  */
 358 static inline uint32_t
 359 iris_bo_offset_from_base_address(struct iris_bo *bo)
 360 {
 361    /* This only works for buffers in the memory zones corresponding to a
 362     * base address - the top, unbounded memory zone doesn't have a base.
 363     */
 364    assert(bo->gtt_offset < IRIS_MEMZONE_OTHER_START);
 365    return bo->gtt_offset;
 366 }
 367
 368 #endif /* IRIS_BUFMGR_H */