2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "pipe/p_context.h"
28 #include "pipe/p_screen.h"
29 #include "util/u_inlines.h"
30 #include "util/u_format.h"
31 #include "util/u_upload_mgr.h"
32 #include "util/ralloc.h"
33 #include "iris_context.h"
34 #include "iris_resource.h"
35 #include "iris_screen.h"
36 #include "intel/compiler/brw_compiler.h"
37 #include "util/format_srgb.h"
40 iris_is_color_fast_clear_compatible(struct iris_context
*ice
,
41 enum isl_format format
,
42 const union isl_color_value color
)
44 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
45 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
47 if (isl_format_has_int_channel(format
)) {
48 perf_debug(&ice
->dbg
, "Integer fast clear not enabled for %s",
49 isl_format_get_name(format
));
53 for (int i
= 0; i
< 4; i
++) {
54 if (!isl_format_has_color_component(format
, i
)) {
58 if (devinfo
->gen
< 9 &&
59 color
.f32
[i
] != 0.0f
&& color
.f32
[i
] != 1.0f
) {
68 can_fast_clear_color(struct iris_context
*ice
,
69 struct pipe_resource
*p_res
,
71 const struct pipe_box
*box
,
72 enum isl_format format
,
73 enum isl_format render_format
,
74 union isl_color_value color
)
76 struct iris_resource
*res
= (void *) p_res
;
78 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
79 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
81 if (res
->aux
.usage
== ISL_AUX_USAGE_NONE
)
84 /* Surface state can only record one fast clear color value. Therefore
85 * unless different levels/layers agree on the color it can be used to
86 * represent only single level/layer. Here it will be reserved for the
87 * first slice (level 0, layer 0).
89 if (level
> 0 || box
->z
> 0 || box
->depth
> 1)
92 /* Check for partial clear */
93 if (box
->x
> 0 || box
->y
> 0 ||
94 box
->width
< p_res
->width0
||
95 box
->height
< p_res
->height0
) {
99 /* We store clear colors as floats or uints as needed. If there are
100 * texture views in play, the formats will not properly be respected
101 * during resolves because the resolve operations only know about the
102 * resource and not the renderbuffer.
104 if (isl_format_srgb_to_linear(render_format
) !=
105 isl_format_srgb_to_linear(format
)) {
109 /* XXX: if (irb->mt->supports_fast_clear)
110 * see intel_miptree_create_for_dri_image()
113 if (!iris_is_color_fast_clear_compatible(ice
, format
, color
))
119 static union isl_color_value
120 convert_fast_clear_color(struct iris_context
*ice
,
121 struct iris_resource
*res
,
122 enum isl_format render_format
,
123 const union isl_color_value color
)
125 union isl_color_value override_color
= color
;
126 struct pipe_resource
*p_res
= (void *) res
;
128 const enum pipe_format format
= p_res
->format
;
129 const struct util_format_description
*desc
=
130 util_format_description(format
);
131 unsigned colormask
= util_format_colormask(desc
);
133 if (util_format_is_intensity(format
) ||
134 util_format_is_luminance(format
) ||
135 util_format_is_luminance_alpha(format
)) {
136 override_color
.u32
[1] = override_color
.u32
[0];
137 override_color
.u32
[2] = override_color
.u32
[0];
138 if (util_format_is_intensity(format
))
139 override_color
.u32
[3] = override_color
.u32
[0];
141 for (int chan
= 0; chan
< 3; chan
++) {
142 if (!(colormask
& (1 << chan
)))
143 override_color
.u32
[chan
] = 0;
147 if (util_format_is_unorm(format
)) {
148 for (int i
= 0; i
< 4; i
++)
149 override_color
.f32
[i
] = CLAMP(override_color
.f32
[i
], 0.0f
, 1.0f
);
150 } else if (util_format_is_snorm(format
)) {
151 for (int i
= 0; i
< 4; i
++)
152 override_color
.f32
[i
] = CLAMP(override_color
.f32
[i
], -1.0f
, 1.0f
);
153 } else if (util_format_is_pure_uint(format
)) {
154 for (int i
= 0; i
< 4; i
++) {
155 unsigned bits
= util_format_get_component_bits(
156 format
, UTIL_FORMAT_COLORSPACE_RGB
, i
);
158 uint32_t max
= (1u << bits
) - 1;
159 override_color
.u32
[i
] = MIN2(override_color
.u32
[i
], max
);
162 } else if (util_format_is_pure_sint(format
)) {
163 for (int i
= 0; i
< 4; i
++) {
164 unsigned bits
= util_format_get_component_bits(
165 format
, UTIL_FORMAT_COLORSPACE_RGB
, i
);
167 int32_t max
= (1 << (bits
- 1)) - 1;
168 int32_t min
= -(1 << (bits
- 1));
169 override_color
.i32
[i
] = CLAMP(override_color
.i32
[i
], min
, max
);
172 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
||
173 format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
174 /* these packed float formats only store unsigned values */
175 for (int i
= 0; i
< 4; i
++)
176 override_color
.f32
[i
] = MAX2(override_color
.f32
[i
], 0.0f
);
179 if (!(colormask
& 1 << 3)) {
180 if (util_format_is_pure_integer(format
))
181 override_color
.u32
[3] = 1;
183 override_color
.f32
[3] = 1.0f
;
186 /* Handle linear to SRGB conversion */
187 if (isl_format_is_srgb(render_format
)) {
188 for (int i
= 0; i
< 3; i
++) {
189 override_color
.f32
[i
] =
190 util_format_linear_to_srgb_float(override_color
.f32
[i
]);
194 return override_color
;
198 fast_clear_color(struct iris_context
*ice
,
199 struct iris_resource
*res
,
201 const struct pipe_box
*box
,
202 enum isl_format format
,
203 union isl_color_value color
,
204 enum blorp_batch_flags blorp_flags
)
206 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
207 struct pipe_resource
*p_res
= (void *) res
;
208 const enum isl_aux_state aux_state
=
209 iris_resource_get_aux_state(res
, level
, box
->z
);
211 color
= convert_fast_clear_color(ice
, res
, format
, color
);
213 bool color_changed
= !!memcmp(&res
->aux
.clear_color
, &color
,
217 /* We decided that we are going to fast clear, and the color is
218 * changing. But if we have a predicate bit set, the predication
219 * affects whether we should clear or not, and if we shouldn't, we
220 * also shouldn't update the clear color.
222 * However, we can't simply predicate-update the clear color (the
223 * commands don't support that). And we would lose track of the
224 * color, preventing us from doing some optimizations later.
226 * Since changing the clear color when the predication bit is enabled
227 * is not something that should happen often, we stall on the CPU here
228 * to resolve the predication, and then proceed.
230 iris_resolve_conditional_render(ice
);
231 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
235 iris_resource_set_clear_color(ice
, res
, color
);
237 /* If the buffer is already in ISL_AUX_STATE_CLEAR, and the color hasn't
238 * changed, the clear is redundant and can be skipped.
240 if (!color_changed
&& aux_state
== ISL_AUX_STATE_CLEAR
)
243 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
245 * "Any transition from any value in {Clear, Render, Resolve} to a
246 * different value in {Clear, Render, Resolve} requires end of pipe
249 * In other words, fast clear ops are not properly synchronized with
250 * other drawing. We need to use a PIPE_CONTROL to ensure that the
251 * contents of the previous draw hit the render target before we resolve
252 * and again afterwards to ensure that the resolve is complete before we
253 * do any more regular drawing.
255 iris_emit_end_of_pipe_sync(batch
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
257 /* If we reach this point, we need to fast clear to change the state to
258 * ISL_AUX_STATE_CLEAR, or to update the fast clear color (or both).
260 blorp_flags
|= color_changed
? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
;
262 struct blorp_batch blorp_batch
;
263 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
265 struct blorp_surf surf
;
266 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, p_res
, res
->aux
.usage
,
269 /* In newer gens (> 9), the hardware will do a linear -> sRGB conversion of
270 * the clear color during the fast clear, if the surface format is of sRGB
271 * type. We use the linear version of the surface format here to prevent
272 * that from happening, since we already do our own linear -> sRGB
273 * conversion in convert_fast_clear_color().
275 blorp_fast_clear(&blorp_batch
, &surf
, isl_format_srgb_to_linear(format
),
276 level
, box
->z
, box
->depth
,
277 box
->x
, box
->y
, box
->x
+ box
->width
,
278 box
->y
+ box
->height
);
279 blorp_batch_finish(&blorp_batch
);
280 iris_emit_end_of_pipe_sync(batch
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
282 iris_resource_set_aux_state(ice
, res
, level
, box
->z
,
283 box
->depth
, ISL_AUX_STATE_CLEAR
);
284 ice
->state
.dirty
|= IRIS_ALL_DIRTY_BINDINGS
;
289 clear_color(struct iris_context
*ice
,
290 struct pipe_resource
*p_res
,
292 const struct pipe_box
*box
,
293 bool render_condition_enabled
,
294 enum isl_format format
,
295 struct isl_swizzle swizzle
,
296 union isl_color_value color
)
298 struct iris_resource
*res
= (void *) p_res
;
300 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
301 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
302 enum blorp_batch_flags blorp_flags
= 0;
304 if (render_condition_enabled
) {
305 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
308 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
)
309 blorp_flags
|= BLORP_BATCH_PREDICATE_ENABLE
;
312 if (p_res
->target
== PIPE_BUFFER
)
313 util_range_add(&res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
315 iris_batch_maybe_flush(batch
, 1500);
317 bool can_fast_clear
= can_fast_clear_color(ice
, p_res
, level
, box
,
318 res
->surf
.format
, format
, color
);
319 if (can_fast_clear
) {
320 fast_clear_color(ice
, res
, level
, box
, format
, color
,
325 bool color_write_disable
[4] = { false, false, false, false };
326 enum isl_aux_usage aux_usage
=
327 iris_resource_render_aux_usage(ice
, res
, format
,
330 iris_resource_prepare_render(ice
, batch
, res
, level
,
331 box
->z
, box
->depth
, aux_usage
);
333 struct blorp_surf surf
;
334 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, p_res
, aux_usage
, level
,
337 struct blorp_batch blorp_batch
;
338 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
340 if (!isl_format_supports_rendering(devinfo
, format
) &&
341 isl_format_is_rgbx(format
))
342 format
= isl_format_rgbx_to_rgba(format
);
344 blorp_clear(&blorp_batch
, &surf
, format
, swizzle
,
345 level
, box
->z
, box
->depth
, box
->x
, box
->y
,
346 box
->x
+ box
->width
, box
->y
+ box
->height
,
347 color
, color_write_disable
);
349 blorp_batch_finish(&blorp_batch
);
350 iris_flush_and_dirty_for_history(ice
, batch
, res
);
352 iris_resource_finish_render(ice
, res
, level
,
353 box
->z
, box
->depth
, aux_usage
);
357 can_fast_clear_depth(struct iris_context
*ice
,
358 struct iris_resource
*res
,
360 const struct pipe_box
*box
,
363 struct pipe_resource
*p_res
= (void *) res
;
365 /* Check for partial clears */
366 if (box
->x
> 0 || box
->y
> 0 ||
367 box
->width
< u_minify(p_res
->width0
, level
) ||
368 box
->height
< u_minify(p_res
->height0
, level
)) {
372 if (!(res
->aux
.has_hiz
& (1 << level
)))
379 fast_clear_depth(struct iris_context
*ice
,
380 struct iris_resource
*res
,
382 const struct pipe_box
*box
,
385 struct pipe_resource
*p_res
= (void *) res
;
386 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
388 /* Quantize the clear value to what can be stored in the actual depth
389 * buffer. This makes the following check more accurate because it now
390 * checks if the actual depth bits will match. It also prevents us from
391 * getting a too-accurate depth value during depth testing or when sampling
394 const unsigned nbits
= p_res
->format
== PIPE_FORMAT_Z16_UNORM
? 16 : 24;
395 const uint32_t depth_max
= (1 << nbits
) - 1;
396 depth
= p_res
->format
== PIPE_FORMAT_Z32_FLOAT
? depth
:
397 (unsigned)(depth
* depth_max
) / (float)depth_max
;
399 bool update_clear_depth
= false;
401 /* If we're clearing to a new clear value, then we need to resolve any clear
402 * flags out of the HiZ buffer into the real depth buffer.
404 if (res
->aux
.clear_color
.f32
[0] != depth
) {
405 /* We decided that we are going to fast clear, and the color is
406 * changing. But if we have a predicate bit set, the predication
407 * affects whether we should clear or not, and if we shouldn't, we
408 * also shouldn't update the clear color.
410 * However, we can't simply predicate-update the clear color (the
411 * commands don't support that). And we would lose track of the
412 * color, preventing us from doing some optimizations later.
414 * For depth clears, things are even more complicated, because here we
415 * resolve the other levels/layers if they have a different color than
416 * the current one. That resolve can be predicated, but we also set those
417 * layers as ISL_AUX_STATE_RESOLVED, and this can't be predicated.
418 * Keeping track of the aux state when predication is involved is just
419 * even more complex, so the easiest thing to do when the fast clear
420 * depth is changing is to stall on the CPU and resolve the predication.
422 iris_resolve_conditional_render(ice
);
423 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
426 for (unsigned res_level
= 0; res_level
< res
->surf
.levels
; res_level
++) {
427 if (!(res
->aux
.has_hiz
& (1 << res_level
)))
430 const unsigned level_layers
=
431 iris_get_num_logical_layers(res
, res_level
);
432 for (unsigned layer
= 0; layer
< level_layers
; layer
++) {
433 if (res_level
== level
&&
435 layer
< box
->z
+ box
->depth
) {
436 /* We're going to clear this layer anyway. Leave it alone. */
440 enum isl_aux_state aux_state
=
441 iris_resource_get_aux_state(res
, res_level
, layer
);
443 if (aux_state
!= ISL_AUX_STATE_CLEAR
&&
444 aux_state
!= ISL_AUX_STATE_COMPRESSED_CLEAR
) {
445 /* This slice doesn't have any fast-cleared bits. */
449 /* If we got here, then the level may have fast-clear bits that
450 * use the old clear value. We need to do a depth resolve to get
451 * rid of their use of the clear value before we can change it.
452 * Fortunately, few applications ever change their depth clear
453 * value so this shouldn't happen often.
455 iris_hiz_exec(ice
, batch
, res
, res_level
, layer
, 1,
456 ISL_AUX_OP_FULL_RESOLVE
, false);
457 iris_resource_set_aux_state(ice
, res
, res_level
, layer
, 1,
458 ISL_AUX_STATE_RESOLVED
);
461 const union isl_color_value clear_value
= { .f32
= {depth
, } };
462 iris_resource_set_clear_color(ice
, res
, clear_value
);
463 update_clear_depth
= true;
466 for (unsigned l
= 0; l
< box
->depth
; l
++) {
467 enum isl_aux_state aux_state
=
468 iris_resource_get_aux_state(res
, level
, box
->z
+ l
);
469 if (aux_state
!= ISL_AUX_STATE_CLEAR
) {
470 iris_hiz_exec(ice
, batch
, res
, level
,
471 box
->z
+ l
, 1, ISL_AUX_OP_FAST_CLEAR
,
476 iris_resource_set_aux_state(ice
, res
, level
, box
->z
, box
->depth
,
477 ISL_AUX_STATE_CLEAR
);
478 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
482 clear_depth_stencil(struct iris_context
*ice
,
483 struct pipe_resource
*p_res
,
485 const struct pipe_box
*box
,
486 bool render_condition_enabled
,
492 struct iris_resource
*res
= (void *) p_res
;
494 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
495 enum blorp_batch_flags blorp_flags
= 0;
497 if (render_condition_enabled
) {
498 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
501 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
)
502 blorp_flags
|= BLORP_BATCH_PREDICATE_ENABLE
;
505 iris_batch_maybe_flush(batch
, 1500);
507 struct iris_resource
*z_res
;
508 struct iris_resource
*stencil_res
;
509 struct blorp_surf z_surf
;
510 struct blorp_surf stencil_surf
;
512 iris_get_depth_stencil_resources(p_res
, &z_res
, &stencil_res
);
513 if (z_res
&& clear_depth
&&
514 can_fast_clear_depth(ice
, z_res
, level
, box
, depth
)) {
515 fast_clear_depth(ice
, z_res
, level
, box
, depth
);
516 iris_flush_and_dirty_for_history(ice
, batch
, res
);
521 /* At this point, we might have fast cleared the depth buffer. So if there's
522 * no stencil clear pending, return early.
524 if (!(clear_depth
|| clear_stencil
)) {
529 iris_resource_prepare_depth(ice
, batch
, z_res
, level
, box
->z
, box
->depth
);
530 iris_blorp_surf_for_resource(&ice
->vtbl
, &z_surf
, &z_res
->base
,
531 z_res
->aux
.usage
, level
, true);
534 struct blorp_batch blorp_batch
;
535 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
538 iris_blorp_surf_for_resource(&ice
->vtbl
, &stencil_surf
,
539 &stencil_res
->base
, stencil_res
->aux
.usage
,
543 blorp_clear_depth_stencil(&blorp_batch
, &z_surf
, &stencil_surf
,
544 level
, box
->z
, box
->depth
,
547 box
->y
+ box
->height
,
548 clear_depth
&& z_res
, depth
,
549 clear_stencil
&& stencil_res
? 0xff : 0, stencil
);
551 blorp_batch_finish(&blorp_batch
);
552 iris_flush_and_dirty_for_history(ice
, batch
, res
);
555 iris_resource_finish_depth(ice
, z_res
, level
,
556 box
->z
, box
->depth
, true);
561 * The pipe->clear() driver hook.
563 * This clears buffers attached to the current draw framebuffer.
566 iris_clear(struct pipe_context
*ctx
,
568 const union pipe_color_union
*p_color
,
572 struct iris_context
*ice
= (void *) ctx
;
573 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
575 assert(buffers
!= 0);
577 if (buffers
& PIPE_CLEAR_DEPTHSTENCIL
) {
578 struct pipe_surface
*psurf
= cso_fb
->zsbuf
;
579 struct pipe_box box
= {
580 .width
= cso_fb
->width
,
581 .height
= cso_fb
->height
,
582 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1,
583 .z
= psurf
->u
.tex
.first_layer
,
586 clear_depth_stencil(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
, true,
587 buffers
& PIPE_CLEAR_DEPTH
,
588 buffers
& PIPE_CLEAR_STENCIL
,
592 if (buffers
& PIPE_CLEAR_COLOR
) {
593 /* pipe_color_union and isl_color_value are interchangeable */
594 union isl_color_value
*color
= (void *) p_color
;
596 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
597 if (buffers
& (PIPE_CLEAR_COLOR0
<< i
)) {
598 struct pipe_surface
*psurf
= cso_fb
->cbufs
[i
];
599 struct iris_surface
*isurf
= (void *) psurf
;
600 struct pipe_box box
= {
601 .width
= cso_fb
->width
,
602 .height
= cso_fb
->height
,
603 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1,
604 .z
= psurf
->u
.tex
.first_layer
,
607 clear_color(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
608 true, isurf
->view
.format
, isurf
->view
.swizzle
,
616 * The pipe->clear_texture() driver hook.
618 * This clears the given texture resource.
621 iris_clear_texture(struct pipe_context
*ctx
,
622 struct pipe_resource
*p_res
,
624 const struct pipe_box
*box
,
627 struct iris_context
*ice
= (void *) ctx
;
628 struct iris_screen
*screen
= (void *) ctx
->screen
;
629 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
631 if (util_format_is_depth_or_stencil(p_res
->format
)) {
632 const struct util_format_description
*fmt_desc
=
633 util_format_description(p_res
->format
);
638 if (fmt_desc
->unpack_z_float
)
639 fmt_desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
641 if (fmt_desc
->unpack_s_8uint
)
642 fmt_desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
644 clear_depth_stencil(ice
, p_res
, level
, box
, true, true, true,
647 union isl_color_value color
;
648 struct iris_resource
*res
= (void *) p_res
;
649 enum isl_format format
= res
->surf
.format
;
651 if (!isl_format_supports_rendering(devinfo
, format
)) {
652 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
653 // XXX: actually just get_copy_format_for_bpb from BLORP
654 // XXX: don't cut and paste this
656 case 8: format
= ISL_FORMAT_R8_UINT
; break;
657 case 16: format
= ISL_FORMAT_R8G8_UINT
; break;
658 case 24: format
= ISL_FORMAT_R8G8B8_UINT
; break;
659 case 32: format
= ISL_FORMAT_R8G8B8A8_UINT
; break;
660 case 48: format
= ISL_FORMAT_R16G16B16_UINT
; break;
661 case 64: format
= ISL_FORMAT_R16G16B16A16_UINT
; break;
662 case 96: format
= ISL_FORMAT_R32G32B32_UINT
; break;
663 case 128: format
= ISL_FORMAT_R32G32B32A32_UINT
; break;
665 unreachable("Unknown format bpb");
668 /* No aux surfaces for non-renderable surfaces */
669 assert(res
->aux
.usage
== ISL_AUX_USAGE_NONE
);
672 isl_color_value_unpack(&color
, format
, data
);
674 clear_color(ice
, p_res
, level
, box
, true, format
,
675 ISL_SWIZZLE_IDENTITY
, color
);
680 * The pipe->clear_render_target() driver hook.
682 * This clears the given render target surface.
685 iris_clear_render_target(struct pipe_context
*ctx
,
686 struct pipe_surface
*psurf
,
687 const union pipe_color_union
*p_color
,
688 unsigned dst_x
, unsigned dst_y
,
689 unsigned width
, unsigned height
,
690 bool render_condition_enabled
)
692 struct iris_context
*ice
= (void *) ctx
;
693 struct iris_surface
*isurf
= (void *) psurf
;
694 struct pipe_box box
= {
697 .z
= psurf
->u
.tex
.first_layer
,
700 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1
703 /* pipe_color_union and isl_color_value are interchangeable */
704 union isl_color_value
*color
= (void *) p_color
;
706 clear_color(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
707 render_condition_enabled
,
708 isurf
->view
.format
, isurf
->view
.swizzle
, *color
);
712 * The pipe->clear_depth_stencil() driver hook.
714 * This clears the given depth/stencil surface.
717 iris_clear_depth_stencil(struct pipe_context
*ctx
,
718 struct pipe_surface
*psurf
,
722 unsigned dst_x
, unsigned dst_y
,
723 unsigned width
, unsigned height
,
724 bool render_condition_enabled
)
726 struct iris_context
*ice
= (void *) ctx
;
727 struct pipe_box box
= {
730 .z
= psurf
->u
.tex
.first_layer
,
733 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1
736 assert(util_format_is_depth_or_stencil(psurf
->texture
->format
));
738 clear_depth_stencil(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
739 render_condition_enabled
,
740 flags
& PIPE_CLEAR_DEPTH
, flags
& PIPE_CLEAR_STENCIL
,
745 iris_init_clear_functions(struct pipe_context
*ctx
)
747 ctx
->clear
= iris_clear
;
748 ctx
->clear_texture
= iris_clear_texture
;
749 ctx
->clear_render_target
= iris_clear_render_target
;
750 ctx
->clear_depth_stencil
= iris_clear_depth_stencil
;