src/gallium/drivers/iris/iris_clear.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "pipe/p_context.h"
  28 #include "pipe/p_screen.h"
  29 #include "util/u_inlines.h"
  30 #include "util/u_format.h"
  31 #include "util/u_upload_mgr.h"
  32 #include "util/ralloc.h"
  33 #include "iris_context.h"
  34 #include "iris_resource.h"
  35 #include "iris_screen.h"
  36 #include "intel/compiler/brw_compiler.h"
  37
  38 static void
  39 clear_color(struct iris_context *ice,
  40             struct pipe_resource *p_res,
  41             unsigned level,
  42             const struct pipe_box *box,
  43             bool render_condition_enabled,
  44             enum isl_format format,
  45             struct isl_swizzle swizzle,
  46             union isl_color_value color)
  47 {
  48    struct iris_resource *res = (void *) p_res;
  49
  50    struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
  51    const struct gen_device_info *devinfo = &batch->screen->devinfo;
  52    enum blorp_batch_flags blorp_flags = 0;
  53
  54    if (render_condition_enabled) {
  55       if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER)
  56          return;
  57
  58       if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT)
  59          blorp_flags |= BLORP_BATCH_PREDICATE_ENABLE;
  60    }
  61
  62    iris_batch_maybe_flush(batch, 1500);
  63
  64    struct blorp_batch blorp_batch;
  65    blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags);
  66
  67    bool color_write_disable[4] = { false, false, false, false };
  68    enum isl_aux_usage aux_usage =
  69       iris_resource_render_aux_usage(ice, res, format,
  70                                      false, false);
  71
  72    iris_resource_prepare_render(ice, batch, res, level,
  73                                 box->z, box->depth, aux_usage);
  74
  75    struct blorp_surf surf;
  76    iris_blorp_surf_for_resource(&ice->vtbl, &surf, p_res, aux_usage, level,
  77                                 true);
  78
  79    if (!isl_format_supports_rendering(devinfo, format) &&
  80        isl_format_is_rgbx(format))
  81       format = isl_format_rgbx_to_rgba(format);
  82
  83    blorp_clear(&blorp_batch, &surf, format, swizzle,
  84                level, box->z, box->depth, box->x, box->y,
  85                box->x + box->width, box->y + box->height,
  86                color, color_write_disable);
  87
  88    blorp_batch_finish(&blorp_batch);
  89    iris_flush_and_dirty_for_history(ice, batch, res);
  90
  91    iris_resource_finish_render(ice, res, level,
  92                                box->z, box->depth, aux_usage);
  93 }
  94
  95
  96 static void
  97 clear_depth_stencil(struct iris_context *ice,
  98                     struct pipe_resource *p_res,
  99                     unsigned level,
 100                     const struct pipe_box *box,
 101                     bool render_condition_enabled,
 102                     bool clear_depth,
 103                     bool clear_stencil,
 104                     float depth,
 105                     uint8_t stencil)
 106 {
 107    struct iris_resource *res = (void *) p_res;
 108
 109    struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
 110    enum blorp_batch_flags blorp_flags = 0;
 111
 112    if (render_condition_enabled) {
 113       if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER)
 114          return;
 115
 116       if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT)
 117          blorp_flags |= BLORP_BATCH_PREDICATE_ENABLE;
 118    }
 119
 120    iris_batch_maybe_flush(batch, 1500);
 121
 122    struct blorp_batch blorp_batch;
 123    blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags);
 124
 125    struct iris_resource *z_res;
 126    struct iris_resource *stencil_res;
 127    struct blorp_surf z_surf;
 128    struct blorp_surf stencil_surf;
 129
 130    iris_get_depth_stencil_resources(p_res, &z_res, &stencil_res);
 131
 132    if (z_res) {
 133       iris_resource_prepare_depth(ice, batch, z_res, level, box->z, box->depth);
 134       iris_blorp_surf_for_resource(&ice->vtbl, &z_surf, &z_res->base,
 135                                    z_res->aux.usage, level, true);
 136    }
 137
 138    if (stencil_res) {
 139       iris_blorp_surf_for_resource(&ice->vtbl, &stencil_surf,
 140                                    &stencil_res->base, stencil_res->aux.usage,
 141                                    level, true);
 142    }
 143
 144    blorp_clear_depth_stencil(&blorp_batch, &z_surf, &stencil_surf,
 145                              level, box->z, box->depth,
 146                              box->x, box->y,
 147                              box->x + box->width,
 148                              box->y + box->height,
 149                              clear_depth && z_res, depth,
 150                              clear_stencil && stencil_res ? 0xff : 0, stencil);
 151
 152    blorp_batch_finish(&blorp_batch);
 153    iris_flush_and_dirty_for_history(ice, batch, res);
 154
 155    if (z_res) {
 156       iris_resource_finish_depth(ice, z_res, level,
 157                                  box->z, box->depth, true);
 158    }
 159 }
 160
 161 /**
 162  * The pipe->clear() driver hook.
 163  *
 164  * This clears buffers attached to the current draw framebuffer.
 165  */
 166 static void
 167 iris_clear(struct pipe_context *ctx,
 168            unsigned buffers,
 169            const union pipe_color_union *p_color,
 170            double depth,
 171            unsigned stencil)
 172 {
 173    struct iris_context *ice = (void *) ctx;
 174    struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
 175
 176    assert(buffers != 0);
 177
 178    if (buffers & PIPE_CLEAR_DEPTHSTENCIL) {
 179       struct pipe_surface *psurf = cso_fb->zsbuf;
 180       struct pipe_box box = {
 181          .width = cso_fb->width,
 182          .height = cso_fb->height,
 183          .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1,
 184          .z = psurf->u.tex.first_layer,
 185       };
 186
 187       clear_depth_stencil(ice, psurf->texture, psurf->u.tex.level, &box, true,
 188                           buffers & PIPE_CLEAR_DEPTH,
 189                           buffers & PIPE_CLEAR_STENCIL,
 190                           depth, stencil);
 191    }
 192
 193    if (buffers & PIPE_CLEAR_COLOR) {
 194       /* pipe_color_union and isl_color_value are interchangeable */
 195       union isl_color_value *color = (void *) p_color;
 196
 197       for (unsigned i = 0; i < cso_fb->nr_cbufs; i++) {
 198          if (buffers & (PIPE_CLEAR_COLOR0 << i)) {
 199             struct pipe_surface *psurf = cso_fb->cbufs[i];
 200             struct iris_surface *isurf = (void *) psurf;
 201             struct pipe_box box = {
 202                .width = cso_fb->width,
 203                .height = cso_fb->height,
 204                .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1,
 205                .z = psurf->u.tex.first_layer,
 206             };
 207
 208             clear_color(ice, psurf->texture, psurf->u.tex.level, &box,
 209                         true, isurf->view.format, isurf->view.swizzle,
 210                         *color);
 211          }
 212       }
 213    }
 214 }
 215
 216 /**
 217  * The pipe->clear_texture() driver hook.
 218  *
 219  * This clears the given texture resource.
 220  */
 221 static void
 222 iris_clear_texture(struct pipe_context *ctx,
 223                    struct pipe_resource *p_res,
 224                    unsigned level,
 225                    const struct pipe_box *box,
 226                    const void *data)
 227 {
 228    struct iris_context *ice = (void *) ctx;
 229    struct iris_screen *screen = (void *) ctx->screen;
 230    const struct gen_device_info *devinfo = &screen->devinfo;
 231
 232    if (util_format_is_depth_or_stencil(p_res->format)) {
 233       const struct util_format_description *fmt_desc =
 234          util_format_description(p_res->format);
 235
 236       float depth = 0.0;
 237       uint8_t stencil = 0;
 238
 239       if (fmt_desc->unpack_z_float)
 240          fmt_desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
 241
 242       if (fmt_desc->unpack_s_8uint)
 243          fmt_desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
 244
 245       clear_depth_stencil(ice, p_res, level, box, true, true, true,
 246                           depth, stencil);
 247    } else {
 248       union isl_color_value color;
 249       struct iris_resource *res = (void *) p_res;
 250       enum isl_format format = res->surf.format;
 251
 252       if (!isl_format_supports_rendering(devinfo, format)) {
 253          const struct isl_format_layout *fmtl = isl_format_get_layout(format);
 254          // XXX: actually just get_copy_format_for_bpb from BLORP
 255          // XXX: don't cut and paste this
 256          switch (fmtl->bpb) {
 257          case 8:   format = ISL_FORMAT_R8_UINT;           break;
 258          case 16:  format = ISL_FORMAT_R8G8_UINT;         break;
 259          case 24:  format = ISL_FORMAT_R8G8B8_UINT;       break;
 260          case 32:  format = ISL_FORMAT_R8G8B8A8_UINT;     break;
 261          case 48:  format = ISL_FORMAT_R16G16B16_UINT;    break;
 262          case 64:  format = ISL_FORMAT_R16G16B16A16_UINT; break;
 263          case 96:  format = ISL_FORMAT_R32G32B32_UINT;    break;
 264          case 128: format = ISL_FORMAT_R32G32B32A32_UINT; break;
 265          default:
 266             unreachable("Unknown format bpb");
 267          }
 268
 269          /* No aux surfaces for non-renderable surfaces */
 270          assert(res->aux.usage == ISL_AUX_USAGE_NONE);
 271       }
 272
 273       isl_color_value_unpack(&color, format, data);
 274
 275       clear_color(ice, p_res, level, box, true, format,
 276                   ISL_SWIZZLE_IDENTITY, color);
 277    }
 278 }
 279
 280 /**
 281  * The pipe->clear_render_target() driver hook.
 282  *
 283  * This clears the given render target surface.
 284  */
 285 static void
 286 iris_clear_render_target(struct pipe_context *ctx,
 287                          struct pipe_surface *psurf,
 288                          const union pipe_color_union *p_color,
 289                          unsigned dst_x, unsigned dst_y,
 290                          unsigned width, unsigned height,
 291                          bool render_condition_enabled)
 292 {
 293    struct iris_context *ice = (void *) ctx;
 294    struct iris_surface *isurf = (void *) psurf;
 295    struct pipe_box box = {
 296       .x = dst_x,
 297       .y = dst_y,
 298       .z = psurf->u.tex.first_layer,
 299       .width = width,
 300       .height = height,
 301       .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1
 302    };
 303
 304    /* pipe_color_union and isl_color_value are interchangeable */
 305    union isl_color_value *color = (void *) p_color;
 306
 307    clear_color(ice, psurf->texture, psurf->u.tex.level, &box,
 308                render_condition_enabled,
 309                isurf->view.format, isurf->view.swizzle, *color);
 310 }
 311
 312 /**
 313  * The pipe->clear_depth_stencil() driver hook.
 314  *
 315  * This clears the given depth/stencil surface.
 316  */
 317 static void
 318 iris_clear_depth_stencil(struct pipe_context *ctx,
 319                          struct pipe_surface *psurf,
 320                          unsigned flags,
 321                          double depth,
 322                          unsigned stencil,
 323                          unsigned dst_x, unsigned dst_y,
 324                          unsigned width, unsigned height,
 325                          bool render_condition_enabled)
 326 {
 327    struct iris_context *ice = (void *) ctx;
 328    struct pipe_box box = {
 329       .x = dst_x,
 330       .y = dst_y,
 331       .z = psurf->u.tex.first_layer,
 332       .width = width,
 333       .height = height,
 334       .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1
 335    };
 336
 337    assert(util_format_is_depth_or_stencil(psurf->texture->format));
 338
 339    clear_depth_stencil(ice, psurf->texture, psurf->u.tex.level, &box,
 340                        render_condition_enabled,
 341                        flags & PIPE_CLEAR_DEPTH, flags & PIPE_CLEAR_STENCIL,
 342                        depth, stencil);
 343 }
 344
 345 void
 346 iris_init_clear_functions(struct pipe_context *ctx)
 347 {
 348    ctx->clear = iris_clear;
 349    ctx->clear_texture = iris_clear_texture;
 350    ctx->clear_render_target = iris_clear_render_target;
 351    ctx->clear_depth_stencil = iris_clear_depth_stencil;
 352 }