src/gallium/drivers/iris/iris_context.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_CONTEXT_H
  24 #define IRIS_CONTEXT_H
  25
  26 #include "pipe/p_context.h"
  27 #include "pipe/p_state.h"
  28 #include "util/u_debug.h"
  29 #include "intel/blorp/blorp.h"
  30 #include "intel/dev/gen_debug.h"
  31 #include "intel/compiler/brw_compiler.h"
  32 #include "iris_batch.h"
  33 #include "iris_binder.h"
  34 #include "iris_fence.h"
  35 #include "iris_resource.h"
  36 #include "iris_screen.h"
  37
  38 struct iris_bo;
  39 struct iris_context;
  40 struct blorp_batch;
  41 struct blorp_params;
  42
  43 #define IRIS_MAX_TEXTURE_BUFFER_SIZE (1 << 27)
  44 #define IRIS_MAX_TEXTURE_SAMPLERS 32
  45 /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */
  46 #define IRIS_MAX_ABOS 16
  47 #define IRIS_MAX_SSBOS 16
  48 #define IRIS_MAX_VIEWPORTS 16
  49 #define IRIS_MAX_CLIP_PLANES 8
  50
  51 enum iris_param_domain {
  52    BRW_PARAM_DOMAIN_BUILTIN = 0,
  53    BRW_PARAM_DOMAIN_IMAGE,
  54 };
  55
  56 #define BRW_PARAM(domain, val)   (BRW_PARAM_DOMAIN_##domain << 24 | (val))
  57 #define BRW_PARAM_DOMAIN(param)  ((uint32_t)(param) >> 24)
  58 #define BRW_PARAM_VALUE(param)   ((uint32_t)(param) & 0x00ffffff)
  59 #define BRW_PARAM_IMAGE(idx, offset) BRW_PARAM(IMAGE, ((idx) << 8) | (offset))
  60 #define BRW_PARAM_IMAGE_IDX(value)   (BRW_PARAM_VALUE(value) >> 8)
  61 #define BRW_PARAM_IMAGE_OFFSET(value)(BRW_PARAM_VALUE(value) & 0xf)
  62
  63 /**
  64  * Dirty flags.  When state changes, we flag some combination of these
  65  * to indicate that particular GPU commands need to be re-emitted.
  66  *
  67  * Each bit typically corresponds to a single 3DSTATE_* command packet, but
  68  * in rare cases they map to a group of related packets that need to be
  69  * emitted together.
  70  *
  71  * See iris_upload_render_state().
  72  */
  73 #define IRIS_DIRTY_COLOR_CALC_STATE         (1ull <<  0)
  74 #define IRIS_DIRTY_POLYGON_STIPPLE          (1ull <<  1)
  75 #define IRIS_DIRTY_SCISSOR_RECT             (1ull <<  2)
  76 #define IRIS_DIRTY_WM_DEPTH_STENCIL         (1ull <<  3)
  77 #define IRIS_DIRTY_CC_VIEWPORT              (1ull <<  4)
  78 #define IRIS_DIRTY_SF_CL_VIEWPORT           (1ull <<  5)
  79 #define IRIS_DIRTY_PS_BLEND                 (1ull <<  6)
  80 #define IRIS_DIRTY_BLEND_STATE              (1ull <<  7)
  81 #define IRIS_DIRTY_RASTER                   (1ull <<  8)
  82 #define IRIS_DIRTY_CLIP                     (1ull <<  9)
  83 #define IRIS_DIRTY_SBE                      (1ull << 10)
  84 #define IRIS_DIRTY_LINE_STIPPLE             (1ull << 11)
  85 #define IRIS_DIRTY_VERTEX_ELEMENTS          (1ull << 12)
  86 #define IRIS_DIRTY_MULTISAMPLE              (1ull << 13)
  87 #define IRIS_DIRTY_VERTEX_BUFFERS           (1ull << 14)
  88 #define IRIS_DIRTY_SAMPLE_MASK              (1ull << 15)
  89 #define IRIS_DIRTY_SAMPLER_STATES_VS        (1ull << 16)
  90 #define IRIS_DIRTY_SAMPLER_STATES_TCS       (1ull << 17)
  91 #define IRIS_DIRTY_SAMPLER_STATES_TES       (1ull << 18)
  92 #define IRIS_DIRTY_SAMPLER_STATES_GS        (1ull << 19)
  93 #define IRIS_DIRTY_SAMPLER_STATES_PS        (1ull << 20)
  94 #define IRIS_DIRTY_SAMPLER_STATES_CS        (1ull << 21)
  95 #define IRIS_DIRTY_UNCOMPILED_VS            (1ull << 22)
  96 #define IRIS_DIRTY_UNCOMPILED_TCS           (1ull << 23)
  97 #define IRIS_DIRTY_UNCOMPILED_TES           (1ull << 24)
  98 #define IRIS_DIRTY_UNCOMPILED_GS            (1ull << 25)
  99 #define IRIS_DIRTY_UNCOMPILED_FS            (1ull << 26)
 100 #define IRIS_DIRTY_UNCOMPILED_CS            (1ull << 27)
 101 #define IRIS_DIRTY_VS                       (1ull << 28)
 102 #define IRIS_DIRTY_TCS                      (1ull << 29)
 103 #define IRIS_DIRTY_TES                      (1ull << 30)
 104 #define IRIS_DIRTY_GS                       (1ull << 31)
 105 #define IRIS_DIRTY_FS                       (1ull << 32)
 106 #define IRIS_DIRTY_CS                       (1ull << 33)
 107 #define IRIS_DIRTY_URB                      (1ull << 34)
 108 #define IRIS_DIRTY_CONSTANTS_VS             (1ull << 35)
 109 #define IRIS_DIRTY_CONSTANTS_TCS            (1ull << 36)
 110 #define IRIS_DIRTY_CONSTANTS_TES            (1ull << 37)
 111 #define IRIS_DIRTY_CONSTANTS_GS             (1ull << 38)
 112 #define IRIS_DIRTY_CONSTANTS_FS             (1ull << 39)
 113 #define IRIS_DIRTY_CONSTANTS_CS             (1ull << 40)
 114 #define IRIS_DIRTY_DEPTH_BUFFER             (1ull << 41)
 115 #define IRIS_DIRTY_WM                       (1ull << 42)
 116 #define IRIS_DIRTY_BINDINGS_VS              (1ull << 43)
 117 #define IRIS_DIRTY_BINDINGS_TCS             (1ull << 44)
 118 #define IRIS_DIRTY_BINDINGS_TES             (1ull << 45)
 119 #define IRIS_DIRTY_BINDINGS_GS              (1ull << 46)
 120 #define IRIS_DIRTY_BINDINGS_FS              (1ull << 47)
 121 #define IRIS_DIRTY_BINDINGS_CS              (1ull << 48)
 122 #define IRIS_DIRTY_SO_BUFFERS               (1ull << 49)
 123 #define IRIS_DIRTY_SO_DECL_LIST             (1ull << 50)
 124 #define IRIS_DIRTY_STREAMOUT                (1ull << 51)
 125 #define IRIS_DIRTY_VF_SGVS                  (1ull << 52)
 126 #define IRIS_DIRTY_VF                       (1ull << 53)
 127 #define IRIS_DIRTY_VF_TOPOLOGY              (1ull << 54)
 128 #define IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES  (1ull << 55)
 129 #define IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES (1ull << 56)
 130 #define IRIS_DIRTY_VF_STATISTICS            (1ull << 57)
 131
 132 #define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_CS | \
 133                                     IRIS_DIRTY_SAMPLER_STATES_CS | \
 134                                     IRIS_DIRTY_UNCOMPILED_CS | \
 135                                     IRIS_DIRTY_CONSTANTS_CS | \
 136                                     IRIS_DIRTY_BINDINGS_CS | \
 137                                     IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES)
 138
 139 #define IRIS_ALL_DIRTY_FOR_RENDER ~IRIS_ALL_DIRTY_FOR_COMPUTE
 140
 141 #define IRIS_ALL_DIRTY_BINDINGS (IRIS_DIRTY_BINDINGS_VS  | \
 142                                  IRIS_DIRTY_BINDINGS_TCS | \
 143                                  IRIS_DIRTY_BINDINGS_TES | \
 144                                  IRIS_DIRTY_BINDINGS_GS  | \
 145                                  IRIS_DIRTY_BINDINGS_FS  | \
 146                                  IRIS_DIRTY_BINDINGS_CS)
 147
 148 /**
 149  * Non-orthogonal state (NOS) dependency flags.
 150  *
 151  * Shader programs may depend on non-orthogonal state.  These flags are
 152  * used to indicate that a shader's key depends on the state provided by
 153  * a certain Gallium CSO.  Changing any CSOs marked as a dependency will
 154  * cause the driver to re-compute the shader key, possibly triggering a
 155  * shader recompile.
 156  */
 157 enum iris_nos_dep {
 158    IRIS_NOS_FRAMEBUFFER,
 159    IRIS_NOS_DEPTH_STENCIL_ALPHA,
 160    IRIS_NOS_RASTERIZER,
 161    IRIS_NOS_BLEND,
 162    IRIS_NOS_LAST_VUE_MAP,
 163
 164    IRIS_NOS_COUNT,
 165 };
 166
 167 struct iris_depth_stencil_alpha_state;
 168
 169 /**
 170  * Cache IDs for the in-memory program cache (ice->shaders.cache).
 171  */
 172 enum iris_program_cache_id {
 173    IRIS_CACHE_VS  = MESA_SHADER_VERTEX,
 174    IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL,
 175    IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL,
 176    IRIS_CACHE_GS  = MESA_SHADER_GEOMETRY,
 177    IRIS_CACHE_FS  = MESA_SHADER_FRAGMENT,
 178    IRIS_CACHE_CS  = MESA_SHADER_COMPUTE,
 179    IRIS_CACHE_BLORP,
 180 };
 181
 182 /** @{
 183  *
 184  * Defines for PIPE_CONTROL operations, which trigger cache flushes,
 185  * synchronization, pipelined memory writes, and so on.
 186  *
 187  * The bits here are not the actual hardware values.  The actual fields
 188  * move between various generations, so we just have flags for each
 189  * potential operation, and use genxml to encode the actual packet.
 190  */
 191 enum pipe_control_flags
 192 {
 193    PIPE_CONTROL_FLUSH_LLC                       = (1 << 1),
 194    PIPE_CONTROL_LRI_POST_SYNC_OP                = (1 << 2),
 195    PIPE_CONTROL_STORE_DATA_INDEX                = (1 << 3),
 196    PIPE_CONTROL_CS_STALL                        = (1 << 4),
 197    PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET     = (1 << 5),
 198    PIPE_CONTROL_SYNC_GFDT                       = (1 << 6),
 199    PIPE_CONTROL_TLB_INVALIDATE                  = (1 << 7),
 200    PIPE_CONTROL_MEDIA_STATE_CLEAR               = (1 << 8),
 201    PIPE_CONTROL_WRITE_IMMEDIATE                 = (1 << 9),
 202    PIPE_CONTROL_WRITE_DEPTH_COUNT               = (1 << 10),
 203    PIPE_CONTROL_WRITE_TIMESTAMP                 = (1 << 11),
 204    PIPE_CONTROL_DEPTH_STALL                     = (1 << 12),
 205    PIPE_CONTROL_RENDER_TARGET_FLUSH             = (1 << 13),
 206    PIPE_CONTROL_INSTRUCTION_INVALIDATE          = (1 << 14),
 207    PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE        = (1 << 15),
 208    PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
 209    PIPE_CONTROL_NOTIFY_ENABLE                   = (1 << 17),
 210    PIPE_CONTROL_FLUSH_ENABLE                    = (1 << 18),
 211    PIPE_CONTROL_DATA_CACHE_FLUSH                = (1 << 19),
 212    PIPE_CONTROL_VF_CACHE_INVALIDATE             = (1 << 20),
 213    PIPE_CONTROL_CONST_CACHE_INVALIDATE          = (1 << 21),
 214    PIPE_CONTROL_STATE_CACHE_INVALIDATE          = (1 << 22),
 215    PIPE_CONTROL_STALL_AT_SCOREBOARD             = (1 << 23),
 216    PIPE_CONTROL_DEPTH_CACHE_FLUSH               = (1 << 24),
 217 };
 218
 219 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
 220    (PIPE_CONTROL_DEPTH_CACHE_FLUSH |  \
 221     PIPE_CONTROL_DATA_CACHE_FLUSH |   \
 222     PIPE_CONTROL_RENDER_TARGET_FLUSH)
 223
 224 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS  \
 225    (PIPE_CONTROL_STATE_CACHE_INVALIDATE |   \
 226     PIPE_CONTROL_CONST_CACHE_INVALIDATE |   \
 227     PIPE_CONTROL_VF_CACHE_INVALIDATE |      \
 228     PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
 229     PIPE_CONTROL_INSTRUCTION_INVALIDATE)
 230
 231 enum iris_predicate_state {
 232    /* The first two states are used if we can determine whether to draw
 233     * without having to look at the values in the query object buffer. This
 234     * will happen if there is no conditional render in progress, if the query
 235     * object is already completed or if something else has already added
 236     * samples to the preliminary result.
 237     */
 238    IRIS_PREDICATE_STATE_RENDER,
 239    IRIS_PREDICATE_STATE_DONT_RENDER,
 240
 241    /* In this case whether to draw or not depends on the result of an
 242     * MI_PREDICATE command so the predicate enable bit needs to be checked.
 243     */
 244    IRIS_PREDICATE_STATE_USE_BIT,
 245 };
 246
 247 /** @} */
 248
 249 /**
 250  * An uncompiled, API-facing shader.  This is the Gallium CSO for shaders.
 251  * It primarily contains the NIR for the shader.
 252  *
 253  * Each API-facing shader can be compiled into multiple shader variants,
 254  * based on non-orthogonal state dependencies, recorded in the shader key.
 255  *
 256  * See iris_compiled_shader, which represents a compiled shader variant.
 257  */
 258 struct iris_uncompiled_shader {
 259    struct nir_shader *nir;
 260
 261    struct pipe_stream_output_info stream_output;
 262
 263    /* A SHA1 of the serialized NIR for the disk cache. */
 264    unsigned char nir_sha1[20];
 265
 266    unsigned program_id;
 267
 268    /** Bitfield of (1 << IRIS_NOS_*) flags. */
 269    unsigned nos;
 270
 271    /** Have any shader variants been compiled yet? */
 272    bool compiled_once;
 273
 274    /** Should we use ALT mode for math?  Useful for ARB programs. */
 275    bool use_alt_mode;
 276
 277    /** Constant data scraped from the shader by nir_opt_large_constants */
 278    struct pipe_resource *const_data;
 279
 280    /** Surface state for const_data */
 281    struct iris_state_ref const_data_state;
 282 };
 283
 284 enum iris_surface_group {
 285    IRIS_SURFACE_GROUP_RENDER_TARGET,
 286    IRIS_SURFACE_GROUP_CS_WORK_GROUPS,
 287    IRIS_SURFACE_GROUP_TEXTURE,
 288    IRIS_SURFACE_GROUP_IMAGE,
 289    IRIS_SURFACE_GROUP_UBO,
 290    IRIS_SURFACE_GROUP_SSBO,
 291
 292    IRIS_SURFACE_GROUP_COUNT,
 293 };
 294
 295 enum {
 296    /* Invalid value for a binding table index. */
 297    IRIS_SURFACE_NOT_USED = 0xa0a0a0a0,
 298 };
 299
 300 struct iris_binding_table {
 301    uint32_t size_bytes;
 302
 303    /** Number of surfaces in each group, before compacting. */
 304    uint32_t sizes[IRIS_SURFACE_GROUP_COUNT];
 305
 306    /** Initial offset of each group. */
 307    uint32_t offsets[IRIS_SURFACE_GROUP_COUNT];
 308
 309    /** Mask of surfaces used in each group. */
 310    uint64_t used_mask[IRIS_SURFACE_GROUP_COUNT];
 311 };
 312
 313 /**
 314  * A compiled shader variant, containing a pointer to the GPU assembly,
 315  * as well as program data and other packets needed by state upload.
 316  *
 317  * There can be several iris_compiled_shader variants per API-level shader
 318  * (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key).
 319  */
 320 struct iris_compiled_shader {
 321    /** Reference to the uploaded assembly. */
 322    struct iris_state_ref assembly;
 323
 324    /** Pointer to the assembly in the BO's map. */
 325    void *map;
 326
 327    /** The program data (owned by the program cache hash table) */
 328    struct brw_stage_prog_data *prog_data;
 329
 330    /** A list of system values to be uploaded as uniforms. */
 331    enum brw_param_builtin *system_values;
 332    unsigned num_system_values;
 333
 334    /** Number of constbufs expected by the shader. */
 335    unsigned num_cbufs;
 336
 337    /**
 338     * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
 339     * (the VUE-based information for transform feedback outputs).
 340     */
 341    uint32_t *streamout;
 342
 343    struct iris_binding_table bt;
 344
 345    /**
 346     * Shader packets and other data derived from prog_data.  These must be
 347     * completely determined from prog_data.
 348     */
 349    uint8_t derived_data[0];
 350 };
 351
 352 /**
 353  * API context state that is replicated per shader stage.
 354  */
 355 struct iris_shader_state {
 356    /** Uniform Buffers */
 357    struct pipe_shader_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
 358    struct iris_state_ref constbuf_surf_state[PIPE_MAX_CONSTANT_BUFFERS];
 359
 360    bool sysvals_need_upload;
 361
 362    /** Shader Storage Buffers */
 363    struct pipe_shader_buffer ssbo[PIPE_MAX_SHADER_BUFFERS];
 364    struct iris_state_ref ssbo_surf_state[PIPE_MAX_SHADER_BUFFERS];
 365
 366    /** Shader Storage Images (image load store) */
 367    struct iris_image_view image[PIPE_MAX_SHADER_IMAGES];
 368
 369    struct iris_state_ref sampler_table;
 370    struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS];
 371    struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS];
 372
 373    /** Bitfield of which constant buffers are bound (non-null). */
 374    uint32_t bound_cbufs;
 375
 376    /** Bitfield of which image views are bound (non-null). */
 377    uint32_t bound_image_views;
 378
 379    /** Bitfield of which sampler views are bound (non-null). */
 380    uint32_t bound_sampler_views;
 381
 382    /** Bitfield of which shader storage buffers are bound (non-null). */
 383    uint32_t bound_ssbos;
 384
 385    /** Bitfield of which shader storage buffers are writable. */
 386    uint32_t writable_ssbos;
 387 };
 388
 389 /**
 390  * Gallium CSO for stream output (transform feedback) targets.
 391  */
 392 struct iris_stream_output_target {
 393    struct pipe_stream_output_target base;
 394
 395    /** Storage holding the offset where we're writing in the buffer */
 396    struct iris_state_ref offset;
 397
 398    /** Stride (bytes-per-vertex) during this transform feedback operation */
 399    uint16_t stride;
 400
 401    /** Has 3DSTATE_SO_BUFFER actually been emitted, zeroing the offsets? */
 402    bool zeroed;
 403 };
 404
 405 /**
 406  * Virtual table for generation-specific (genxml) function calls.
 407  */
 408 struct iris_vtable {
 409    void (*destroy_state)(struct iris_context *ice);
 410    void (*init_render_context)(struct iris_screen *screen,
 411                                struct iris_batch *batch,
 412                                struct iris_vtable *vtbl,
 413                                struct pipe_debug_callback *dbg);
 414    void (*init_compute_context)(struct iris_screen *screen,
 415                                 struct iris_batch *batch,
 416                                 struct iris_vtable *vtbl,
 417                                 struct pipe_debug_callback *dbg);
 418    void (*upload_render_state)(struct iris_context *ice,
 419                                struct iris_batch *batch,
 420                                const struct pipe_draw_info *draw);
 421    void (*update_surface_base_address)(struct iris_batch *batch,
 422                                        struct iris_binder *binder);
 423    void (*upload_compute_state)(struct iris_context *ice,
 424                                 struct iris_batch *batch,
 425                                 const struct pipe_grid_info *grid);
 426    void (*rebind_buffer)(struct iris_context *ice,
 427                          struct iris_resource *res,
 428                          uint64_t old_address);
 429    void (*resolve_conditional_render)(struct iris_context *ice);
 430    void (*load_register_reg32)(struct iris_batch *batch, uint32_t dst,
 431                                uint32_t src);
 432    void (*load_register_reg64)(struct iris_batch *batch, uint32_t dst,
 433                                uint32_t src);
 434    void (*load_register_imm32)(struct iris_batch *batch, uint32_t reg,
 435                                uint32_t val);
 436    void (*load_register_imm64)(struct iris_batch *batch, uint32_t reg,
 437                                uint64_t val);
 438    void (*load_register_mem32)(struct iris_batch *batch, uint32_t reg,
 439                                struct iris_bo *bo, uint32_t offset);
 440    void (*load_register_mem64)(struct iris_batch *batch, uint32_t reg,
 441                                struct iris_bo *bo, uint32_t offset);
 442    void (*store_register_mem32)(struct iris_batch *batch, uint32_t reg,
 443                                 struct iris_bo *bo, uint32_t offset,
 444                                 bool predicated);
 445    void (*store_register_mem64)(struct iris_batch *batch, uint32_t reg,
 446                                 struct iris_bo *bo, uint32_t offset,
 447                                 bool predicated);
 448    void (*store_data_imm32)(struct iris_batch *batch,
 449                             struct iris_bo *bo, uint32_t offset,
 450                             uint32_t value);
 451    void (*store_data_imm64)(struct iris_batch *batch,
 452                             struct iris_bo *bo, uint32_t offset,
 453                             uint64_t value);
 454    void (*copy_mem_mem)(struct iris_batch *batch,
 455                         struct iris_bo *dst_bo, uint32_t dst_offset,
 456                         struct iris_bo *src_bo, uint32_t src_offset,
 457                         unsigned bytes);
 458    void (*emit_raw_pipe_control)(struct iris_batch *batch,
 459                                  const char *reason, uint32_t flags,
 460                                  struct iris_bo *bo, uint32_t offset,
 461                                  uint64_t imm);
 462
 463    unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
 464    void (*store_derived_program_state)(struct iris_context *ice,
 465                                        enum iris_program_cache_id cache_id,
 466                                        struct iris_compiled_shader *shader);
 467    uint32_t *(*create_so_decl_list)(const struct pipe_stream_output_info *sol,
 468                                     const struct brw_vue_map *vue_map);
 469    void (*populate_vs_key)(const struct iris_context *ice,
 470                            const struct shader_info *info,
 471                            struct brw_vs_prog_key *key);
 472    void (*populate_tcs_key)(const struct iris_context *ice,
 473                             struct brw_tcs_prog_key *key);
 474    void (*populate_tes_key)(const struct iris_context *ice,
 475                             struct brw_tes_prog_key *key);
 476    void (*populate_gs_key)(const struct iris_context *ice,
 477                            struct brw_gs_prog_key *key);
 478    void (*populate_fs_key)(const struct iris_context *ice,
 479                            const struct shader_info *info,
 480                            struct brw_wm_prog_key *key);
 481    void (*populate_cs_key)(const struct iris_context *ice,
 482                            struct brw_cs_prog_key *key);
 483    uint32_t (*mocs)(const struct iris_bo *bo);
 484 };
 485
 486 /**
 487  * A pool containing SAMPLER_BORDER_COLOR_STATE entries.
 488  *
 489  * See iris_border_color.c for more information.
 490  */
 491 struct iris_border_color_pool {
 492    struct iris_bo *bo;
 493    void *map;
 494    unsigned insert_point;
 495
 496    /** Map from border colors to offsets in the buffer. */
 497    struct hash_table *ht;
 498 };
 499
 500 /**
 501  * The API context (derived from pipe_context).
 502  *
 503  * Most driver state is tracked here.
 504  */
 505 struct iris_context {
 506    struct pipe_context ctx;
 507
 508    /** A debug callback for KHR_debug output. */
 509    struct pipe_debug_callback dbg;
 510
 511    /** A device reset status callback for notifying that the GPU is hosed. */
 512    struct pipe_device_reset_callback reset;
 513
 514    /** Slab allocator for iris_transfer_map objects. */
 515    struct slab_child_pool transfer_pool;
 516
 517    struct iris_vtable vtbl;
 518
 519    struct blorp_context blorp;
 520
 521    struct iris_batch batches[IRIS_BATCH_COUNT];
 522
 523    struct u_upload_mgr *query_buffer_uploader;
 524
 525    struct {
 526       struct {
 527          /**
 528           * Either the value of BaseVertex for indexed draw calls or the value
 529           * of the argument <first> for non-indexed draw calls.
 530           */
 531          int firstvertex;
 532          int baseinstance;
 533       } params;
 534
 535       /**
 536        * Resource and offset that stores draw_parameters from the indirect
 537        * buffer or to the buffer that stures the previous values for non
 538        * indirect draws.
 539        */
 540       struct pipe_resource *draw_params_res;
 541       uint32_t draw_params_offset;
 542
 543       struct {
 544          /**
 545           * The value of DrawID. This always comes in from it's own vertex
 546           * buffer since it's not part of the indirect draw parameters.
 547           */
 548          int drawid;
 549
 550          /**
 551           * Stores if an indexed or non-indexed draw (~0/0). Useful to
 552           * calculate BaseVertex as an AND of firstvertex and is_indexed_draw.
 553           */
 554          int is_indexed_draw;
 555       } derived_params;
 556
 557       /**
 558        * Resource and offset used for GL_ARB_shader_draw_parameters which
 559        * contains parameters that are not present in the indirect buffer as
 560        * drawid and is_indexed_draw. They will go in their own vertex element.
 561        */
 562       struct pipe_resource *derived_draw_params_res;
 563       uint32_t derived_draw_params_offset;
 564
 565       bool is_indirect;
 566    } draw;
 567
 568    struct {
 569       struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
 570       struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
 571       struct brw_vue_map *last_vue_map;
 572
 573       struct u_upload_mgr *uploader;
 574       struct hash_table *cache;
 575
 576       unsigned urb_size;
 577
 578       /** Is a GS or TES outputting points or lines? */
 579       bool output_topology_is_points_or_lines;
 580
 581       /* Track last VS URB entry size */
 582       unsigned last_vs_entry_size;
 583
 584       /**
 585        * Scratch buffers for various sizes and stages.
 586        *
 587        * Indexed by the "Per-Thread Scratch Space" field's 4-bit encoding,
 588        * and shader stage.
 589        */
 590       struct iris_bo *scratch_bos[1 << 4][MESA_SHADER_STAGES];
 591    } shaders;
 592
 593    struct {
 594       struct iris_query *query;
 595       bool condition;
 596    } condition;
 597
 598    struct {
 599       uint64_t dirty;
 600       uint64_t dirty_for_nos[IRIS_NOS_COUNT];
 601
 602       unsigned num_viewports;
 603       unsigned sample_mask;
 604       struct iris_blend_state *cso_blend;
 605       struct iris_rasterizer_state *cso_rast;
 606       struct iris_depth_stencil_alpha_state *cso_zsa;
 607       struct iris_vertex_element_state *cso_vertex_elements;
 608       struct pipe_blend_color blend_color;
 609       struct pipe_poly_stipple poly_stipple;
 610       struct pipe_viewport_state viewports[IRIS_MAX_VIEWPORTS];
 611       struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
 612       struct pipe_stencil_ref stencil_ref;
 613       struct pipe_framebuffer_state framebuffer;
 614       struct pipe_clip_state clip_planes;
 615
 616       float default_outer_level[4];
 617       float default_inner_level[2];
 618
 619       /** Bitfield of which vertex buffers are bound (non-null). */
 620       uint64_t bound_vertex_buffers;
 621
 622       bool primitive_restart;
 623       unsigned cut_index;
 624       enum pipe_prim_type prim_mode:8;
 625       bool prim_is_points_or_lines;
 626       uint8_t vertices_per_patch;
 627
 628       /** The last compute grid size */
 629       uint32_t last_grid[3];
 630       /** Reference to the BO containing the compute grid size */
 631       struct iris_state_ref grid_size;
 632       /** Reference to the SURFACE_STATE for the compute grid resource */
 633       struct iris_state_ref grid_surf_state;
 634
 635       /**
 636        * Array of aux usages for drawing, altered to account for any
 637        * self-dependencies from resources bound for sampling and rendering.
 638        */
 639       enum isl_aux_usage draw_aux_usage[BRW_MAX_DRAW_BUFFERS];
 640
 641       /** Bitfield of whether color blending is enabled for RT[i] */
 642       uint8_t blend_enables;
 643
 644       /** Are depth writes enabled?  (Depth buffer may or may not exist.) */
 645       bool depth_writes_enabled;
 646
 647       /** Are stencil writes enabled?  (Stencil buffer may or may not exist.) */
 648       bool stencil_writes_enabled;
 649
 650       /** GenX-specific current state */
 651       struct iris_genx_state *genx;
 652
 653       struct iris_shader_state shaders[MESA_SHADER_STAGES];
 654
 655       /** Do vertex shader uses shader draw parameters ? */
 656       bool vs_uses_draw_params;
 657       bool vs_uses_derived_draw_params;
 658       bool vs_needs_sgvs_element;
 659
 660       /** Do vertex shader uses edge flag ? */
 661       bool vs_needs_edge_flag;
 662
 663       /** Do any samplers need border color?  One bit per shader stage. */
 664       uint8_t need_border_colors;
 665
 666       struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS];
 667       bool streamout_active;
 668
 669       bool statistics_counters_enabled;
 670
 671       /** Current conditional rendering mode */
 672       enum iris_predicate_state predicate;
 673
 674       /**
 675        * Query BO with a MI_PREDICATE_RESULT snapshot calculated on the
 676        * render context that needs to be uploaded to the compute context.
 677        */
 678       struct iris_bo *compute_predicate;
 679
 680       /** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */
 681       bool prims_generated_query_active;
 682
 683       /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
 684       uint32_t *streamout;
 685
 686       /** The SURFACE_STATE for a 1x1x1 null surface. */
 687       struct iris_state_ref unbound_tex;
 688
 689       /** The SURFACE_STATE for a framebuffer-sized null surface. */
 690       struct iris_state_ref null_fb;
 691
 692       struct u_upload_mgr *surface_uploader;
 693       struct u_upload_mgr *dynamic_uploader;
 694
 695       struct iris_binder binder;
 696
 697       struct iris_border_color_pool border_color_pool;
 698
 699       /** The high 16-bits of the last VBO/index buffer addresses */
 700       uint16_t last_vbo_high_bits[33];
 701       uint16_t last_index_bo_high_bits;
 702
 703       /**
 704        * Resources containing streamed state which our render context
 705        * currently points to.  Used to re-add these to the validation
 706        * list when we start a new batch and haven't resubmitted commands.
 707        */
 708       struct {
 709          struct pipe_resource *cc_vp;
 710          struct pipe_resource *sf_cl_vp;
 711          struct pipe_resource *color_calc;
 712          struct pipe_resource *scissor;
 713          struct pipe_resource *blend;
 714          struct pipe_resource *index_buffer;
 715          struct pipe_resource *cs_thread_ids;
 716          struct pipe_resource *cs_desc;
 717       } last_res;
 718
 719       /** Records the size of variable-length state for INTEL_DEBUG=bat */
 720       struct hash_table_u64 *sizes;
 721    } state;
 722 };
 723
 724 #define perf_debug(dbg, ...) do {                      \
 725    if (INTEL_DEBUG & DEBUG_PERF)                       \
 726       dbg_printf(__VA_ARGS__);                         \
 727    if (unlikely(dbg))                                  \
 728       pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
 729 } while(0)
 730
 731 double get_time(void);
 732
 733 struct pipe_context *
 734 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
 735
 736 void iris_lost_context_state(struct iris_batch *batch);
 737
 738 void iris_init_blit_functions(struct pipe_context *ctx);
 739 void iris_init_clear_functions(struct pipe_context *ctx);
 740 void iris_init_program_functions(struct pipe_context *ctx);
 741 void iris_init_resource_functions(struct pipe_context *ctx);
 742 void iris_update_compiled_shaders(struct iris_context *ice);
 743 void iris_update_compiled_compute_shader(struct iris_context *ice);
 744 void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data,
 745                                     uint32_t *dst);
 746
 747
 748 /* iris_blit.c */
 749 void iris_blorp_surf_for_resource(struct iris_vtable *vtbl,
 750                                   struct blorp_surf *surf,
 751                                   struct pipe_resource *p_res,
 752                                   enum isl_aux_usage aux_usage,
 753                                   unsigned level,
 754                                   bool is_render_target);
 755 void iris_copy_region(struct blorp_context *blorp,
 756                       struct iris_batch *batch,
 757                       struct pipe_resource *dst,
 758                       unsigned dst_level,
 759                       unsigned dstx, unsigned dsty, unsigned dstz,
 760                       struct pipe_resource *src,
 761                       unsigned src_level,
 762                       const struct pipe_box *src_box);
 763
 764 /* iris_draw.c */
 765
 766 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 767 void iris_launch_grid(struct pipe_context *, const struct pipe_grid_info *);
 768
 769 /* iris_pipe_control.c */
 770
 771 void iris_emit_pipe_control_flush(struct iris_batch *batch,
 772                                   const char *reason, uint32_t flags);
 773 void iris_emit_pipe_control_write(struct iris_batch *batch,
 774                                   const char *reason, uint32_t flags,
 775                                   struct iris_bo *bo, uint32_t offset,
 776                                   uint64_t imm);
 777 void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
 778                                 const char *reason, uint32_t flags);
 779
 780 void iris_init_flush_functions(struct pipe_context *ctx);
 781
 782 /* iris_border_color.c */
 783
 784 void iris_init_border_color_pool(struct iris_context *ice);
 785 void iris_destroy_border_color_pool(struct iris_context *ice);
 786 void iris_border_color_pool_reserve(struct iris_context *ice, unsigned count);
 787 uint32_t iris_upload_border_color(struct iris_context *ice,
 788                                   union pipe_color_union *color);
 789
 790 /* iris_program.c */
 791 void iris_upload_ubo_ssbo_surf_state(struct iris_context *ice,
 792                                      struct pipe_shader_buffer *buf,
 793                                      struct iris_state_ref *surf_state,
 794                                      bool ssbo);
 795 const struct shader_info *iris_get_shader_info(const struct iris_context *ice,
 796                                                gl_shader_stage stage);
 797 struct iris_bo *iris_get_scratch_space(struct iris_context *ice,
 798                                        unsigned per_thread_scratch,
 799                                        gl_shader_stage stage);
 800 uint32_t iris_group_index_to_bti(const struct iris_binding_table *bt,
 801                                  enum iris_surface_group group,
 802                                  uint32_t index);
 803 uint32_t iris_bti_to_group_index(const struct iris_binding_table *bt,
 804                                  enum iris_surface_group group,
 805                                  uint32_t bti);
 806
 807 /* iris_disk_cache.c */
 808
 809 void iris_disk_cache_store(struct disk_cache *cache,
 810                            const struct iris_uncompiled_shader *ish,
 811                            const struct iris_compiled_shader *shader,
 812                            const void *prog_key,
 813                            uint32_t prog_key_size);
 814 struct iris_compiled_shader *
 815 iris_disk_cache_retrieve(struct iris_context *ice,
 816                          const struct iris_uncompiled_shader *ish,
 817                          const void *prog_key,
 818                          uint32_t prog_key_size);
 819
 820 /* iris_program_cache.c */
 821
 822 void iris_init_program_cache(struct iris_context *ice);
 823 void iris_destroy_program_cache(struct iris_context *ice);
 824 void iris_print_program_cache(struct iris_context *ice);
 825 struct iris_compiled_shader *iris_find_cached_shader(struct iris_context *ice,
 826                                                      enum iris_program_cache_id,
 827                                                      uint32_t key_size,
 828                                                      const void *key);
 829 struct iris_compiled_shader *iris_upload_shader(struct iris_context *ice,
 830                                                 enum iris_program_cache_id,
 831                                                 uint32_t key_size,
 832                                                 const void *key,
 833                                                 const void *assembly,
 834                                                 struct brw_stage_prog_data *,
 835                                                 uint32_t *streamout,
 836                                                 enum brw_param_builtin *sysv,
 837                                                 unsigned num_system_values,
 838                                                 unsigned num_cbufs,
 839                                                 const struct iris_binding_table *bt);
 840 const void *iris_find_previous_compile(const struct iris_context *ice,
 841                                        enum iris_program_cache_id cache_id,
 842                                        unsigned program_string_id);
 843 bool iris_blorp_lookup_shader(struct blorp_batch *blorp_batch,
 844                               const void *key,
 845                               uint32_t key_size,
 846                               uint32_t *kernel_out,
 847                               void *prog_data_out);
 848 bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch,
 849                               const void *key, uint32_t key_size,
 850                               const void *kernel, uint32_t kernel_size,
 851                               const struct brw_stage_prog_data *prog_data,
 852                               uint32_t prog_data_size,
 853                               uint32_t *kernel_out,
 854                               void *prog_data_out);
 855
 856 /* iris_query.c */
 857
 858 void iris_math_div32_gpr0(struct iris_context *ice,
 859                           struct iris_batch *batch,
 860                           uint32_t D);
 861 void iris_math_add32_gpr0(struct iris_context *ice,
 862                           struct iris_batch *batch,
 863                           uint32_t x);
 864
 865 /* iris_resolve.c */
 866
 867 void iris_predraw_resolve_inputs(struct iris_context *ice,
 868                                  struct iris_batch *batch,
 869                                  bool *draw_aux_buffer_disabled,
 870                                  gl_shader_stage stage,
 871                                  bool consider_framebuffer);
 872 void iris_predraw_resolve_framebuffer(struct iris_context *ice,
 873                                       struct iris_batch *batch,
 874                                       bool *draw_aux_buffer_disabled);
 875 void iris_postdraw_update_resolve_tracking(struct iris_context *ice,
 876                                            struct iris_batch *batch);
 877 void iris_cache_sets_clear(struct iris_batch *batch);
 878 void iris_flush_depth_and_render_caches(struct iris_batch *batch);
 879 void iris_cache_flush_for_read(struct iris_batch *batch, struct iris_bo *bo);
 880 void iris_cache_flush_for_render(struct iris_batch *batch,
 881                                  struct iris_bo *bo,
 882                                  enum isl_format format,
 883                                  enum isl_aux_usage aux_usage);
 884 void iris_render_cache_add_bo(struct iris_batch *batch,
 885                               struct iris_bo *bo,
 886                               enum isl_format format,
 887                               enum isl_aux_usage aux_usage);
 888 void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
 889 void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
 890
 891 /* iris_state.c */
 892 void gen9_toggle_preemption(struct iris_context *ice,
 893                             struct iris_batch *batch,
 894                             const struct pipe_draw_info *draw);
 895
 896 #ifdef genX
 897 #  include "iris_genx_protos.h"
 898 #else
 899 #  define genX(x) gen4_##x
 900 #  include "iris_genx_protos.h"
 901 #  undef genX
 902 #  define genX(x) gen5_##x
 903 #  include "iris_genx_protos.h"
 904 #  undef genX
 905 #  define genX(x) gen6_##x
 906 #  include "iris_genx_protos.h"
 907 #  undef genX
 908 #  define genX(x) gen7_##x
 909 #  include "iris_genx_protos.h"
 910 #  undef genX
 911 #  define genX(x) gen75_##x
 912 #  include "iris_genx_protos.h"
 913 #  undef genX
 914 #  define genX(x) gen8_##x
 915 #  include "iris_genx_protos.h"
 916 #  undef genX
 917 #  define genX(x) gen9_##x
 918 #  include "iris_genx_protos.h"
 919 #  undef genX
 920 #  define genX(x) gen10_##x
 921 #  include "iris_genx_protos.h"
 922 #  undef genX
 923 #  define genX(x) gen11_##x
 924 #  include "iris_genx_protos.h"
 925 #  undef genX
 926 #endif
 927
 928 #endif